1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * cs35l45.h - CS35L45 ALSA SoC audio driver 4 * 5 * Copyright 2019-2022 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * 9 */ 10 11 #ifndef CS35L45_H 12 #define CS35L45_H 13 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 #include <dt-bindings/sound/cs35l45.h> 18 19 #define CS35L45_DEVID 0x00000000 20 #define CS35L45_REVID 0x00000004 21 #define CS35L45_RELID 0x0000000C 22 #define CS35L45_OTPID 0x00000010 23 #define CS35L45_SFT_RESET 0x00000020 24 #define CS35L45_GLOBAL_ENABLES 0x00002014 25 #define CS35L45_BLOCK_ENABLES 0x00002018 26 #define CS35L45_BLOCK_ENABLES2 0x0000201C 27 #define CS35L45_ERROR_RELEASE 0x00002034 28 #define CS35L45_SYNC_GPIO1 0x00002430 29 #define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434 30 #define CS35L45_GPIO3 0x00002438 31 #define CS35L45_REFCLK_INPUT 0x00002C04 32 #define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C 33 #define CS35L45_BOOST_CCM_CFG 0x00003808 34 #define CS35L45_BOOST_DCM_CFG 0x0000380C 35 #define CS35L45_BOOST_OV_CFG 0x0000382C 36 #define CS35L45_ASP_ENABLES1 0x00004800 37 #define CS35L45_ASP_CONTROL1 0x00004804 38 #define CS35L45_ASP_CONTROL2 0x00004808 39 #define CS35L45_ASP_CONTROL3 0x0000480C 40 #define CS35L45_ASP_FRAME_CONTROL1 0x00004810 41 #define CS35L45_ASP_FRAME_CONTROL2 0x00004814 42 #define CS35L45_ASP_FRAME_CONTROL5 0x00004820 43 #define CS35L45_ASP_DATA_CONTROL1 0x00004830 44 #define CS35L45_ASP_DATA_CONTROL5 0x00004840 45 #define CS35L45_DACPCM1_INPUT 0x00004C00 46 #define CS35L45_ASPTX1_INPUT 0x00004C20 47 #define CS35L45_ASPTX2_INPUT 0x00004C24 48 #define CS35L45_ASPTX3_INPUT 0x00004C28 49 #define CS35L45_ASPTX4_INPUT 0x00004C2C 50 #define CS35L45_ASPTX5_INPUT 0x00004C30 51 #define CS35L45_LDPM_CONFIG 0x00006404 52 #define CS35L45_AMP_PCM_CONTROL 0x00007000 53 #define CS35L45_AMP_PCM_HPF_TST 0x00007004 54 #define CS35L45_IRQ1_CFG 0x0000E000 55 #define CS35L45_IRQ1_STATUS 0x0000E004 56 #define CS35L45_IRQ1_EINT_1 0x0000E010 57 #define CS35L45_IRQ1_EINT_2 0x0000E014 58 #define CS35L45_IRQ1_EINT_3 0x0000E018 59 #define CS35L45_IRQ1_EINT_4 0x0000E01C 60 #define CS35L45_IRQ1_EINT_5 0x0000E020 61 #define CS35L45_IRQ1_EINT_7 0x0000E028 62 #define CS35L45_IRQ1_EINT_8 0x0000E02C 63 #define CS35L45_IRQ1_EINT_18 0x0000E054 64 #define CS35L45_IRQ1_STS_1 0x0000E090 65 #define CS35L45_IRQ1_STS_2 0x0000E094 66 #define CS35L45_IRQ1_STS_3 0x0000E098 67 #define CS35L45_IRQ1_STS_4 0x0000E09C 68 #define CS35L45_IRQ1_STS_5 0x0000E0A0 69 #define CS35L45_IRQ1_STS_7 0x0000E0A8 70 #define CS35L45_IRQ1_STS_8 0x0000E0AC 71 #define CS35L45_IRQ1_STS_18 0x0000E0D4 72 #define CS35L45_IRQ1_MASK_1 0x0000E110 73 #define CS35L45_IRQ1_MASK_2 0x0000E114 74 #define CS35L45_IRQ1_MASK_3 0x0000E118 75 #define CS35L45_IRQ1_MASK_4 0x0000E11C 76 #define CS35L45_IRQ1_MASK_5 0x0000E120 77 #define CS35L45_IRQ1_MASK_6 0x0000E124 78 #define CS35L45_IRQ1_MASK_7 0x0000E128 79 #define CS35L45_IRQ1_MASK_8 0x0000E12C 80 #define CS35L45_IRQ1_MASK_9 0x0000E130 81 #define CS35L45_IRQ1_MASK_10 0x0000E134 82 #define CS35L45_IRQ1_MASK_11 0x0000E138 83 #define CS35L45_IRQ1_MASK_12 0x0000E13C 84 #define CS35L45_IRQ1_MASK_13 0x0000E140 85 #define CS35L45_IRQ1_MASK_14 0x0000E144 86 #define CS35L45_IRQ1_MASK_15 0x0000E148 87 #define CS35L45_IRQ1_MASK_16 0x0000E14C 88 #define CS35L45_IRQ1_MASK_17 0x0000E150 89 #define CS35L45_IRQ1_MASK_18 0x0000E154 90 #define CS35L45_GPIO_STATUS1 0x0000F000 91 #define CS35L45_GPIO1_CTRL1 0x0000F008 92 #define CS35L45_GPIO2_CTRL1 0x0000F00C 93 #define CS35L45_GPIO3_CTRL1 0x0000F010 94 #define CS35L45_LASTREG 0x0000F010 95 /* SFT_RESET */ 96 #define CS35L45_SOFT_RESET_TRIGGER 0x5A000000 97 98 /* GLOBAL_ENABLES */ 99 #define CS35L45_GLOBAL_EN_SHIFT 0 100 #define CS35L45_GLOBAL_EN_MASK BIT(0) 101 102 /* BLOCK_ENABLES */ 103 #define CS35L45_IMON_EN_SHIFT 13 104 #define CS35L45_VMON_EN_SHIFT 12 105 #define CS35L45_VDD_BSTMON_EN_SHIFT 9 106 #define CS35L45_VDD_BATTMON_EN_SHIFT 8 107 #define CS35L45_BST_EN_SHIFT 4 108 #define CS35L45_BST_EN_MASK GENMASK(5, 4) 109 110 #define CS35L45_BST_DISABLE_FET_ON 0x01 111 112 /* BLOCK_ENABLES2 */ 113 #define CS35L45_ASP_EN_SHIFT 27 114 115 /* ERROR_RELEASE */ 116 #define CS35L45_GLOBAL_ERR_RLS_MASK BIT(11) 117 118 /* REFCLK_INPUT */ 119 #define CS35L45_PLL_FORCE_EN_SHIFT 16 120 #define CS35L45_PLL_FORCE_EN_MASK BIT(16) 121 #define CS35L45_PLL_OPEN_LOOP_SHIFT 11 122 #define CS35L45_PLL_OPEN_LOOP_MASK BIT(11) 123 #define CS35L45_PLL_REFCLK_FREQ_SHIFT 5 124 #define CS35L45_PLL_REFCLK_FREQ_MASK GENMASK(10, 5) 125 #define CS35L45_PLL_REFCLK_EN_SHIFT 4 126 #define CS35L45_PLL_REFCLK_EN_MASK BIT(4) 127 #define CS35L45_PLL_REFCLK_SEL_SHIFT 0 128 #define CS35L45_PLL_REFCLK_SEL_MASK GENMASK(2, 0) 129 130 #define CS35L45_PLL_REFCLK_SEL_BCLK 0x0 131 132 /* GLOBAL_SAMPLE_RATE */ 133 #define CS35L45_GLOBAL_FS_SHIFT 0 134 #define CS35L45_GLOBAL_FS_MASK GENMASK(4, 0) 135 136 #define CS35L45_48P0_KHZ 0x03 137 #define CS35L45_96P0_KHZ 0x04 138 #define CS35L45_44P100_KHZ 0x0B 139 #define CS35L45_88P200_KHZ 0x0C 140 141 /* ASP_ENABLES_1 */ 142 #define CS35L45_ASP_RX2_EN_SHIFT 17 143 #define CS35L45_ASP_RX1_EN_SHIFT 16 144 #define CS35L45_ASP_TX5_EN_SHIFT 4 145 #define CS35L45_ASP_TX4_EN_SHIFT 3 146 #define CS35L45_ASP_TX3_EN_SHIFT 2 147 #define CS35L45_ASP_TX2_EN_SHIFT 1 148 #define CS35L45_ASP_TX1_EN_SHIFT 0 149 150 /* ASP_CONTROL2 */ 151 #define CS35L45_ASP_WIDTH_RX_SHIFT 24 152 #define CS35L45_ASP_WIDTH_RX_MASK GENMASK(31, 24) 153 #define CS35L45_ASP_WIDTH_TX_SHIFT 16 154 #define CS35L45_ASP_WIDTH_TX_MASK GENMASK(23, 16) 155 #define CS35L45_ASP_FMT_SHIFT 8 156 #define CS35L45_ASP_FMT_MASK GENMASK(10, 8) 157 #define CS35L45_ASP_BCLK_INV_SHIFT 6 158 #define CS35L45_ASP_BCLK_INV_MASK BIT(6) 159 #define CS35L45_ASP_FSYNC_INV_SHIFT 2 160 #define CS35L45_ASP_FSYNC_INV_MASK BIT(2) 161 162 #define CS35l45_ASP_FMT_DSP_A 0 163 #define CS35L45_ASP_FMT_I2S 2 164 165 /* ASP_CONTROL3 */ 166 #define CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT 0 167 #define CS35L45_ASP_DOUT_HIZ_CTRL_MASK GENMASK(1, 0) 168 169 /* ASP_FRAME_CONTROL1 */ 170 #define CS35L45_ASP_TX4_SLOT_SHIFT 24 171 #define CS35L45_ASP_TX4_SLOT_MASK GENMASK(29, 24) 172 #define CS35L45_ASP_TX3_SLOT_SHIFT 16 173 #define CS35L45_ASP_TX3_SLOT_MASK GENMASK(21, 16) 174 #define CS35L45_ASP_TX2_SLOT_SHIFT 8 175 #define CS35L45_ASP_TX2_SLOT_MASK GENMASK(13, 8) 176 #define CS35L45_ASP_TX1_SLOT_SHIFT 0 177 #define CS35L45_ASP_TX1_SLOT_MASK GENMASK(5, 0) 178 179 #define CS35L45_ASP_TX_ALL_SLOTS (CS35L45_ASP_TX4_SLOT_MASK | \ 180 CS35L45_ASP_TX3_SLOT_MASK | \ 181 CS35L45_ASP_TX2_SLOT_MASK | \ 182 CS35L45_ASP_TX1_SLOT_MASK) 183 /* ASP_FRAME_CONTROL5 */ 184 #define CS35L45_ASP_RX2_SLOT_SHIFT 8 185 #define CS35L45_ASP_RX2_SLOT_MASK GENMASK(13, 8) 186 #define CS35L45_ASP_RX1_SLOT_SHIFT 0 187 #define CS35L45_ASP_RX1_SLOT_MASK GENMASK(5, 0) 188 189 #define CS35L45_ASP_RX_ALL_SLOTS (CS35L45_ASP_RX2_SLOT_MASK | \ 190 CS35L45_ASP_RX1_SLOT_MASK) 191 192 /* ASP_DATA_CONTROL1 */ 193 /* ASP_DATA_CONTROL5 */ 194 #define CS35L45_ASP_WL_SHIFT 0 195 #define CS35L45_ASP_WL_MASK GENMASK(5, 0) 196 197 /* AMP_PCM_CONTROL */ 198 #define CS35L45_AMP_VOL_PCM_SHIFT 0 199 #define CS35L45_AMP_VOL_PCM_WIDTH 11 200 201 /* AMP_PCM_HPF_TST */ 202 #define CS35l45_HPF_DEFAULT 0x00000000 203 #define CS35L45_HPF_44P1 0x000108BD 204 #define CS35L45_HPF_88P2 0x0001045F 205 206 /* IRQ1_EINT_4 */ 207 #define CS35L45_OTP_BOOT_DONE_STS_MASK BIT(1) 208 #define CS35L45_OTP_BUSY_MASK BIT(0) 209 210 /* GPIOX_CTRL1 */ 211 #define CS35L45_GPIO_DIR_SHIFT 31 212 #define CS35L45_GPIO_DIR_MASK BIT(31) 213 #define CS35L45_GPIO_LVL_SHIFT 15 214 #define CS35L45_GPIO_LVL_MASK BIT(15) 215 #define CS35L45_GPIO_OP_CFG_SHIFT 14 216 #define CS35L45_GPIO_OP_CFG_MASK BIT(14) 217 #define CS35L45_GPIO_POL_SHIFT 12 218 #define CS35L45_GPIO_POL_MASK BIT(12) 219 220 /* SYNC_GPIO1, INTB_GPIO2_MCLK_REF, GPIO3 */ 221 #define CS35L45_GPIO_CTRL_SHIFT 20 222 #define CS35L45_GPIO_CTRL_MASK GENMASK(22, 20) 223 #define CS35L45_GPIO_INVERT_SHIFT 19 224 #define CS35L45_GPIO_INVERT_MASK BIT(19) 225 226 /* CS35L45_IRQ1_EINT_1 */ 227 #define CS35L45_BST_UVP_ERR_SHIFT 7 228 #define CS35L45_BST_UVP_ERR_MASK BIT(7) 229 #define CS35L45_BST_SHORT_ERR_SHIFT 8 230 #define CS35L45_BST_SHORT_ERR_MASK BIT(8) 231 #define CS35L45_TEMP_ERR_SHIFT 17 232 #define CS35L45_TEMP_ERR_MASK BIT(17) 233 #define CS35L45_MSM_GLOBAL_EN_ASSERT_SHIFT 22 234 #define CS35L45_MSM_GLOBAL_EN_ASSERT_MASK BIT(22) 235 #define CS35L45_UVLO_VDDBATT_ERR_SHIFT 29 236 #define CS35L45_UVLO_VDDBATT_ERR_MASK BIT(29) 237 #define CS35L45_AMP_SHORT_ERR_SHIFT 31 238 #define CS35L45_AMP_SHORT_ERR_MASK BIT(31) 239 240 /* CS35L45_IRQ1_EINT_2 */ 241 #define CS35L45_DSP_WDT_EXPIRE_SHIFT 4 242 #define CS35L45_DSP_WDT_EXPIRE_MASK BIT(4) 243 244 /* CS35L45_IRQ1_EINT_3 */ 245 #define CS35L45_PLL_LOCK_FLAG_SHIFT 1 246 #define CS35L45_PLL_LOCK_FLAG_MASK BIT(1) 247 #define CS35L45_PLL_UNLOCK_FLAG_RISE_SHIFT 4 248 #define CS35L45_PLL_UNLOCK_FLAG_RISE_MASK BIT(4) 249 #define CS35L45_AMP_CAL_ERR_SHIFT 25 250 #define CS35L45_AMP_CAL_ERR_MASK BIT(25) 251 252 /* CS35L45_IRQ1_EINT_18 */ 253 #define CS35L45_GLOBAL_ERROR_SHIFT 15 254 #define CS35L45_GLOBAL_ERROR_MASK BIT(15) 255 #define CS35L45_UVLO_VDDLV_ERR_SHIFT 16 256 #define CS35L45_UVLO_VDDLV_ERR_MASK BIT(16) 257 258 /* Mixer sources */ 259 #define CS35L45_PCM_SRC_MASK 0x7F 260 #define CS35L45_PCM_SRC_ZERO 0x00 261 #define CS35L45_PCM_SRC_ASP_RX1 0x08 262 #define CS35L45_PCM_SRC_ASP_RX2 0x09 263 #define CS35L45_PCM_SRC_VMON 0x18 264 #define CS35L45_PCM_SRC_IMON 0x19 265 #define CS35L45_PCM_SRC_ERR_VOL 0x20 266 #define CS35L45_PCM_SRC_CLASSH_TGT 0x21 267 #define CS35L45_PCM_SRC_VDD_BATTMON 0x28 268 #define CS35L45_PCM_SRC_VDD_BSTMON 0x29 269 #define CS35L45_PCM_SRC_TEMPMON 0x3A 270 #define CS35L45_PCM_SRC_INTERPOLATOR 0x40 271 #define CS35L45_PCM_SRC_IL_TARGET 0x48 272 273 #define CS35L45_RESET_HOLD_US 2000 274 #define CS35L45_RESET_US 2000 275 #define CS35L45_POST_GLOBAL_EN_US 5000 276 #define CS35L45_PRE_GLOBAL_DIS_US 3000 277 278 #define CS35L45_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 279 SNDRV_PCM_FMTBIT_S24_3LE| \ 280 SNDRV_PCM_FMTBIT_S24_LE) 281 282 #define CS35L45_RATES (SNDRV_PCM_RATE_44100 | \ 283 SNDRV_PCM_RATE_48000 | \ 284 SNDRV_PCM_RATE_88200 | \ 285 SNDRV_PCM_RATE_96000) 286 287 /* 288 * IRQs 289 */ 290 #define CS35L45_IRQ(_irq, _name, _hand) \ 291 { \ 292 .irq = CS35L45_ ## _irq ## _IRQ,\ 293 .name = _name, \ 294 .handler = _hand, \ 295 } 296 297 struct cs35l45_irq { 298 int irq; 299 const char *name; 300 irqreturn_t (*handler)(int irq, void *data); 301 }; 302 303 #define CS35L45_REG_IRQ(_reg, _irq) \ 304 [CS35L45_ ## _irq ## _IRQ] = { \ 305 .reg_offset = (CS35L45_ ## _reg) - CS35L45_IRQ1_EINT_1, \ 306 .mask = CS35L45_ ## _irq ## _MASK \ 307 } 308 309 enum cs35l45_irq_list { 310 CS35L45_AMP_SHORT_ERR_IRQ, 311 CS35L45_UVLO_VDDBATT_ERR_IRQ, 312 CS35L45_BST_SHORT_ERR_IRQ, 313 CS35L45_BST_UVP_ERR_IRQ, 314 CS35L45_TEMP_ERR_IRQ, 315 CS35L45_AMP_CAL_ERR_IRQ, 316 CS35L45_UVLO_VDDLV_ERR_IRQ, 317 CS35L45_GLOBAL_ERROR_IRQ, 318 CS35L45_DSP_WDT_EXPIRE_IRQ, 319 CS35L45_PLL_UNLOCK_FLAG_RISE_IRQ, 320 CS35L45_PLL_LOCK_FLAG_IRQ, 321 CS35L45_NUM_IRQ 322 }; 323 324 struct cs35l45_private { 325 struct device *dev; 326 struct regmap *regmap; 327 struct gpio_desc *reset_gpio; 328 struct regulator *vdd_batt; 329 struct regulator *vdd_a; 330 bool initialized; 331 bool sysclk_set; 332 u8 slot_width; 333 u8 slot_count; 334 int irq_invert; 335 int irq; 336 struct regmap_irq_chip_data *irq_data; 337 }; 338 339 extern const struct dev_pm_ops cs35l45_pm_ops; 340 extern const struct regmap_config cs35l45_i2c_regmap; 341 extern const struct regmap_config cs35l45_spi_regmap; 342 int cs35l45_apply_patch(struct cs35l45_private *cs35l45); 343 unsigned int cs35l45_get_clk_freq_id(unsigned int freq); 344 int cs35l45_probe(struct cs35l45_private *cs35l45); 345 void cs35l45_remove(struct cs35l45_private *cs35l45); 346 347 #endif /* CS35L45_H */ 348