cs35l45-tables.c (fa8c052b4c614aa1d2d60e5c9f40e9d885bf9511) cs35l45-tables.c (6085f9e6dc1973cf98ee7f5dcf629939e50f1b84)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2//
3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8

--- 50 unchanged lines hidden (view full) ---

59 { CS35L45_ASP_DATA_CONTROL5, 0x00000018 },
60 { CS35L45_DACPCM1_INPUT, 0x00000008 },
61 { CS35L45_ASPTX1_INPUT, 0x00000018 },
62 { CS35L45_ASPTX2_INPUT, 0x00000019 },
63 { CS35L45_ASPTX3_INPUT, 0x00000020 },
64 { CS35L45_ASPTX4_INPUT, 0x00000028 },
65 { CS35L45_ASPTX5_INPUT, 0x00000048 },
66 { CS35L45_AMP_PCM_CONTROL, 0x00100000 },
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2//
3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8

--- 50 unchanged lines hidden (view full) ---

59 { CS35L45_ASP_DATA_CONTROL5, 0x00000018 },
60 { CS35L45_DACPCM1_INPUT, 0x00000008 },
61 { CS35L45_ASPTX1_INPUT, 0x00000018 },
62 { CS35L45_ASPTX2_INPUT, 0x00000019 },
63 { CS35L45_ASPTX3_INPUT, 0x00000020 },
64 { CS35L45_ASPTX4_INPUT, 0x00000028 },
65 { CS35L45_ASPTX5_INPUT, 0x00000048 },
66 { CS35L45_AMP_PCM_CONTROL, 0x00100000 },
67 { CS35L45_IRQ1_CFG, 0x00000000 },
68 { CS35L45_IRQ1_MASK_1, 0xBFEFFFBF },
69 { CS35L45_IRQ1_MASK_2, 0xFFFFFFFF },
70 { CS35L45_IRQ1_MASK_3, 0xFFFF87FF },
71 { CS35L45_IRQ1_MASK_4, 0xF8FFFFFF },
72 { CS35L45_IRQ1_MASK_5, 0x0EF80000 },
73 { CS35L45_IRQ1_MASK_6, 0x00000000 },
74 { CS35L45_IRQ1_MASK_7, 0xFFFFFF78 },
75 { CS35L45_IRQ1_MASK_8, 0x00003FFF },
76 { CS35L45_IRQ1_MASK_9, 0x00000000 },
77 { CS35L45_IRQ1_MASK_10, 0x00000000 },
78 { CS35L45_IRQ1_MASK_11, 0x00000000 },
79 { CS35L45_IRQ1_MASK_12, 0x00000000 },
80 { CS35L45_IRQ1_MASK_13, 0x00000000 },
81 { CS35L45_IRQ1_MASK_14, 0x00000001 },
82 { CS35L45_IRQ1_MASK_15, 0x00000000 },
83 { CS35L45_IRQ1_MASK_16, 0x00000000 },
84 { CS35L45_IRQ1_MASK_17, 0x00000000 },
85 { CS35L45_IRQ1_MASK_18, 0x3FE5D0FF },
67 { CS35L45_GPIO1_CTRL1, 0x81000001 },
68 { CS35L45_GPIO2_CTRL1, 0x81000001 },
69 { CS35L45_GPIO3_CTRL1, 0x81000001 },
70};
71
72static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
73{
74 switch (reg) {

--- 20 unchanged lines hidden (view full) ---

95 case CS35L45_DACPCM1_INPUT:
96 case CS35L45_ASPTX1_INPUT:
97 case CS35L45_ASPTX2_INPUT:
98 case CS35L45_ASPTX3_INPUT:
99 case CS35L45_ASPTX4_INPUT:
100 case CS35L45_ASPTX5_INPUT:
101 case CS35L45_AMP_PCM_CONTROL:
102 case CS35L45_AMP_PCM_HPF_TST:
86 { CS35L45_GPIO1_CTRL1, 0x81000001 },
87 { CS35L45_GPIO2_CTRL1, 0x81000001 },
88 { CS35L45_GPIO3_CTRL1, 0x81000001 },
89};
90
91static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
92{
93 switch (reg) {

--- 20 unchanged lines hidden (view full) ---

114 case CS35L45_DACPCM1_INPUT:
115 case CS35L45_ASPTX1_INPUT:
116 case CS35L45_ASPTX2_INPUT:
117 case CS35L45_ASPTX3_INPUT:
118 case CS35L45_ASPTX4_INPUT:
119 case CS35L45_ASPTX5_INPUT:
120 case CS35L45_AMP_PCM_CONTROL:
121 case CS35L45_AMP_PCM_HPF_TST:
103 case CS35L45_IRQ1_EINT_4:
122 case CS35L45_IRQ1_CFG:
123 case CS35L45_IRQ1_STATUS:
124 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
125 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
126 case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18:
104 case CS35L45_GPIO_STATUS1:
105 case CS35L45_GPIO1_CTRL1:
106 case CS35L45_GPIO2_CTRL1:
107 case CS35L45_GPIO3_CTRL1:
108 return true;
109 default:
110 return false;
111 }
112}
113
114static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
115{
116 switch (reg) {
117 case CS35L45_DEVID ... CS35L45_OTPID:
118 case CS35L45_SFT_RESET:
119 case CS35L45_GLOBAL_ENABLES:
120 case CS35L45_ERROR_RELEASE:
121 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */
127 case CS35L45_GPIO_STATUS1:
128 case CS35L45_GPIO1_CTRL1:
129 case CS35L45_GPIO2_CTRL1:
130 case CS35L45_GPIO3_CTRL1:
131 return true;
132 default:
133 return false;
134 }
135}
136
137static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
138{
139 switch (reg) {
140 case CS35L45_DEVID ... CS35L45_OTPID:
141 case CS35L45_SFT_RESET:
142 case CS35L45_GLOBAL_ENABLES:
143 case CS35L45_ERROR_RELEASE:
144 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */
122 case CS35L45_IRQ1_EINT_4:
145 case CS35L45_IRQ1_STATUS:
146 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
147 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
123 case CS35L45_GPIO_STATUS1:
124 return true;
125 default:
126 return false;
127 }
128}
129
130const struct regmap_config cs35l45_i2c_regmap = {

--- 82 unchanged lines hidden --- 		148 case CS35L45_GPIO_STATUS1:
149 return true;
150 default:
151 return false;
152 }
153}
154
155const struct regmap_config cs35l45_i2c_regmap = {

--- 82 unchanged lines hidden ---