cs35l45-tables.c (74b14e2850a34740c121cf2758d4181063d4c77c) cs35l45-tables.c (6c07be8fe92c6b0c24ee1c599601dce3506b83c7)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2//
3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8

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42
43static const struct reg_default cs35l45_defaults[] = {
44 { CS35L45_BLOCK_ENABLES, 0x00003323 },
45 { CS35L45_BLOCK_ENABLES2, 0x00000010 },
46 { CS35L45_SYNC_GPIO1, 0x00000007 },
47 { CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 },
48 { CS35L45_GPIO3, 0x00000005 },
49 { CS35L45_PWRMGT_CTL, 0x00000000 },
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2//
3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8

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42
43static const struct reg_default cs35l45_defaults[] = {
44 { CS35L45_BLOCK_ENABLES, 0x00003323 },
45 { CS35L45_BLOCK_ENABLES2, 0x00000010 },
46 { CS35L45_SYNC_GPIO1, 0x00000007 },
47 { CS35L45_INTB_GPIO2_MCLK_REF, 0x00000005 },
48 { CS35L45_GPIO3, 0x00000005 },
49 { CS35L45_PWRMGT_CTL, 0x00000000 },
50 { CS35L45_WAKESRC_CTL, 0x00000008 },
51 { CS35L45_WKI2C_CTL, 0x00000030 },
50 { CS35L45_REFCLK_INPUT, 0x00000510 },
51 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 },
52 { CS35L45_ASP_ENABLES1, 0x00000000 },
53 { CS35L45_ASP_CONTROL1, 0x00000028 },
54 { CS35L45_ASP_CONTROL2, 0x18180200 },
55 { CS35L45_ASP_CONTROL3, 0x00000002 },
56 { CS35L45_ASP_FRAME_CONTROL1, 0x03020100 },
57 { CS35L45_ASP_FRAME_CONTROL2, 0x00000004 },

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121 case CS35L45_GLOBAL_ENABLES:
122 case CS35L45_BLOCK_ENABLES:
123 case CS35L45_BLOCK_ENABLES2:
124 case CS35L45_ERROR_RELEASE:
125 case CS35L45_SYNC_GPIO1:
126 case CS35L45_INTB_GPIO2_MCLK_REF:
127 case CS35L45_GPIO3:
128 case CS35L45_PWRMGT_CTL:
52 { CS35L45_REFCLK_INPUT, 0x00000510 },
53 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 },
54 { CS35L45_ASP_ENABLES1, 0x00000000 },
55 { CS35L45_ASP_CONTROL1, 0x00000028 },
56 { CS35L45_ASP_CONTROL2, 0x18180200 },
57 { CS35L45_ASP_CONTROL3, 0x00000002 },
58 { CS35L45_ASP_FRAME_CONTROL1, 0x03020100 },
59 { CS35L45_ASP_FRAME_CONTROL2, 0x00000004 },

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123 case CS35L45_GLOBAL_ENABLES:
124 case CS35L45_BLOCK_ENABLES:
125 case CS35L45_BLOCK_ENABLES2:
126 case CS35L45_ERROR_RELEASE:
127 case CS35L45_SYNC_GPIO1:
128 case CS35L45_INTB_GPIO2_MCLK_REF:
129 case CS35L45_GPIO3:
130 case CS35L45_PWRMGT_CTL:
131 case CS35L45_WAKESRC_CTL:
132 case CS35L45_WKI2C_CTL:
133 case CS35L45_PWRMGT_STS:
129 case CS35L45_REFCLK_INPUT:
130 case CS35L45_GLOBAL_SAMPLE_RATE:
131 case CS35L45_ASP_ENABLES1:
132 case CS35L45_ASP_CONTROL1:
133 case CS35L45_ASP_CONTROL2:
134 case CS35L45_ASP_CONTROL3:
135 case CS35L45_ASP_FRAME_CONTROL1:
136 case CS35L45_ASP_FRAME_CONTROL2:

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205static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
206{
207 switch (reg) {
208 case CS35L45_DEVID ... CS35L45_OTPID:
209 case CS35L45_SFT_RESET:
210 case CS35L45_GLOBAL_ENABLES:
211 case CS35L45_ERROR_RELEASE:
212 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */
134 case CS35L45_REFCLK_INPUT:
135 case CS35L45_GLOBAL_SAMPLE_RATE:
136 case CS35L45_ASP_ENABLES1:
137 case CS35L45_ASP_CONTROL1:
138 case CS35L45_ASP_CONTROL2:
139 case CS35L45_ASP_CONTROL3:
140 case CS35L45_ASP_FRAME_CONTROL1:
141 case CS35L45_ASP_FRAME_CONTROL2:

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210static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
211{
212 switch (reg) {
213 case CS35L45_DEVID ... CS35L45_OTPID:
214 case CS35L45_SFT_RESET:
215 case CS35L45_GLOBAL_ENABLES:
216 case CS35L45_ERROR_RELEASE:
217 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */
218 case CS35L45_PWRMGT_STS:
213 case CS35L45_IRQ1_STATUS:
214 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
215 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
216 case CS35L45_GPIO_STATUS1:
217 case CS35L45_DSP_MBOX_1:
218 case CS35L45_DSP_MBOX_2:
219 case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
220 case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:

--- 103 unchanged lines hidden --- 		219 case CS35L45_IRQ1_STATUS:
220 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
221 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
222 case CS35L45_GPIO_STATUS1:
223 case CS35L45_DSP_MBOX_1:
224 case CS35L45_DSP_MBOX_2:
225 case CS35L45_DSP_VIRT1_MBOX_1 ... CS35L45_DSP_VIRT1_MBOX_4:
226 case CS35L45_DSP_VIRT2_MBOX_1 ... CS35L45_DSP_VIRT2_MBOX_4:

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