amd.h (c32bd332ce5c9eda087dedae2cf5f98bb008e841) amd.h (5a9f07a41522e1d16f2a43b1843e266434df0866)
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11#ifndef __AMD_ACP_H
12#define __AMD_ACP_H
13
14#include <sound/pcm.h>
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11#ifndef __AMD_ACP_H
12#define __AMD_ACP_H
13
14#include <sound/pcm.h>
15#include <sound/soc.h>
15#include <sound/soc-acpi.h>
16#include <sound/soc-acpi.h>
17#include <sound/soc-dai.h>
18
16#include "chip_offset_byte.h"
17
19#include "chip_offset_byte.h"
20
21#define ACP3X_DEV 3
22
18#define I2S_SP_INSTANCE 0x00
19#define I2S_BT_INSTANCE 0x01
20#define DMIC_INSTANCE 0x02
21
22#define MEM_WINDOW_START 0x4080000
23
24#define ACP_I2S_REG_START 0x1242400
25#define ACP_I2S_REG_END 0x1242810

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65#define FIFO_SIZE 0x100
66#define DMA_SIZE 0x40
67#define FRM_LEN 0x100
68
69#define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
70
71#define ACP_MAX_STREAM 6
72
23#define I2S_SP_INSTANCE 0x00
24#define I2S_BT_INSTANCE 0x01
25#define DMIC_INSTANCE 0x02
26
27#define MEM_WINDOW_START 0x4080000
28
29#define ACP_I2S_REG_START 0x1242400
30#define ACP_I2S_REG_END 0x1242810

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70#define FIFO_SIZE 0x100
71#define DMA_SIZE 0x40
72#define FRM_LEN 0x100
73
74#define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
75
76#define ACP_MAX_STREAM 6
77
78struct acp_chip_info {
79 char *name; /* Platform name */
80 unsigned int acp_rev; /* ACP Revision id */
81 void __iomem *base; /* ACP memory PCI base */
82};
83
73struct acp_stream {
74 struct snd_pcm_substream *substream;
75 int irq_bit;
76 int dai_id;
77 int id;
78 u64 bytescount;
79 u32 reg_offset;
80 u32 pte_offset;

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101extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
102
103int asoc_acp_i2s_probe(struct snd_soc_dai *dai);
104int acp_platform_register(struct device *dev);
105int acp_platform_unregister(struct device *dev);
106
107int acp_machine_select(struct acp_dev_data *adata);
108
84struct acp_stream {
85 struct snd_pcm_substream *substream;
86 int irq_bit;
87 int dai_id;
88 int id;
89 u64 bytescount;
90 u32 reg_offset;
91 u32 pte_offset;

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112extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
113
114int asoc_acp_i2s_probe(struct snd_soc_dai *dai);
115int acp_platform_register(struct device *dev);
116int acp_platform_unregister(struct device *dev);
117
118int acp_machine_select(struct acp_dev_data *adata);
119
120/* Machine configuration */
121int snd_amd_acp_find_config(struct pci_dev *pci);
122
109static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)
110{
111 u64 byte_count, low = 0, high = 0;
112
113 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
114 switch (dai_id) {
115 case I2S_BT_INSTANCE:
116 high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);

--- 36 unchanged lines hidden --- 		123static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)
124{
125 u64 byte_count, low = 0, high = 0;
126
127 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
128 switch (dai_id) {
129 case I2S_BT_INSTANCE:
130 high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);

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