amd.h (87a0b2fafc09766d8c55461a18345a1cfb10a7fe) amd.h (c32bd332ce5c9eda087dedae2cf5f98bb008e841)
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11#ifndef __AMD_ACP_H
12#define __AMD_ACP_H
13
14#include <sound/pcm.h>
15#include <sound/soc-acpi.h>
16#include "chip_offset_byte.h"
17
18#define I2S_SP_INSTANCE 0x00
19#define I2S_BT_INSTANCE 0x01
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11#ifndef __AMD_ACP_H
12#define __AMD_ACP_H
13
14#include <sound/pcm.h>
15#include <sound/soc-acpi.h>
16#include "chip_offset_byte.h"
17
18#define I2S_SP_INSTANCE 0x00
19#define I2S_BT_INSTANCE 0x01
20#define DMIC_INSTANCE 0x02
20
21
21#define MEM_WINDOW_START 0x4000000
22#define MEM_WINDOW_START 0x4080000
22
23#define ACP_I2S_REG_START 0x1242400
24#define ACP_I2S_REG_END 0x1242810
25#define ACP3x_I2STDM_REG_START 0x1242400
26#define ACP3x_I2STDM_REG_END 0x1242410
27#define ACP3x_BT_TDM_REG_START 0x1242800
28#define ACP3x_BT_TDM_REG_END 0x1242810
29#define I2S_MODE 0x04
30#define I2S_RX_THRESHOLD 27
31#define I2S_TX_THRESHOLD 28
32#define BT_TX_THRESHOLD 26
33#define BT_RX_THRESHOLD 25
34
35#define ACP_SRAM_PTE_OFFSET 0x02052800
36
37#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
38#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
39#define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
40#define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
23
24#define ACP_I2S_REG_START 0x1242400
25#define ACP_I2S_REG_END 0x1242810
26#define ACP3x_I2STDM_REG_START 0x1242400
27#define ACP3x_I2STDM_REG_END 0x1242410
28#define ACP3x_BT_TDM_REG_START 0x1242800
29#define ACP3x_BT_TDM_REG_END 0x1242810
30#define I2S_MODE 0x04
31#define I2S_RX_THRESHOLD 27
32#define I2S_TX_THRESHOLD 28
33#define BT_TX_THRESHOLD 26
34#define BT_RX_THRESHOLD 25
35
36#define ACP_SRAM_PTE_OFFSET 0x02052800
37
38#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
39#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
40#define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
41#define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
42#define ACP_SRAM_PDM_PTE_OFFSET 0x400
41#define PAGE_SIZE_4K_ENABLE 0x2
42
43#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
44#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
45#define I2S_BT_TX_MEM_WINDOW_START 0x4040000
46#define I2S_BT_RX_MEM_WINDOW_START 0x4060000
47
48#define SP_PB_FIFO_ADDR_OFFSET 0x500

--- 42 unchanged lines hidden (view full) ---

91
92 struct acp_stream *stream[ACP_MAX_STREAM];
93
94 struct snd_soc_acpi_mach *machines;
95 struct platform_device *mach_dev;
96};
97
98extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
43#define PAGE_SIZE_4K_ENABLE 0x2
44
45#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
46#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
47#define I2S_BT_TX_MEM_WINDOW_START 0x4040000
48#define I2S_BT_RX_MEM_WINDOW_START 0x4060000
49
50#define SP_PB_FIFO_ADDR_OFFSET 0x500

--- 42 unchanged lines hidden (view full) ---

93
94 struct acp_stream *stream[ACP_MAX_STREAM];
95
96 struct snd_soc_acpi_mach *machines;
97 struct platform_device *mach_dev;
98};
99
100extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
101extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
99
100int asoc_acp_i2s_probe(struct snd_soc_dai *dai);
101int acp_platform_register(struct device *dev);
102int acp_platform_unregister(struct device *dev);
103
104int acp_machine_select(struct acp_dev_data *adata);
105
106static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)

--- 19 unchanged lines hidden (view full) ---

126 case I2S_BT_INSTANCE:
127 high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
128 low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
129 break;
130 case I2S_SP_INSTANCE:
131 high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
132 low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
133 break;
102
103int asoc_acp_i2s_probe(struct snd_soc_dai *dai);
104int acp_platform_register(struct device *dev);
105int acp_platform_unregister(struct device *dev);
106
107int acp_machine_select(struct acp_dev_data *adata);
108
109static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)

--- 19 unchanged lines hidden (view full) ---

129 case I2S_BT_INSTANCE:
130 high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
131 low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
132 break;
133 case I2S_SP_INSTANCE:
134 high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
135 low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
136 break;
137 case DMIC_INSTANCE:
138 high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
139 low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
140 break;
134 default:
135 dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
136 return -EINVAL;
137 }
138 }
139 /* Get 64 bit value from two 32 bit registers */
140 byte_count = (high << 32) | low;
141
142 return byte_count;
143}
144
145#endif
141 default:
142 dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
143 return -EINVAL;
144 }
145 }
146 /* Get 64 bit value from two 32 bit registers */
147 byte_count = (high << 32) | low;
148
149 return byte_count;
150}
151
152#endif