core.h (1e6b98ebd458e63b9effda2feb696e36644d4eed) core.h (38e9002b85672352f8693c82192c8029586dd86d)
1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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462#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
463
464 int otg_ver;
465 int dma_desc_enable;
466 int dma_desc_fs_enable;
467 int speed;
468#define DWC2_SPEED_PARAM_HIGH 0
469#define DWC2_SPEED_PARAM_FULL 1
1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 453 unchanged lines hidden (view full) ---

462#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
463
464 int otg_ver;
465 int dma_desc_enable;
466 int dma_desc_fs_enable;
467 int speed;
468#define DWC2_SPEED_PARAM_HIGH 0
469#define DWC2_SPEED_PARAM_FULL 1
470#define DWC2_SPEED_PARAM_LOW 2
470
471 int enable_dynamic_fifo;
472 int en_multiple_tx_fifo;
473 int host_rx_fifo_size;
474 int host_nperio_tx_fifo_size;
475 int host_perio_tx_fifo_size;
476 int max_transfer_size;
477 int max_packet_count;

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472 int enable_dynamic_fifo;
473 int en_multiple_tx_fifo;
474 int host_rx_fifo_size;
475 int host_nperio_tx_fifo_size;
476 int host_perio_tx_fifo_size;
477 int max_transfer_size;
478 int max_packet_count;

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