amba-pl011.c (1f2d9c9dd8276b1c19ef80e6d8059fe47506d4c3) amba-pl011.c (c16d51a32bbb61ac8fd96f78b5ce2fccfe0fb4c3)
1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA

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45#include <linux/serial.h>
46#include <linux/amba/bus.h>
47#include <linux/amba/serial.h>
48#include <linux/clk.h>
49#include <linux/slab.h>
50#include <linux/dmaengine.h>
51#include <linux/dma-mapping.h>
52#include <linux/scatterlist.h>
1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA

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45#include <linux/serial.h>
46#include <linux/amba/bus.h>
47#include <linux/amba/serial.h>
48#include <linux/clk.h>
49#include <linux/slab.h>
50#include <linux/dmaengine.h>
51#include <linux/dma-mapping.h>
52#include <linux/scatterlist.h>
53#include <linux/delay.h>
53
54#include <asm/io.h>
55#include <asm/sizes.h>
56
57#define UART_NR 14
58
59#define SERIAL_AMBA_MAJOR 204
60#define SERIAL_AMBA_MINOR 64
61#define SERIAL_AMBA_NR UART_NR
62
63#define AMBA_ISR_PASS_LIMIT 256
64
65#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
66#define UART_DUMMY_DR_RX (1 << 16)
67
54
55#include <asm/io.h>
56#include <asm/sizes.h>
57
58#define UART_NR 14
59
60#define SERIAL_AMBA_MAJOR 204
61#define SERIAL_AMBA_MINOR 64
62#define SERIAL_AMBA_NR UART_NR
63
64#define AMBA_ISR_PASS_LIMIT 256
65
66#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
67#define UART_DUMMY_DR_RX (1 << 16)
68
69
70#define UART_WA_SAVE_NR 14
71
72static void pl011_lockup_wa(unsigned long data);
73static const u32 uart_wa_reg[UART_WA_SAVE_NR] = {
74 ST_UART011_DMAWM,
75 ST_UART011_TIMEOUT,
76 ST_UART011_LCRH_RX,
77 UART011_IBRD,
78 UART011_FBRD,
79 ST_UART011_LCRH_TX,
80 UART011_IFLS,
81 ST_UART011_XFCR,
82 ST_UART011_XON1,
83 ST_UART011_XON2,
84 ST_UART011_XOFF1,
85 ST_UART011_XOFF2,
86 UART011_CR,
87 UART011_IMSC
88};
89
90static u32 uart_wa_regdata[UART_WA_SAVE_NR];
91static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0);
92
68/* There is by now at least one vendor with differing details, so handle it */
69struct vendor_data {
70 unsigned int ifls;
71 unsigned int fifosize;
72 unsigned int lcrh_tx;
73 unsigned int lcrh_rx;
74 bool oversampling;
93/* There is by now at least one vendor with differing details, so handle it */
94struct vendor_data {
95 unsigned int ifls;
96 unsigned int fifosize;
97 unsigned int lcrh_tx;
98 unsigned int lcrh_rx;
99 bool oversampling;
100 bool interrupt_may_hang; /* vendor-specific */
75 bool dma_threshold;
76};
77
78static struct vendor_data vendor_arm = {
79 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
80 .fifosize = 16,
81 .lcrh_tx = UART011_LCRH,
82 .lcrh_rx = UART011_LCRH,
83 .oversampling = false,
84 .dma_threshold = false,
85};
86
87static struct vendor_data vendor_st = {
88 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
89 .fifosize = 64,
90 .lcrh_tx = ST_UART011_LCRH_TX,
91 .lcrh_rx = ST_UART011_LCRH_RX,
92 .oversampling = true,
101 bool dma_threshold;
102};
103
104static struct vendor_data vendor_arm = {
105 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
106 .fifosize = 16,
107 .lcrh_tx = UART011_LCRH,
108 .lcrh_rx = UART011_LCRH,
109 .oversampling = false,
110 .dma_threshold = false,
111};
112
113static struct vendor_data vendor_st = {
114 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
115 .fifosize = 64,
116 .lcrh_tx = ST_UART011_LCRH_TX,
117 .lcrh_rx = ST_UART011_LCRH_RX,
118 .oversampling = true,
119 .interrupt_may_hang = true,
93 .dma_threshold = true,
94};
95
120 .dma_threshold = true,
121};
122
123static struct uart_amba_port *amba_ports[UART_NR];
124
96/* Deals with DMA transactions */
97
98struct pl011_sgbuf {
99 struct scatterlist sg;
100 char *buf;
101};
102
103struct pl011_dmarx_data {

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127 unsigned int dmacr; /* dma control reg */
128 unsigned int im; /* interrupt mask */
129 unsigned int old_status;
130 unsigned int fifosize; /* vendor-specific */
131 unsigned int lcrh_tx; /* vendor-specific */
132 unsigned int lcrh_rx; /* vendor-specific */
133 bool autorts;
134 char type[12];
125/* Deals with DMA transactions */
126
127struct pl011_sgbuf {
128 struct scatterlist sg;
129 char *buf;
130};
131
132struct pl011_dmarx_data {

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156 unsigned int dmacr; /* dma control reg */
157 unsigned int im; /* interrupt mask */
158 unsigned int old_status;
159 unsigned int fifosize; /* vendor-specific */
160 unsigned int lcrh_tx; /* vendor-specific */
161 unsigned int lcrh_rx; /* vendor-specific */
162 bool autorts;
163 char type[12];
164 bool interrupt_may_hang; /* vendor-specific */
135#ifdef CONFIG_DMA_ENGINE
136 /* DMA stuff */
137 bool using_tx_dma;
138 bool using_rx_dma;
139 struct pl011_dmarx_data dmarx;
140 struct pl011_dmatx_data dmatx;
141#endif
142};

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1003{
1004 return false;
1005}
1006
1007#define pl011_dma_flush_buffer NULL
1008#endif
1009
1010
165#ifdef CONFIG_DMA_ENGINE
166 /* DMA stuff */
167 bool using_tx_dma;
168 bool using_rx_dma;
169 struct pl011_dmarx_data dmarx;
170 struct pl011_dmatx_data dmatx;
171#endif
172};

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1033{
1034 return false;
1035}
1036
1037#define pl011_dma_flush_buffer NULL
1038#endif
1039
1040
1041/*
1042 * pl011_lockup_wa
1043 * This workaround aims to break the deadlock situation
1044 * when after long transfer over uart in hardware flow
1045 * control, uart interrupt registers cannot be cleared.
1046 * Hence uart transfer gets blocked.
1047 *
1048 * It is seen that during such deadlock condition ICR
1049 * don't get cleared even on multiple write. This leads
1050 * pass_counter to decrease and finally reach zero. This
1051 * can be taken as trigger point to run this UART_BT_WA.
1052 *
1053 */
1054static void pl011_lockup_wa(unsigned long data)
1055{
1056 struct uart_amba_port *uap = amba_ports[0];
1057 void __iomem *base = uap->port.membase;
1058 struct circ_buf *xmit = &uap->port.state->xmit;
1059 struct tty_struct *tty = uap->port.state->port.tty;
1060 int buf_empty_retries = 200;
1061 int loop;
1062
1063 /* Stop HCI layer from submitting data for tx */
1064 tty->hw_stopped = 1;
1065 while (!uart_circ_empty(xmit)) {
1066 if (buf_empty_retries-- == 0)
1067 break;
1068 udelay(100);
1069 }
1070
1071 /* Backup registers */
1072 for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
1073 uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]);
1074
1075 /* Disable UART so that FIFO data is flushed out */
1076 writew(0x00, uap->port.membase + UART011_CR);
1077
1078 /* Soft reset UART module */
1079 if (uap->port.dev->platform_data) {
1080 struct amba_pl011_data *plat;
1081
1082 plat = uap->port.dev->platform_data;
1083 if (plat->reset)
1084 plat->reset();
1085 }
1086
1087 /* Restore registers */
1088 for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
1089 writew(uart_wa_regdata[loop] ,
1090 uap->port.membase + uart_wa_reg[loop]);
1091
1092 /* Initialise the old status of the modem signals */
1093 uap->old_status = readw(uap->port.membase + UART01x_FR) &
1094 UART01x_FR_MODEM_ANY;
1095
1096 if (readl(base + UART011_MIS) & 0x2)
1097 printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n");
1098
1099 /* Start Tx/Rx */
1100 tty->hw_stopped = 0;
1101}
1102
1011static void pl011_stop_tx(struct uart_port *port)
1012{
1013 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1014
1015 uap->im &= ~UART011_TXIM;
1016 writew(uap->im, uap->port.membase + UART011_IMSC);
1017 pl011_dma_tx_stop(uap);
1018}

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1153 pl011_rx_chars(uap);
1154 }
1155 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1156 UART011_CTSMIS|UART011_RIMIS))
1157 pl011_modem_status(uap);
1158 if (status & UART011_TXIS)
1159 pl011_tx_chars(uap);
1160
1103static void pl011_stop_tx(struct uart_port *port)
1104{
1105 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1106
1107 uap->im &= ~UART011_TXIM;
1108 writew(uap->im, uap->port.membase + UART011_IMSC);
1109 pl011_dma_tx_stop(uap);
1110}

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1245 pl011_rx_chars(uap);
1246 }
1247 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1248 UART011_CTSMIS|UART011_RIMIS))
1249 pl011_modem_status(uap);
1250 if (status & UART011_TXIS)
1251 pl011_tx_chars(uap);
1252
1161 if (pass_counter-- == 0)
1253 if (pass_counter-- == 0) {
1254 if (uap->interrupt_may_hang)
1255 tasklet_schedule(&pl011_lockup_tlet);
1162 break;
1256 break;
1257 }
1163
1164 status = readw(uap->port.membase + UART011_MIS);
1165 } while (status != 0);
1166 handled = 1;
1167 }
1168
1169 spin_unlock_irqrestore(&uap->port.lock, flags);
1170

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1334 */
1335 spin_lock_irq(&uap->port.lock);
1336 uap->im = UART011_RTIM;
1337 if (!pl011_dma_rx_running(uap))
1338 uap->im |= UART011_RXIM;
1339 writew(uap->im, uap->port.membase + UART011_IMSC);
1340 spin_unlock_irq(&uap->port.lock);
1341
1258
1259 status = readw(uap->port.membase + UART011_MIS);
1260 } while (status != 0);
1261 handled = 1;
1262 }
1263
1264 spin_unlock_irqrestore(&uap->port.lock, flags);
1265

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1429 */
1430 spin_lock_irq(&uap->port.lock);
1431 uap->im = UART011_RTIM;
1432 if (!pl011_dma_rx_running(uap))
1433 uap->im |= UART011_RXIM;
1434 writew(uap->im, uap->port.membase + UART011_IMSC);
1435 spin_unlock_irq(&uap->port.lock);
1436
1437 if (uap->port.dev->platform_data) {
1438 struct amba_pl011_data *plat;
1439
1440 plat = uap->port.dev->platform_data;
1441 if (plat->init)
1442 plat->init();
1443 }
1444
1342 return 0;
1343
1344 clk_dis:
1345 clk_disable(uap->clk);
1346 out:
1347 return retval;
1348}
1349

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1389 pl011_shutdown_channel(uap, uap->lcrh_rx);
1390 if (uap->lcrh_rx != uap->lcrh_tx)
1391 pl011_shutdown_channel(uap, uap->lcrh_tx);
1392
1393 /*
1394 * Shut down the clock producer
1395 */
1396 clk_disable(uap->clk);
1445 return 0;
1446
1447 clk_dis:
1448 clk_disable(uap->clk);
1449 out:
1450 return retval;
1451}
1452

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1492 pl011_shutdown_channel(uap, uap->lcrh_rx);
1493 if (uap->lcrh_rx != uap->lcrh_tx)
1494 pl011_shutdown_channel(uap, uap->lcrh_tx);
1495
1496 /*
1497 * Shut down the clock producer
1498 */
1499 clk_disable(uap->clk);
1500
1501 if (uap->port.dev->platform_data) {
1502 struct amba_pl011_data *plat;
1503
1504 plat = uap->port.dev->platform_data;
1505 if (plat->exit)
1506 plat->exit();
1507 }
1508
1397}
1398
1399static void
1400pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1401 struct ktermios *old)
1402{
1403 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1404 unsigned int lcr_h, old_cr;

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1695 * console support.
1696 */
1697 if (co->index >= UART_NR)
1698 co->index = 0;
1699 uap = amba_ports[co->index];
1700 if (!uap)
1701 return -ENODEV;
1702
1509}
1510
1511static void
1512pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1513 struct ktermios *old)
1514{
1515 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1516 unsigned int lcr_h, old_cr;

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1807 * console support.
1808 */
1809 if (co->index >= UART_NR)
1810 co->index = 0;
1811 uap = amba_ports[co->index];
1812 if (!uap)
1813 return -ENODEV;
1814
1815 if (uap->port.dev->platform_data) {
1816 struct amba_pl011_data *plat;
1817
1818 plat = uap->port.dev->platform_data;
1819 if (plat->init)
1820 plat->init();
1821 }
1822
1703 uap->port.uartclk = clk_get_rate(uap->clk);
1704
1705 if (options)
1706 uart_parse_options(options, &baud, &parity, &bits, &flow);
1707 else
1708 pl011_console_get_options(uap, &baud, &parity, &bits);
1709
1710 return uart_set_options(&uap->port, co, baud, parity, bits, flow);

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1769 ret = PTR_ERR(uap->clk);
1770 goto unmap;
1771 }
1772
1773 uap->vendor = vendor;
1774 uap->lcrh_rx = vendor->lcrh_rx;
1775 uap->lcrh_tx = vendor->lcrh_tx;
1776 uap->fifosize = vendor->fifosize;
1823 uap->port.uartclk = clk_get_rate(uap->clk);
1824
1825 if (options)
1826 uart_parse_options(options, &baud, &parity, &bits, &flow);
1827 else
1828 pl011_console_get_options(uap, &baud, &parity, &bits);
1829
1830 return uart_set_options(&uap->port, co, baud, parity, bits, flow);

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1889 ret = PTR_ERR(uap->clk);
1890 goto unmap;
1891 }
1892
1893 uap->vendor = vendor;
1894 uap->lcrh_rx = vendor->lcrh_rx;
1895 uap->lcrh_tx = vendor->lcrh_tx;
1896 uap->fifosize = vendor->fifosize;
1897 uap->interrupt_may_hang = vendor->interrupt_may_hang;
1777 uap->port.dev = &dev->dev;
1778 uap->port.mapbase = dev->res.start;
1779 uap->port.membase = base;
1780 uap->port.iotype = UPIO_MEM;
1781 uap->port.irq = dev->irq[0];
1782 uap->port.fifosize = uap->fifosize;
1783 uap->port.ops = &amba_pl011_pops;
1784 uap->port.flags = UPF_BOOT_AUTOCONF;

--- 122 unchanged lines hidden --- 		1898 uap->port.dev = &dev->dev;
1899 uap->port.mapbase = dev->res.start;
1900 uap->port.membase = base;
1901 uap->port.iotype = UPIO_MEM;
1902 uap->port.irq = dev->irq[0];
1903 uap->port.fifosize = uap->fifosize;
1904 uap->port.ops = &amba_pl011_pops;
1905 uap->port.flags = UPF_BOOT_AUTOCONF;

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