exynos_tmu.c (e6b7991ed50fea9bf8b36e8a4794ee36d35e1651) exynos_tmu.c (d0a0ce3e77c795258d47f9163e92d5031d0c5221)
1/*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
7 *
8 * This program is free software; you can redistribute it and/or modify

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38#define EXYNOS_TMU_REG_STATUS 0x28
39#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
40#define EXYNOS_TMU_REG_INTEN 0x70
41#define EXYNOS_TMU_REG_INTSTAT 0x74
42#define EXYNOS_TMU_REG_INTCLEAR 0x78
43
44#define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
45#define EXYNOS_TMU_GAIN_SHIFT 8
1/*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
7 *
8 * This program is free software; you can redistribute it and/or modify

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38#define EXYNOS_TMU_REG_STATUS 0x28
39#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
40#define EXYNOS_TMU_REG_INTEN 0x70
41#define EXYNOS_TMU_REG_INTSTAT 0x74
42#define EXYNOS_TMU_REG_INTCLEAR 0x78
43
44#define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
45#define EXYNOS_TMU_GAIN_SHIFT 8
46#define EXYNOS_TMU_GAIN_MASK 0xf
46#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
47#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
47#define EXYNOS_TMU_CORE_ON 3
48#define EXYNOS_TMU_CORE_OFF 2
48#define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
49#define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
50#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
51#define EXYNOS_TMU_CORE_EN_SHIFT 0
49#define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
50
51/* Exynos4210 specific registers */
52#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
53#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
54#define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
55#define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
56#define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
57#define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
58#define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
59#define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
60#define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
61
62#define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
63#define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
64#define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
65#define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
52#define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
53
54/* Exynos4210 specific registers */
55#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
56#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
57#define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
58#define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
59#define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
60#define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
61#define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
62#define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
63#define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
64
65#define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
66#define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
67#define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
68#define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
69#define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111
66#define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
67
68/* Exynos5250 and Exynos4412 specific registers */
69#define EXYNOS_TMU_TRIMINFO_CON 0x14
70#define EXYNOS_THD_TEMP_RISE 0x50
71#define EXYNOS_THD_TEMP_FALL 0x54
72#define EXYNOS_EMUL_CON 0x80
73
74#define EXYNOS_TRIMINFO_RELOAD 0x1
70#define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
71
72/* Exynos5250 and Exynos4412 specific registers */
73#define EXYNOS_TMU_TRIMINFO_CON 0x14
74#define EXYNOS_THD_TEMP_RISE 0x50
75#define EXYNOS_THD_TEMP_FALL 0x54
76#define EXYNOS_EMUL_CON 0x80
77
78#define EXYNOS_TRIMINFO_RELOAD 0x1
79#define EXYNOS_TRIMINFO_SHIFT 0x0
80#define EXYNOS_TMU_RISE_INT_MASK 0x111
81#define EXYNOS_TMU_RISE_INT_SHIFT 0
82#define EXYNOS_TMU_FALL_INT_MASK 0x111
83#define EXYNOS_TMU_FALL_INT_SHIFT 12
75#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
76#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
84#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
85#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
77#define EXYNOS_MUX_ADDR_VALUE 6
78#define EXYNOS_MUX_ADDR_SHIFT 20
79#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
86#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
87#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
80
88
89#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
90#define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
91#define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
92#define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
93#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
94#define EXYNOS_TMU_INTEN_FALL1_SHIFT 20
95#define EXYNOS_TMU_INTEN_FALL2_SHIFT 24
96
81#define EFUSE_MIN_VALUE 40
82#define EFUSE_MAX_VALUE 100
83
84#ifdef CONFIG_THERMAL_EMULATION
85#define EXYNOS_EMUL_TIME 0x57F0
97#define EFUSE_MIN_VALUE 40
98#define EFUSE_MAX_VALUE 100
99
100#ifdef CONFIG_THERMAL_EMULATION
101#define EXYNOS_EMUL_TIME 0x57F0
102#define EXYNOS_EMUL_TIME_MASK 0xffff
86#define EXYNOS_EMUL_TIME_SHIFT 16
87#define EXYNOS_EMUL_DATA_SHIFT 8
88#define EXYNOS_EMUL_DATA_MASK 0xFF
89#define EXYNOS_EMUL_ENABLE 0x1
90#endif /* CONFIG_THERMAL_EMULATION */
91
92struct exynos_tmu_data {
93 struct exynos_tmu_platform_data *pdata;

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256{
257 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
258 struct exynos_tmu_platform_data *pdata = data->pdata;
259 unsigned int con, interrupt_en;
260
261 mutex_lock(&data->lock);
262 clk_enable(data->clk);
263
103#define EXYNOS_EMUL_TIME_SHIFT 16
104#define EXYNOS_EMUL_DATA_SHIFT 8
105#define EXYNOS_EMUL_DATA_MASK 0xFF
106#define EXYNOS_EMUL_ENABLE 0x1
107#endif /* CONFIG_THERMAL_EMULATION */
108
109struct exynos_tmu_data {
110 struct exynos_tmu_platform_data *pdata;

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273{
274 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
275 struct exynos_tmu_platform_data *pdata = data->pdata;
276 unsigned int con, interrupt_en;
277
278 mutex_lock(&data->lock);
279 clk_enable(data->clk);
280
264 con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
265 pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
281 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
266
282
267 if (data->soc == SOC_ARCH_EXYNOS) {
268 con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT;
269 con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
283 if (pdata->reference_voltage) {
284 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK <<
285 EXYNOS_TMU_REF_VOLTAGE_SHIFT);
286 con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
270 }
271
287 }
288
289 if (pdata->gain) {
290 con &= ~(EXYNOS_TMU_GAIN_MASK << EXYNOS_TMU_GAIN_SHIFT);
291 con |= (pdata->gain << EXYNOS_TMU_GAIN_SHIFT);
292 }
293
294 if (pdata->noise_cancel_mode) {
295 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK <<
296 EXYNOS_TMU_TRIP_MODE_SHIFT);
297 con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
298 }
299
272 if (on) {
300 if (on) {
273 con |= EXYNOS_TMU_CORE_ON;
274 interrupt_en = pdata->trigger_level3_en << 12 |
275 pdata->trigger_level2_en << 8 |
276 pdata->trigger_level1_en << 4 |
277 pdata->trigger_level0_en;
301 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
302 interrupt_en =
303 pdata->trigger_level3_en << EXYNOS_TMU_INTEN_RISE3_SHIFT |
304 pdata->trigger_level2_en << EXYNOS_TMU_INTEN_RISE2_SHIFT |
305 pdata->trigger_level1_en << EXYNOS_TMU_INTEN_RISE1_SHIFT |
306 pdata->trigger_level0_en << EXYNOS_TMU_INTEN_RISE0_SHIFT;
278 if (pdata->threshold_falling)
307 if (pdata->threshold_falling)
279 interrupt_en |= interrupt_en << 16;
308 interrupt_en |=
309 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
280 } else {
310 } else {
281 con |= EXYNOS_TMU_CORE_OFF;
311 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
282 interrupt_en = 0; /* Disable all interrupts */
283 }
284 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
285 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
286
287 clk_disable(data->clk);
288 mutex_unlock(&data->lock);
289}

--- 303 unchanged lines hidden --- 		312 interrupt_en = 0; /* Disable all interrupts */
313 }
314 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
315 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
316
317 clk_disable(data->clk);
318 mutex_unlock(&data->lock);
319}

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