1 /* 2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) 3 * 4 * Copyright (C) 2011 Samsung Electronics 5 * Donggeun Kim <dg77.kim@samsung.com> 6 * Amit Daniel Kachhap <amit.kachhap@linaro.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23 24 #include <linux/clk.h> 25 #include <linux/io.h> 26 #include <linux/interrupt.h> 27 #include <linux/module.h> 28 #include <linux/of.h> 29 #include <linux/platform_device.h> 30 31 #include "exynos_thermal_common.h" 32 #include "exynos_tmu.h" 33 #include "exynos_tmu_data.h" 34 35 /* Exynos generic registers */ 36 #define EXYNOS_TMU_REG_TRIMINFO 0x0 37 #define EXYNOS_TMU_REG_CONTROL 0x20 38 #define EXYNOS_TMU_REG_STATUS 0x28 39 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 40 #define EXYNOS_TMU_REG_INTEN 0x70 41 #define EXYNOS_TMU_REG_INTSTAT 0x74 42 #define EXYNOS_TMU_REG_INTCLEAR 0x78 43 44 #define EXYNOS_TMU_TRIM_TEMP_MASK 0xff 45 #define EXYNOS_TMU_GAIN_SHIFT 8 46 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 47 #define EXYNOS_TMU_CORE_ON 3 48 #define EXYNOS_TMU_CORE_OFF 2 49 #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50 50 51 /* Exynos4210 specific registers */ 52 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 53 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 54 #define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54 55 #define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58 56 #define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C 57 #define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60 58 #define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64 59 #define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68 60 #define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C 61 62 #define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1 63 #define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10 64 #define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100 65 #define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000 66 #define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111 67 68 /* Exynos5250 and Exynos4412 specific registers */ 69 #define EXYNOS_TMU_TRIMINFO_CON 0x14 70 #define EXYNOS_THD_TEMP_RISE 0x50 71 #define EXYNOS_THD_TEMP_FALL 0x54 72 #define EXYNOS_EMUL_CON 0x80 73 74 #define EXYNOS_TRIMINFO_RELOAD 0x1 75 #define EXYNOS_TMU_CLEAR_RISE_INT 0x111 76 #define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12) 77 #define EXYNOS_MUX_ADDR_VALUE 6 78 #define EXYNOS_MUX_ADDR_SHIFT 20 79 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 80 81 #define EFUSE_MIN_VALUE 40 82 #define EFUSE_MAX_VALUE 100 83 84 #ifdef CONFIG_THERMAL_EMULATION 85 #define EXYNOS_EMUL_TIME 0x57F0 86 #define EXYNOS_EMUL_TIME_SHIFT 16 87 #define EXYNOS_EMUL_DATA_SHIFT 8 88 #define EXYNOS_EMUL_DATA_MASK 0xFF 89 #define EXYNOS_EMUL_ENABLE 0x1 90 #endif /* CONFIG_THERMAL_EMULATION */ 91 92 struct exynos_tmu_data { 93 struct exynos_tmu_platform_data *pdata; 94 struct resource *mem; 95 void __iomem *base; 96 int irq; 97 enum soc_type soc; 98 struct work_struct irq_work; 99 struct mutex lock; 100 struct clk *clk; 101 u8 temp_error1, temp_error2; 102 }; 103 104 /* 105 * TMU treats temperature as a mapped temperature code. 106 * The temperature is converted differently depending on the calibration type. 107 */ 108 static int temp_to_code(struct exynos_tmu_data *data, u8 temp) 109 { 110 struct exynos_tmu_platform_data *pdata = data->pdata; 111 int temp_code; 112 113 if (data->soc == SOC_ARCH_EXYNOS4210) 114 /* temp should range between 25 and 125 */ 115 if (temp < 25 || temp > 125) { 116 temp_code = -EINVAL; 117 goto out; 118 } 119 120 switch (pdata->cal_type) { 121 case TYPE_TWO_POINT_TRIMMING: 122 temp_code = (temp - 25) * 123 (data->temp_error2 - data->temp_error1) / 124 (85 - 25) + data->temp_error1; 125 break; 126 case TYPE_ONE_POINT_TRIMMING: 127 temp_code = temp + data->temp_error1 - 25; 128 break; 129 default: 130 temp_code = temp + EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET; 131 break; 132 } 133 out: 134 return temp_code; 135 } 136 137 /* 138 * Calculate a temperature value from a temperature code. 139 * The unit of the temperature is degree Celsius. 140 */ 141 static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code) 142 { 143 struct exynos_tmu_platform_data *pdata = data->pdata; 144 int temp; 145 146 if (data->soc == SOC_ARCH_EXYNOS4210) 147 /* temp_code should range between 75 and 175 */ 148 if (temp_code < 75 || temp_code > 175) { 149 temp = -ENODATA; 150 goto out; 151 } 152 153 switch (pdata->cal_type) { 154 case TYPE_TWO_POINT_TRIMMING: 155 temp = (temp_code - data->temp_error1) * (85 - 25) / 156 (data->temp_error2 - data->temp_error1) + 25; 157 break; 158 case TYPE_ONE_POINT_TRIMMING: 159 temp = temp_code - data->temp_error1 + 25; 160 break; 161 default: 162 temp = temp_code - EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET; 163 break; 164 } 165 out: 166 return temp; 167 } 168 169 static int exynos_tmu_initialize(struct platform_device *pdev) 170 { 171 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 172 struct exynos_tmu_platform_data *pdata = data->pdata; 173 unsigned int status, trim_info; 174 unsigned int rising_threshold = 0, falling_threshold = 0; 175 int ret = 0, threshold_code, i, trigger_levs = 0; 176 177 mutex_lock(&data->lock); 178 clk_enable(data->clk); 179 180 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 181 if (!status) { 182 ret = -EBUSY; 183 goto out; 184 } 185 186 if (data->soc == SOC_ARCH_EXYNOS) { 187 __raw_writel(EXYNOS_TRIMINFO_RELOAD, 188 data->base + EXYNOS_TMU_TRIMINFO_CON); 189 } 190 /* Save trimming info in order to perform calibration */ 191 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 192 data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK; 193 data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK); 194 195 if ((EFUSE_MIN_VALUE > data->temp_error1) || 196 (data->temp_error1 > EFUSE_MAX_VALUE) || 197 (data->temp_error2 != 0)) 198 data->temp_error1 = pdata->efuse_value; 199 200 /* Count trigger levels to be enabled */ 201 for (i = 0; i < MAX_THRESHOLD_LEVS; i++) 202 if (pdata->trigger_levels[i]) 203 trigger_levs++; 204 205 if (data->soc == SOC_ARCH_EXYNOS4210) { 206 /* Write temperature code for threshold */ 207 threshold_code = temp_to_code(data, pdata->threshold); 208 if (threshold_code < 0) { 209 ret = threshold_code; 210 goto out; 211 } 212 writeb(threshold_code, 213 data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); 214 for (i = 0; i < trigger_levs; i++) 215 writeb(pdata->trigger_levels[i], 216 data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4); 217 218 writel(EXYNOS4210_TMU_INTCLEAR_VAL, 219 data->base + EXYNOS_TMU_REG_INTCLEAR); 220 } else if (data->soc == SOC_ARCH_EXYNOS) { 221 /* Write temperature code for rising and falling threshold */ 222 for (i = 0; i < trigger_levs; i++) { 223 threshold_code = temp_to_code(data, 224 pdata->trigger_levels[i]); 225 if (threshold_code < 0) { 226 ret = threshold_code; 227 goto out; 228 } 229 rising_threshold |= threshold_code << 8 * i; 230 if (pdata->threshold_falling) { 231 threshold_code = temp_to_code(data, 232 pdata->trigger_levels[i] - 233 pdata->threshold_falling); 234 if (threshold_code > 0) 235 falling_threshold |= 236 threshold_code << 8 * i; 237 } 238 } 239 240 writel(rising_threshold, 241 data->base + EXYNOS_THD_TEMP_RISE); 242 writel(falling_threshold, 243 data->base + EXYNOS_THD_TEMP_FALL); 244 245 writel(EXYNOS_TMU_CLEAR_RISE_INT | EXYNOS_TMU_CLEAR_FALL_INT, 246 data->base + EXYNOS_TMU_REG_INTCLEAR); 247 } 248 out: 249 clk_disable(data->clk); 250 mutex_unlock(&data->lock); 251 252 return ret; 253 } 254 255 static void exynos_tmu_control(struct platform_device *pdev, bool on) 256 { 257 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 258 struct exynos_tmu_platform_data *pdata = data->pdata; 259 unsigned int con, interrupt_en; 260 261 mutex_lock(&data->lock); 262 clk_enable(data->clk); 263 264 con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT | 265 pdata->gain << EXYNOS_TMU_GAIN_SHIFT; 266 267 if (data->soc == SOC_ARCH_EXYNOS) { 268 con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT; 269 con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT); 270 } 271 272 if (on) { 273 con |= EXYNOS_TMU_CORE_ON; 274 interrupt_en = pdata->trigger_level3_en << 12 | 275 pdata->trigger_level2_en << 8 | 276 pdata->trigger_level1_en << 4 | 277 pdata->trigger_level0_en; 278 if (pdata->threshold_falling) 279 interrupt_en |= interrupt_en << 16; 280 } else { 281 con |= EXYNOS_TMU_CORE_OFF; 282 interrupt_en = 0; /* Disable all interrupts */ 283 } 284 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); 285 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 286 287 clk_disable(data->clk); 288 mutex_unlock(&data->lock); 289 } 290 291 static int exynos_tmu_read(struct exynos_tmu_data *data) 292 { 293 u8 temp_code; 294 int temp; 295 296 mutex_lock(&data->lock); 297 clk_enable(data->clk); 298 299 temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 300 temp = code_to_temp(data, temp_code); 301 302 clk_disable(data->clk); 303 mutex_unlock(&data->lock); 304 305 return temp; 306 } 307 308 #ifdef CONFIG_THERMAL_EMULATION 309 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) 310 { 311 struct exynos_tmu_data *data = drv_data; 312 unsigned int reg; 313 int ret = -EINVAL; 314 315 if (data->soc == SOC_ARCH_EXYNOS4210) 316 goto out; 317 318 if (temp && temp < MCELSIUS) 319 goto out; 320 321 mutex_lock(&data->lock); 322 clk_enable(data->clk); 323 324 reg = readl(data->base + EXYNOS_EMUL_CON); 325 326 if (temp) { 327 temp /= MCELSIUS; 328 329 reg = (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT) | 330 (temp_to_code(data, temp) 331 << EXYNOS_EMUL_DATA_SHIFT) | EXYNOS_EMUL_ENABLE; 332 } else { 333 reg &= ~EXYNOS_EMUL_ENABLE; 334 } 335 336 writel(reg, data->base + EXYNOS_EMUL_CON); 337 338 clk_disable(data->clk); 339 mutex_unlock(&data->lock); 340 return 0; 341 out: 342 return ret; 343 } 344 #else 345 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) 346 { return -EINVAL; } 347 #endif/*CONFIG_THERMAL_EMULATION*/ 348 349 static void exynos_tmu_work(struct work_struct *work) 350 { 351 struct exynos_tmu_data *data = container_of(work, 352 struct exynos_tmu_data, irq_work); 353 354 exynos_report_trigger(); 355 mutex_lock(&data->lock); 356 clk_enable(data->clk); 357 if (data->soc == SOC_ARCH_EXYNOS) 358 writel(EXYNOS_TMU_CLEAR_RISE_INT | 359 EXYNOS_TMU_CLEAR_FALL_INT, 360 data->base + EXYNOS_TMU_REG_INTCLEAR); 361 else 362 writel(EXYNOS4210_TMU_INTCLEAR_VAL, 363 data->base + EXYNOS_TMU_REG_INTCLEAR); 364 clk_disable(data->clk); 365 mutex_unlock(&data->lock); 366 367 enable_irq(data->irq); 368 } 369 370 static irqreturn_t exynos_tmu_irq(int irq, void *id) 371 { 372 struct exynos_tmu_data *data = id; 373 374 disable_irq_nosync(irq); 375 schedule_work(&data->irq_work); 376 377 return IRQ_HANDLED; 378 } 379 static struct thermal_sensor_conf exynos_sensor_conf = { 380 .name = "exynos-therm", 381 .read_temperature = (int (*)(void *))exynos_tmu_read, 382 .write_emul_temp = exynos_tmu_set_emulation, 383 }; 384 385 #ifdef CONFIG_OF 386 static const struct of_device_id exynos_tmu_match[] = { 387 { 388 .compatible = "samsung,exynos4210-tmu", 389 .data = (void *)EXYNOS4210_TMU_DRV_DATA, 390 }, 391 { 392 .compatible = "samsung,exynos4412-tmu", 393 .data = (void *)EXYNOS5250_TMU_DRV_DATA, 394 }, 395 { 396 .compatible = "samsung,exynos5250-tmu", 397 .data = (void *)EXYNOS5250_TMU_DRV_DATA, 398 }, 399 {}, 400 }; 401 MODULE_DEVICE_TABLE(of, exynos_tmu_match); 402 #endif 403 404 static struct platform_device_id exynos_tmu_driver_ids[] = { 405 { 406 .name = "exynos4210-tmu", 407 .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA, 408 }, 409 { 410 .name = "exynos5250-tmu", 411 .driver_data = (kernel_ulong_t)EXYNOS5250_TMU_DRV_DATA, 412 }, 413 { }, 414 }; 415 MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids); 416 417 static inline struct exynos_tmu_platform_data *exynos_get_driver_data( 418 struct platform_device *pdev) 419 { 420 #ifdef CONFIG_OF 421 if (pdev->dev.of_node) { 422 const struct of_device_id *match; 423 match = of_match_node(exynos_tmu_match, pdev->dev.of_node); 424 if (!match) 425 return NULL; 426 return (struct exynos_tmu_platform_data *) match->data; 427 } 428 #endif 429 return (struct exynos_tmu_platform_data *) 430 platform_get_device_id(pdev)->driver_data; 431 } 432 433 static int exynos_tmu_probe(struct platform_device *pdev) 434 { 435 struct exynos_tmu_data *data; 436 struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data; 437 int ret, i; 438 439 if (!pdata) 440 pdata = exynos_get_driver_data(pdev); 441 442 if (!pdata) { 443 dev_err(&pdev->dev, "No platform init data supplied.\n"); 444 return -ENODEV; 445 } 446 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 447 GFP_KERNEL); 448 if (!data) { 449 dev_err(&pdev->dev, "Failed to allocate driver structure\n"); 450 return -ENOMEM; 451 } 452 453 data->irq = platform_get_irq(pdev, 0); 454 if (data->irq < 0) { 455 dev_err(&pdev->dev, "Failed to get platform irq\n"); 456 return data->irq; 457 } 458 459 INIT_WORK(&data->irq_work, exynos_tmu_work); 460 461 data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 462 data->base = devm_ioremap_resource(&pdev->dev, data->mem); 463 if (IS_ERR(data->base)) 464 return PTR_ERR(data->base); 465 466 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, 467 IRQF_TRIGGER_RISING, "exynos-tmu", data); 468 if (ret) { 469 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 470 return ret; 471 } 472 473 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); 474 if (IS_ERR(data->clk)) { 475 dev_err(&pdev->dev, "Failed to get clock\n"); 476 return PTR_ERR(data->clk); 477 } 478 479 ret = clk_prepare(data->clk); 480 if (ret) 481 return ret; 482 483 if (pdata->type == SOC_ARCH_EXYNOS || 484 pdata->type == SOC_ARCH_EXYNOS4210) 485 data->soc = pdata->type; 486 else { 487 ret = -EINVAL; 488 dev_err(&pdev->dev, "Platform not supported\n"); 489 goto err_clk; 490 } 491 492 data->pdata = pdata; 493 platform_set_drvdata(pdev, data); 494 mutex_init(&data->lock); 495 496 ret = exynos_tmu_initialize(pdev); 497 if (ret) { 498 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 499 goto err_clk; 500 } 501 502 exynos_tmu_control(pdev, true); 503 504 /* Register the sensor with thermal management interface */ 505 (&exynos_sensor_conf)->private_data = data; 506 exynos_sensor_conf.trip_data.trip_count = pdata->trigger_level0_en + 507 pdata->trigger_level1_en + pdata->trigger_level2_en + 508 pdata->trigger_level3_en; 509 510 for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++) 511 exynos_sensor_conf.trip_data.trip_val[i] = 512 pdata->threshold + pdata->trigger_levels[i]; 513 514 exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling; 515 516 exynos_sensor_conf.cooling_data.freq_clip_count = 517 pdata->freq_tab_count; 518 for (i = 0; i < pdata->freq_tab_count; i++) { 519 exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max = 520 pdata->freq_tab[i].freq_clip_max; 521 exynos_sensor_conf.cooling_data.freq_data[i].temp_level = 522 pdata->freq_tab[i].temp_level; 523 } 524 525 ret = exynos_register_thermal(&exynos_sensor_conf); 526 if (ret) { 527 dev_err(&pdev->dev, "Failed to register thermal interface\n"); 528 goto err_clk; 529 } 530 531 return 0; 532 err_clk: 533 clk_unprepare(data->clk); 534 return ret; 535 } 536 537 static int exynos_tmu_remove(struct platform_device *pdev) 538 { 539 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 540 541 exynos_tmu_control(pdev, false); 542 543 exynos_unregister_thermal(); 544 545 clk_unprepare(data->clk); 546 547 return 0; 548 } 549 550 #ifdef CONFIG_PM_SLEEP 551 static int exynos_tmu_suspend(struct device *dev) 552 { 553 exynos_tmu_control(to_platform_device(dev), false); 554 555 return 0; 556 } 557 558 static int exynos_tmu_resume(struct device *dev) 559 { 560 struct platform_device *pdev = to_platform_device(dev); 561 562 exynos_tmu_initialize(pdev); 563 exynos_tmu_control(pdev, true); 564 565 return 0; 566 } 567 568 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, 569 exynos_tmu_suspend, exynos_tmu_resume); 570 #define EXYNOS_TMU_PM (&exynos_tmu_pm) 571 #else 572 #define EXYNOS_TMU_PM NULL 573 #endif 574 575 static struct platform_driver exynos_tmu_driver = { 576 .driver = { 577 .name = "exynos-tmu", 578 .owner = THIS_MODULE, 579 .pm = EXYNOS_TMU_PM, 580 .of_match_table = of_match_ptr(exynos_tmu_match), 581 }, 582 .probe = exynos_tmu_probe, 583 .remove = exynos_tmu_remove, 584 .id_table = exynos_tmu_driver_ids, 585 }; 586 587 module_platform_driver(exynos_tmu_driver); 588 589 MODULE_DESCRIPTION("EXYNOS TMU Driver"); 590 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 591 MODULE_LICENSE("GPL"); 592 MODULE_ALIAS("platform:exynos-tmu"); 593