exynos_tmu.c (09d29426bce847330440ba735880ab0ef595cad2) exynos_tmu.c (e3ed36499bc95658c28557c0f4a6364f30e51bd0)
1/*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
4 * Copyright (C) 2014 Samsung Electronics
5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
6 * Lukasz Majewski <l.majewski@samsung.com>
7 *
8 * Copyright (C) 2011 Samsung Electronics

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180 * @base_second: base address of the common registers of the TMU controller.
181 * @irq: irq number of the TMU controller.
182 * @soc: id of the SOC type.
183 * @irq_work: pointer to the irq work structure.
184 * @lock: lock to implement synchronization.
185 * @clk: pointer to the clock structure.
186 * @clk_sec: pointer to the clock structure for accessing the base_second.
187 * @sclk: pointer to the clock structure for accessing the tmu special clk.
1/*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
4 * Copyright (C) 2014 Samsung Electronics
5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
6 * Lukasz Majewski <l.majewski@samsung.com>
7 *
8 * Copyright (C) 2011 Samsung Electronics

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180 * @base_second: base address of the common registers of the TMU controller.
181 * @irq: irq number of the TMU controller.
182 * @soc: id of the SOC type.
183 * @irq_work: pointer to the irq work structure.
184 * @lock: lock to implement synchronization.
185 * @clk: pointer to the clock structure.
186 * @clk_sec: pointer to the clock structure for accessing the base_second.
187 * @sclk: pointer to the clock structure for accessing the tmu special clk.
188 * @efuse_value: SoC defined fuse value
189 * @min_efuse_value: minimum valid trimming data
190 * @max_efuse_value: maximum valid trimming data
188 * @temp_error1: fused value of the first point trim.
189 * @temp_error2: fused value of the second point trim.
190 * @regulator: pointer to the TMU regulator structure.
191 * @reg_conf: pointer to structure to register with core thermal.
192 * @ntrip: number of supported trip points.
193 * @enabled: current status of TMU device
194 * @tmu_initialize: SoC specific TMU initialization method
195 * @tmu_control: SoC specific TMU control method

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202 struct exynos_tmu_platform_data *pdata;
203 void __iomem *base;
204 void __iomem *base_second;
205 int irq;
206 enum soc_type soc;
207 struct work_struct irq_work;
208 struct mutex lock;
209 struct clk *clk, *clk_sec, *sclk;
191 * @temp_error1: fused value of the first point trim.
192 * @temp_error2: fused value of the second point trim.
193 * @regulator: pointer to the TMU regulator structure.
194 * @reg_conf: pointer to structure to register with core thermal.
195 * @ntrip: number of supported trip points.
196 * @enabled: current status of TMU device
197 * @tmu_initialize: SoC specific TMU initialization method
198 * @tmu_control: SoC specific TMU control method

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205 struct exynos_tmu_platform_data *pdata;
206 void __iomem *base;
207 void __iomem *base_second;
208 int irq;
209 enum soc_type soc;
210 struct work_struct irq_work;
211 struct mutex lock;
212 struct clk *clk, *clk_sec, *sclk;
213 u32 efuse_value;
214 u32 min_efuse_value;
215 u32 max_efuse_value;
210 u16 temp_error1, temp_error2;
211 struct regulator *regulator;
212 struct thermal_zone_device *tzd;
213 unsigned int ntrip;
214 bool enabled;
215
216 int (*tmu_initialize)(struct platform_device *pdev);
217 void (*tmu_control)(struct platform_device *pdev, bool on);

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278 return (temp_code - data->temp_error1) *
279 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) /
280 (data->temp_error2 - data->temp_error1) +
281 EXYNOS_FIRST_POINT_TRIM;
282}
283
284static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
285{
216 u16 temp_error1, temp_error2;
217 struct regulator *regulator;
218 struct thermal_zone_device *tzd;
219 unsigned int ntrip;
220 bool enabled;
221
222 int (*tmu_initialize)(struct platform_device *pdev);
223 void (*tmu_control)(struct platform_device *pdev, bool on);

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284 return (temp_code - data->temp_error1) *
285 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) /
286 (data->temp_error2 - data->temp_error1) +
287 EXYNOS_FIRST_POINT_TRIM;
288}
289
290static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
291{
286 struct exynos_tmu_platform_data *pdata = data->pdata;
287
288 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
289 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
290 EXYNOS_TMU_TEMP_MASK);
291
292 if (!data->temp_error1 ||
292 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
293 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
294 EXYNOS_TMU_TEMP_MASK);
295
296 if (!data->temp_error1 ||
293 (pdata->min_efuse_value > data->temp_error1) ||
294 (data->temp_error1 > pdata->max_efuse_value))
295 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
297 (data->min_efuse_value > data->temp_error1) ||
298 (data->temp_error1 > data->max_efuse_value))
299 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
296
297 if (!data->temp_error2)
298 data->temp_error2 =
300
301 if (!data->temp_error2)
302 data->temp_error2 =
299 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
303 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
300 EXYNOS_TMU_TEMP_MASK;
301}
302
303static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
304{
305 struct thermal_zone_device *tz = data->tzd;
306 const struct thermal_trip * const trips =
307 of_thermal_get_trip_points(tz);

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650
651 return 0;
652}
653
654static int exynos7_tmu_initialize(struct platform_device *pdev)
655{
656 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
657 struct thermal_zone_device *tz = data->tzd;
304 EXYNOS_TMU_TEMP_MASK;
305}
306
307static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
308{
309 struct thermal_zone_device *tz = data->tzd;
310 const struct thermal_trip * const trips =
311 of_thermal_get_trip_points(tz);

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654
655 return 0;
656}
657
658static int exynos7_tmu_initialize(struct platform_device *pdev)
659{
660 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
661 struct thermal_zone_device *tz = data->tzd;
658 struct exynos_tmu_platform_data *pdata = data->pdata;
659 unsigned int status, trim_info;
660 unsigned int rising_threshold = 0, falling_threshold = 0;
661 int ret = 0, threshold_code, i;
662 int temp, temp_hist;
663 unsigned int reg_off, bit_off;
664
665 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
666 if (!status) {
667 ret = -EBUSY;
668 goto out;
669 }
670
671 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
672
673 data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK;
674 if (!data->temp_error1 ||
662 unsigned int status, trim_info;
663 unsigned int rising_threshold = 0, falling_threshold = 0;
664 int ret = 0, threshold_code, i;
665 int temp, temp_hist;
666 unsigned int reg_off, bit_off;
667
668 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
669 if (!status) {
670 ret = -EBUSY;
671 goto out;
672 }
673
674 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
675
676 data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK;
677 if (!data->temp_error1 ||
675 (pdata->min_efuse_value > data->temp_error1) ||
676 (data->temp_error1 > pdata->max_efuse_value))
677 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
678 (data->min_efuse_value > data->temp_error1) ||
679 (data->temp_error1 > data->max_efuse_value))
680 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
678
679 /* Write temperature code for rising and falling threshold */
680 for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
681 /*
682 * On exynos7 there are 4 rising and 4 falling threshold
683 * registers (0x50-0x5c and 0x60-0x6c respectively). Each
684 * register holds the value of two threshold levels (at bit
685 * offsets 0 and 16). Based on the fact that there are atmost

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1131
1132 of_node_get(np);
1133
1134 ret = of_property_read_u32(np, "samsung,tmu_gain", &value);
1135 pdata->gain = (u8)value;
1136 of_property_read_u32(np, "samsung,tmu_reference_voltage", &value);
1137 pdata->reference_voltage = (u8)value;
1138
681
682 /* Write temperature code for rising and falling threshold */
683 for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
684 /*
685 * On exynos7 there are 4 rising and 4 falling threshold
686 * registers (0x50-0x5c and 0x60-0x6c respectively). Each
687 * register holds the value of two threshold levels (at bit
688 * offsets 0 and 16). Based on the fact that there are atmost

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1134
1135 of_node_get(np);
1136
1137 ret = of_property_read_u32(np, "samsung,tmu_gain", &value);
1138 pdata->gain = (u8)value;
1139 of_property_read_u32(np, "samsung,tmu_reference_voltage", &value);
1140 pdata->reference_voltage = (u8)value;
1141
1139 of_property_read_u32(np, "samsung,tmu_efuse_value",
1140 &pdata->efuse_value);
1141 of_property_read_u32(np, "samsung,tmu_min_efuse_value",
1142 &pdata->min_efuse_value);
1143 of_property_read_u32(np, "samsung,tmu_max_efuse_value",
1144 &pdata->max_efuse_value);
1145
1146 of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type);
1147
1148 of_node_put(np);
1149 return 0;
1150}
1151
1152static int exynos_map_dt_data(struct platform_device *pdev)
1153{

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1191
1192 switch (data->soc) {
1193 case SOC_ARCH_EXYNOS4210:
1194 data->tmu_initialize = exynos4210_tmu_initialize;
1195 data->tmu_control = exynos4210_tmu_control;
1196 data->tmu_read = exynos4210_tmu_read;
1197 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1198 data->ntrip = 4;
1142 of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type);
1143
1144 of_node_put(np);
1145 return 0;
1146}
1147
1148static int exynos_map_dt_data(struct platform_device *pdev)
1149{

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1187
1188 switch (data->soc) {
1189 case SOC_ARCH_EXYNOS4210:
1190 data->tmu_initialize = exynos4210_tmu_initialize;
1191 data->tmu_control = exynos4210_tmu_control;
1192 data->tmu_read = exynos4210_tmu_read;
1193 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1194 data->ntrip = 4;
1195 data->efuse_value = 55;
1196 data->min_efuse_value = 40;
1197 data->max_efuse_value = 100;
1199 break;
1200 case SOC_ARCH_EXYNOS3250:
1201 case SOC_ARCH_EXYNOS4412:
1202 case SOC_ARCH_EXYNOS5250:
1203 case SOC_ARCH_EXYNOS5260:
1204 case SOC_ARCH_EXYNOS5420:
1205 case SOC_ARCH_EXYNOS5420_TRIMINFO:
1206 data->tmu_initialize = exynos4412_tmu_initialize;
1207 data->tmu_control = exynos4210_tmu_control;
1208 data->tmu_read = exynos4412_tmu_read;
1209 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1210 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1211 data->ntrip = 4;
1198 break;
1199 case SOC_ARCH_EXYNOS3250:
1200 case SOC_ARCH_EXYNOS4412:
1201 case SOC_ARCH_EXYNOS5250:
1202 case SOC_ARCH_EXYNOS5260:
1203 case SOC_ARCH_EXYNOS5420:
1204 case SOC_ARCH_EXYNOS5420_TRIMINFO:
1205 data->tmu_initialize = exynos4412_tmu_initialize;
1206 data->tmu_control = exynos4210_tmu_control;
1207 data->tmu_read = exynos4412_tmu_read;
1208 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1209 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1210 data->ntrip = 4;
1211 data->efuse_value = 55;
1212 if (data->soc != SOC_ARCH_EXYNOS5420 &&
1213 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)
1214 data->min_efuse_value = 40;
1215 else
1216 data->min_efuse_value = 0;
1217 data->max_efuse_value = 100;
1212 break;
1213 case SOC_ARCH_EXYNOS5433:
1214 data->tmu_initialize = exynos5433_tmu_initialize;
1215 data->tmu_control = exynos5433_tmu_control;
1216 data->tmu_read = exynos4412_tmu_read;
1217 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1218 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1219 data->ntrip = 8;
1218 break;
1219 case SOC_ARCH_EXYNOS5433:
1220 data->tmu_initialize = exynos5433_tmu_initialize;
1221 data->tmu_control = exynos5433_tmu_control;
1222 data->tmu_read = exynos4412_tmu_read;
1223 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1224 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1225 data->ntrip = 8;
1226 data->efuse_value = 75;
1227 data->min_efuse_value = 40;
1228 data->max_efuse_value = 150;
1220 break;
1221 case SOC_ARCH_EXYNOS5440:
1222 data->tmu_initialize = exynos5440_tmu_initialize;
1223 data->tmu_control = exynos5440_tmu_control;
1224 data->tmu_read = exynos5440_tmu_read;
1225 data->tmu_set_emulation = exynos5440_tmu_set_emulation;
1226 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
1227 data->ntrip = 4;
1229 break;
1230 case SOC_ARCH_EXYNOS5440:
1231 data->tmu_initialize = exynos5440_tmu_initialize;
1232 data->tmu_control = exynos5440_tmu_control;
1233 data->tmu_read = exynos5440_tmu_read;
1234 data->tmu_set_emulation = exynos5440_tmu_set_emulation;
1235 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
1236 data->ntrip = 4;
1237 data->efuse_value = 0x5d2d;
1238 data->min_efuse_value = 16;
1239 data->max_efuse_value = 76;
1228 break;
1229 case SOC_ARCH_EXYNOS7:
1230 data->tmu_initialize = exynos7_tmu_initialize;
1231 data->tmu_control = exynos7_tmu_control;
1232 data->tmu_read = exynos7_tmu_read;
1233 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1234 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1235 data->ntrip = 8;
1240 break;
1241 case SOC_ARCH_EXYNOS7:
1242 data->tmu_initialize = exynos7_tmu_initialize;
1243 data->tmu_control = exynos7_tmu_control;
1244 data->tmu_read = exynos7_tmu_read;
1245 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1246 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1247 data->ntrip = 8;
1248 data->efuse_value = 75;
1249 data->min_efuse_value = 15;
1250 data->max_efuse_value = 100;
1236 break;
1237 default:
1238 dev_err(&pdev->dev, "Platform not supported\n");
1239 return -EINVAL;
1240 }
1241
1242 /*
1243 * Check if the TMU shares some registers and then try to map the

--- 214 unchanged lines hidden --- 		1251 break;
1252 default:
1253 dev_err(&pdev->dev, "Platform not supported\n");
1254 return -EINVAL;
1255 }
1256
1257 /*
1258 * Check if the TMU shares some registers and then try to map the

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