pmc.c (95b780b3d7e3f1900e09dfe90e959f220a8df343) pmc.c (21b4991051780b49b217c363f79366ed94c3b4b7)
1/*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *

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59
60#define PWRGATE_TOGGLE 0x30
61#define PWRGATE_TOGGLE_START BIT(8)
62
63#define REMOVE_CLAMPING 0x34
64
65#define PWRGATE_STATUS 0x38
66
1/*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *

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59
60#define PWRGATE_TOGGLE 0x30
61#define PWRGATE_TOGGLE_START BIT(8)
62
63#define REMOVE_CLAMPING 0x34
64
65#define PWRGATE_STATUS 0x38
66
67#define PMC_PWR_DET 0x48
68
67#define PMC_SCRATCH0 0x50
68#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
69#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
70#define PMC_SCRATCH0_MODE_RCM BIT(1)
71#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
72 PMC_SCRATCH0_MODE_BOOTLOADER | \
73 PMC_SCRATCH0_MODE_RCM)
74
75#define PMC_CPUPWRGOOD_TIMER 0xc8
76#define PMC_CPUPWROFF_TIMER 0xcc
77
69#define PMC_SCRATCH0 0x50
70#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
71#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
72#define PMC_SCRATCH0_MODE_RCM BIT(1)
73#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
74 PMC_SCRATCH0_MODE_BOOTLOADER | \
75 PMC_SCRATCH0_MODE_RCM)
76
77#define PMC_CPUPWRGOOD_TIMER 0xc8
78#define PMC_CPUPWROFF_TIMER 0xcc
79
80#define PMC_PWR_DET_VALUE 0xe4
81
78#define PMC_SCRATCH41 0x140
79
80#define PMC_SENSOR_CTRL 0x1b0
81#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
82#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
83
84#define PMC_RST_STATUS 0x1b4
85#define PMC_RST_STATUS_POR 0

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119 struct tegra_pmc *pmc;
120 unsigned int id;
121 struct clk **clks;
122 unsigned int num_clks;
123 struct reset_control **resets;
124 unsigned int num_resets;
125};
126
82#define PMC_SCRATCH41 0x140
83
84#define PMC_SENSOR_CTRL 0x1b0
85#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
86#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
87
88#define PMC_RST_STATUS 0x1b4
89#define PMC_RST_STATUS_POR 0

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123 struct tegra_pmc *pmc;
124 unsigned int id;
125 struct clk **clks;
126 unsigned int num_clks;
127 struct reset_control **resets;
128 unsigned int num_resets;
129};
130
131struct tegra_io_pad_soc {
132 enum tegra_io_pad id;
133 unsigned int dpd;
134 unsigned int voltage;
135};
136
127struct tegra_pmc_soc {
128 unsigned int num_powergates;
129 const char *const *powergates;
130 unsigned int num_cpu_powergates;
131 const u8 *cpu_powergates;
132
133 bool has_tsense_reset;
134 bool has_gpu_clamps;
137struct tegra_pmc_soc {
138 unsigned int num_powergates;
139 const char *const *powergates;
140 unsigned int num_cpu_powergates;
141 const u8 *cpu_powergates;
142
143 bool has_tsense_reset;
144 bool has_gpu_clamps;
145
146 const struct tegra_io_pad_soc *io_pads;
147 unsigned int num_io_pads;
135};
136
137/**
138 * struct tegra_pmc - NVIDIA Tegra PMC
139 * @dev: pointer to PMC device structure
140 * @base: pointer to I/O remapped register region
141 * @clk: pointer to pclk clock
142 * @soc: pointer to SoC data structure

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903 for_each_child_of_node(np, child) {
904 tegra_powergate_add(pmc, child);
905 of_node_put(child);
906 }
907
908 of_node_put(np);
909}
910
148};
149
150/**
151 * struct tegra_pmc - NVIDIA Tegra PMC
152 * @dev: pointer to PMC device structure
153 * @base: pointer to I/O remapped register region
154 * @clk: pointer to pclk clock
155 * @soc: pointer to SoC data structure

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916 for_each_child_of_node(np, child) {
917 tegra_powergate_add(pmc, child);
918 of_node_put(child);
919 }
920
921 of_node_put(np);
922}
923
911static int tegra_io_rail_prepare(unsigned int id, unsigned long *request,
912 unsigned long *status, unsigned int *bit)
924static const struct tegra_io_pad_soc *
925tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
913{
926{
927 unsigned int i;
928
929 for (i = 0; i < pmc->soc->num_io_pads; i++)
930 if (pmc->soc->io_pads[i].id == id)
931 return &pmc->soc->io_pads[i];
932
933 return NULL;
934}
935
936static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
937 unsigned long *status, unsigned int *bit)
938{
939 const struct tegra_io_pad_soc *pad;
914 unsigned long rate, value;
915
940 unsigned long rate, value;
941
916 *bit = id % 32;
942 pad = tegra_io_pad_find(pmc, id);
943 if (!pad)
944 return -ENOENT;
917
945
918 /*
919 * There are two sets of 30 bits to select IO rails, but bits 30 and
920 * 31 are control bits rather than IO rail selection bits.
921 */
922 if (id > 63 || *bit == 30 || *bit == 31)
923 return -EINVAL;
946 if (pad->dpd == UINT_MAX)
947 return -ENOTSUPP;
924
948
925 if (id < 32) {
949 *bit = pad->dpd % 32;
950
951 if (pad->dpd < 32) {
926 *status = IO_DPD_STATUS;
927 *request = IO_DPD_REQ;
928 } else {
929 *status = IO_DPD2_STATUS;
930 *request = IO_DPD2_REQ;
931 }
932
933 rate = clk_get_rate(pmc->clk);
934
935 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
936
937 /* must be at least 200 ns, in APB (PCLK) clock cycles */
938 value = DIV_ROUND_UP(1000000000, rate);
939 value = DIV_ROUND_UP(200, value);
940 tegra_pmc_writel(value, SEL_DPD_TIM);
941
942 return 0;
943}
944
952 *status = IO_DPD_STATUS;
953 *request = IO_DPD_REQ;
954 } else {
955 *status = IO_DPD2_STATUS;
956 *request = IO_DPD2_REQ;
957 }
958
959 rate = clk_get_rate(pmc->clk);
960
961 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
962
963 /* must be at least 200 ns, in APB (PCLK) clock cycles */
964 value = DIV_ROUND_UP(1000000000, rate);
965 value = DIV_ROUND_UP(200, value);
966 tegra_pmc_writel(value, SEL_DPD_TIM);
967
968 return 0;
969}
970
945static int tegra_io_rail_poll(unsigned long offset, u32 mask,
946 u32 val, unsigned long timeout)
971static int tegra_io_pad_poll(unsigned long offset, u32 mask,
972 u32 val, unsigned long timeout)
947{
948 u32 value;
949
950 timeout = jiffies + msecs_to_jiffies(timeout);
951
952 while (time_after(timeout, jiffies)) {
953 value = tegra_pmc_readl(offset);
954 if ((value & mask) == val)
955 return 0;
956
957 usleep_range(250, 1000);
958 }
959
960 return -ETIMEDOUT;
961}
962
973{
974 u32 value;
975
976 timeout = jiffies + msecs_to_jiffies(timeout);
977
978 while (time_after(timeout, jiffies)) {
979 value = tegra_pmc_readl(offset);
980 if ((value & mask) == val)
981 return 0;
982
983 usleep_range(250, 1000);
984 }
985
986 return -ETIMEDOUT;
987}
988
963static void tegra_io_rail_unprepare(void)
989static void tegra_io_pad_unprepare(void)
964{
965 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
966}
967
990{
991 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
992}
993
968int tegra_io_rail_power_on(unsigned int id)
994/**
995 * tegra_io_pad_power_enable() - enable power to I/O pad
996 * @id: Tegra I/O pad ID for which to enable power
997 *
998 * Returns: 0 on success or a negative error code on failure.
999 */
1000int tegra_io_pad_power_enable(enum tegra_io_pad id)
969{
970 unsigned long request, status;
971 unsigned int bit;
972 int err;
973
974 mutex_lock(&pmc->powergates_lock);
975
1001{
1002 unsigned long request, status;
1003 unsigned int bit;
1004 int err;
1005
1006 mutex_lock(&pmc->powergates_lock);
1007
976 err = tegra_io_rail_prepare(id, &request, &status, &bit);
977 if (err)
978 goto error;
1008 err = tegra_io_pad_prepare(id, &request, &status, &bit);
1009 if (err < 0) {
1010 dev_err(pmc->dev, "tegra_io_pad_prepare() failed: %d\n", err);
1011 goto unlock;
1012 }
979
980 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | BIT(bit), request);
981
1013
1014 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | BIT(bit), request);
1015
982 err = tegra_io_rail_poll(status, BIT(bit), 0, 250);
983 if (err) {
984 pr_info("tegra_io_rail_poll() failed: %d\n", err);
985 goto error;
1016 err = tegra_io_pad_poll(status, BIT(bit), 0, 250);
1017 if (err < 0) {
1018 dev_err(pmc->dev, "tegra_io_pad_poll() failed: %d\n", err);
1019 goto unlock;
986 }
987
1020 }
1021
988 tegra_io_rail_unprepare();
1022 tegra_io_pad_unprepare();
989
1023
990error:
1024unlock:
991 mutex_unlock(&pmc->powergates_lock);
1025 mutex_unlock(&pmc->powergates_lock);
992
993 return err;
994}
1026 return err;
1027}
995EXPORT_SYMBOL(tegra_io_rail_power_on);
1028EXPORT_SYMBOL(tegra_io_pad_power_enable);
996
1029
997int tegra_io_rail_power_off(unsigned int id)
1030/**
1031 * tegra_io_pad_power_disable() - disable power to I/O pad
1032 * @id: Tegra I/O pad ID for which to disable power
1033 *
1034 * Returns: 0 on success or a negative error code on failure.
1035 */
1036int tegra_io_pad_power_disable(enum tegra_io_pad id)
998{
999 unsigned long request, status;
1000 unsigned int bit;
1001 int err;
1002
1003 mutex_lock(&pmc->powergates_lock);
1004
1037{
1038 unsigned long request, status;
1039 unsigned int bit;
1040 int err;
1041
1042 mutex_lock(&pmc->powergates_lock);
1043
1005 err = tegra_io_rail_prepare(id, &request, &status, &bit);
1006 if (err) {
1007 pr_info("tegra_io_rail_prepare() failed: %d\n", err);
1008 goto error;
1044 err = tegra_io_pad_prepare(id, &request, &status, &bit);
1045 if (err < 0) {
1046 dev_err(pmc->dev, "tegra_io_pad_prepare() failed: %d\n", err);
1047 goto unlock;
1009 }
1010
1011 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | BIT(bit), request);
1012
1048 }
1049
1050 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | BIT(bit), request);
1051
1013 err = tegra_io_rail_poll(status, BIT(bit), BIT(bit), 250);
1014 if (err)
1015 goto error;
1052 err = tegra_io_pad_poll(status, BIT(bit), BIT(bit), 250);
1053 if (err < 0) {
1054 dev_err(pmc->dev, "tegra_io_pad_poll() failed: %d\n", err);
1055 goto unlock;
1056 }
1016
1057
1017 tegra_io_rail_unprepare();
1058 tegra_io_pad_unprepare();
1018
1059
1019error:
1060unlock:
1020 mutex_unlock(&pmc->powergates_lock);
1061 mutex_unlock(&pmc->powergates_lock);
1021
1022 return err;
1023}
1062 return err;
1063}
1064EXPORT_SYMBOL(tegra_io_pad_power_disable);
1065
1066int tegra_io_pad_set_voltage(enum tegra_io_pad id,
1067 enum tegra_io_pad_voltage voltage)
1068{
1069 const struct tegra_io_pad_soc *pad;
1070 u32 value;
1071
1072 pad = tegra_io_pad_find(pmc, id);
1073 if (!pad)
1074 return -ENOENT;
1075
1076 if (pad->voltage == UINT_MAX)
1077 return -ENOTSUPP;
1078
1079 mutex_lock(&pmc->powergates_lock);
1080
1081 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1082 value = tegra_pmc_readl(PMC_PWR_DET);
1083 value |= BIT(pad->voltage);
1084 tegra_pmc_writel(value, PMC_PWR_DET);
1085
1086 /* update I/O voltage */
1087 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1088
1089 if (voltage == TEGRA_IO_PAD_1800000UV)
1090 value &= ~BIT(pad->voltage);
1091 else
1092 value |= BIT(pad->voltage);
1093
1094 tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
1095
1096 mutex_unlock(&pmc->powergates_lock);
1097
1098 usleep_range(100, 250);
1099
1100 return 0;
1101}
1102EXPORT_SYMBOL(tegra_io_pad_set_voltage);
1103
1104int tegra_io_pad_get_voltage(enum tegra_io_pad id)
1105{
1106 const struct tegra_io_pad_soc *pad;
1107 u32 value;
1108
1109 pad = tegra_io_pad_find(pmc, id);
1110 if (!pad)
1111 return -ENOENT;
1112
1113 if (pad->voltage == UINT_MAX)
1114 return -ENOTSUPP;
1115
1116 value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
1117
1118 if ((value & BIT(pad->voltage)) == 0)
1119 return TEGRA_IO_PAD_1800000UV;
1120
1121 return TEGRA_IO_PAD_3300000UV;
1122}
1123EXPORT_SYMBOL(tegra_io_pad_get_voltage);
1124
1125/**
1126 * tegra_io_rail_power_on() - enable power to I/O rail
1127 * @id: Tegra I/O pad ID for which to enable power
1128 *
1129 * See also: tegra_io_pad_power_enable()
1130 */
1131int tegra_io_rail_power_on(unsigned int id)
1132{
1133 return tegra_io_pad_power_enable(id);
1134}
1135EXPORT_SYMBOL(tegra_io_rail_power_on);
1136
1137/**
1138 * tegra_io_rail_power_off() - disable power to I/O rail
1139 * @id: Tegra I/O pad ID for which to disable power
1140 *
1141 * See also: tegra_io_pad_power_disable()
1142 */
1143int tegra_io_rail_power_off(unsigned int id)
1144{
1145 return tegra_io_pad_power_disable(id);
1146}
1024EXPORT_SYMBOL(tegra_io_rail_power_off);
1025
1026#ifdef CONFIG_PM_SLEEP
1027enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1028{
1029 return pmc->suspend_mode;
1030}
1031

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1449
1450static const u8 tegra124_cpu_powergates[] = {
1451 TEGRA_POWERGATE_CPU0,
1452 TEGRA_POWERGATE_CPU1,
1453 TEGRA_POWERGATE_CPU2,
1454 TEGRA_POWERGATE_CPU3,
1455};
1456
1147EXPORT_SYMBOL(tegra_io_rail_power_off);
1148
1149#ifdef CONFIG_PM_SLEEP
1150enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1151{
1152 return pmc->suspend_mode;
1153}
1154

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1572
1573static const u8 tegra124_cpu_powergates[] = {
1574 TEGRA_POWERGATE_CPU0,
1575 TEGRA_POWERGATE_CPU1,
1576 TEGRA_POWERGATE_CPU2,
1577 TEGRA_POWERGATE_CPU3,
1578};
1579
1580static const struct tegra_io_pad_soc tegra124_io_pads[] = {
1581 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1582 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
1583 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
1584 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
1585 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1586 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1587 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1588 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1589 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1590 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1591 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1592 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1593 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1594 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
1595 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1596 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1597 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
1598 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1599 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1600 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1601 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1602 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
1603 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
1604 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
1605 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
1606 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1607 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1608 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1609 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1610 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1611};
1612
1457static const struct tegra_pmc_soc tegra124_pmc_soc = {
1458 .num_powergates = ARRAY_SIZE(tegra124_powergates),
1459 .powergates = tegra124_powergates,
1460 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
1461 .cpu_powergates = tegra124_cpu_powergates,
1462 .has_tsense_reset = true,
1463 .has_gpu_clamps = true,
1613static const struct tegra_pmc_soc tegra124_pmc_soc = {
1614 .num_powergates = ARRAY_SIZE(tegra124_powergates),
1615 .powergates = tegra124_powergates,
1616 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
1617 .cpu_powergates = tegra124_cpu_powergates,
1618 .has_tsense_reset = true,
1619 .has_gpu_clamps = true,
1620 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
1621 .io_pads = tegra124_io_pads,
1464};
1465
1466static const char * const tegra210_powergates[] = {
1467 [TEGRA_POWERGATE_CPU] = "crail",
1468 [TEGRA_POWERGATE_3D] = "3d",
1469 [TEGRA_POWERGATE_VENC] = "venc",
1470 [TEGRA_POWERGATE_PCIE] = "pcie",
1471 [TEGRA_POWERGATE_MPE] = "mpe",

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1492
1493static const u8 tegra210_cpu_powergates[] = {
1494 TEGRA_POWERGATE_CPU0,
1495 TEGRA_POWERGATE_CPU1,
1496 TEGRA_POWERGATE_CPU2,
1497 TEGRA_POWERGATE_CPU3,
1498};
1499
1622};
1623
1624static const char * const tegra210_powergates[] = {
1625 [TEGRA_POWERGATE_CPU] = "crail",
1626 [TEGRA_POWERGATE_3D] = "3d",
1627 [TEGRA_POWERGATE_VENC] = "venc",
1628 [TEGRA_POWERGATE_PCIE] = "pcie",
1629 [TEGRA_POWERGATE_MPE] = "mpe",

--- 20 unchanged lines hidden (view full) ---

1650
1651static const u8 tegra210_cpu_powergates[] = {
1652 TEGRA_POWERGATE_CPU0,
1653 TEGRA_POWERGATE_CPU1,
1654 TEGRA_POWERGATE_CPU2,
1655 TEGRA_POWERGATE_CPU3,
1656};
1657
1658static const struct tegra_io_pad_soc tegra210_io_pads[] = {
1659 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
1660 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
1661 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
1662 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1663 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1664 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
1665 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
1666 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1667 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
1668 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
1669 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
1670 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
1671 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
1672 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1673 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1674 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1675 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1676 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
1677 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
1678 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
1679 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1680 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1681 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1682 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1683 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1684 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1685 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1686 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
1687 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
1688 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
1689 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
1690 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
1691 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
1692 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1693 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1694 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1695 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
1696 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1697};
1698
1500static const struct tegra_pmc_soc tegra210_pmc_soc = {
1501 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1502 .powergates = tegra210_powergates,
1503 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1504 .cpu_powergates = tegra210_cpu_powergates,
1505 .has_tsense_reset = true,
1506 .has_gpu_clamps = true,
1699static const struct tegra_pmc_soc tegra210_pmc_soc = {
1700 .num_powergates = ARRAY_SIZE(tegra210_powergates),
1701 .powergates = tegra210_powergates,
1702 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
1703 .cpu_powergates = tegra210_cpu_powergates,
1704 .has_tsense_reset = true,
1705 .has_gpu_clamps = true,
1706 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
1707 .io_pads = tegra210_io_pads,
1507};
1508
1509static const struct of_device_id tegra_pmc_match[] = {
1510 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1511 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1512 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1513 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1514 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },

--- 103 unchanged lines hidden --- 		1708};
1709
1710static const struct of_device_id tegra_pmc_match[] = {
1711 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1712 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
1713 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
1714 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
1715 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },

--- 103 unchanged lines hidden ---