1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #define pr_fmt(fmt) "tegra-pmc: " fmt 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/clk/tegra.h> 25 #include <linux/debugfs.h> 26 #include <linux/delay.h> 27 #include <linux/err.h> 28 #include <linux/export.h> 29 #include <linux/init.h> 30 #include <linux/io.h> 31 #include <linux/iopoll.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_platform.h> 35 #include <linux/platform_device.h> 36 #include <linux/pm_domain.h> 37 #include <linux/reboot.h> 38 #include <linux/reset.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 43 #include <soc/tegra/common.h> 44 #include <soc/tegra/fuse.h> 45 #include <soc/tegra/pmc.h> 46 47 #define PMC_CNTRL 0x0 48 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 49 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 50 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 51 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 52 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 53 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 54 #define PMC_CNTRL_MAIN_RST BIT(4) 55 56 #define DPD_SAMPLE 0x020 57 #define DPD_SAMPLE_ENABLE BIT(0) 58 #define DPD_SAMPLE_DISABLE (0 << 0) 59 60 #define PWRGATE_TOGGLE 0x30 61 #define PWRGATE_TOGGLE_START BIT(8) 62 63 #define REMOVE_CLAMPING 0x34 64 65 #define PWRGATE_STATUS 0x38 66 67 #define PMC_PWR_DET 0x48 68 69 #define PMC_SCRATCH0 0x50 70 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 71 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 72 #define PMC_SCRATCH0_MODE_RCM BIT(1) 73 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 74 PMC_SCRATCH0_MODE_BOOTLOADER | \ 75 PMC_SCRATCH0_MODE_RCM) 76 77 #define PMC_CPUPWRGOOD_TIMER 0xc8 78 #define PMC_CPUPWROFF_TIMER 0xcc 79 80 #define PMC_PWR_DET_VALUE 0xe4 81 82 #define PMC_SCRATCH41 0x140 83 84 #define PMC_SENSOR_CTRL 0x1b0 85 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 86 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 87 88 #define PMC_RST_STATUS 0x1b4 89 #define PMC_RST_STATUS_POR 0 90 #define PMC_RST_STATUS_WATCHDOG 1 91 #define PMC_RST_STATUS_SENSOR 2 92 #define PMC_RST_STATUS_SW_MAIN 3 93 #define PMC_RST_STATUS_LP0 4 94 #define PMC_RST_STATUS_AOTAG 5 95 96 #define IO_DPD_REQ 0x1b8 97 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 98 #define IO_DPD_REQ_CODE_OFF (1U << 30) 99 #define IO_DPD_REQ_CODE_ON (2U << 30) 100 #define IO_DPD_REQ_CODE_MASK (3U << 30) 101 102 #define IO_DPD_STATUS 0x1bc 103 #define IO_DPD2_REQ 0x1c0 104 #define IO_DPD2_STATUS 0x1c4 105 #define SEL_DPD_TIM 0x1c8 106 107 #define PMC_SCRATCH54 0x258 108 #define PMC_SCRATCH54_DATA_SHIFT 8 109 #define PMC_SCRATCH54_ADDR_SHIFT 0 110 111 #define PMC_SCRATCH55 0x25c 112 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 113 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 114 #define PMC_SCRATCH55_PINMUX_SHIFT 24 115 #define PMC_SCRATCH55_16BITOP BIT(15) 116 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 117 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 118 119 #define GPU_RG_CNTRL 0x2d4 120 121 struct tegra_powergate { 122 struct generic_pm_domain genpd; 123 struct tegra_pmc *pmc; 124 unsigned int id; 125 struct clk **clks; 126 unsigned int num_clks; 127 struct reset_control **resets; 128 unsigned int num_resets; 129 }; 130 131 struct tegra_io_pad_soc { 132 enum tegra_io_pad id; 133 unsigned int dpd; 134 unsigned int voltage; 135 }; 136 137 struct tegra_pmc_soc { 138 unsigned int num_powergates; 139 const char *const *powergates; 140 unsigned int num_cpu_powergates; 141 const u8 *cpu_powergates; 142 143 bool has_tsense_reset; 144 bool has_gpu_clamps; 145 146 const struct tegra_io_pad_soc *io_pads; 147 unsigned int num_io_pads; 148 }; 149 150 /** 151 * struct tegra_pmc - NVIDIA Tegra PMC 152 * @dev: pointer to PMC device structure 153 * @base: pointer to I/O remapped register region 154 * @clk: pointer to pclk clock 155 * @soc: pointer to SoC data structure 156 * @debugfs: pointer to debugfs entry 157 * @rate: currently configured rate of pclk 158 * @suspend_mode: lowest suspend mode available 159 * @cpu_good_time: CPU power good time (in microseconds) 160 * @cpu_off_time: CPU power off time (in microsecends) 161 * @core_osc_time: core power good OSC time (in microseconds) 162 * @core_pmu_time: core power good PMU time (in microseconds) 163 * @core_off_time: core power off time (in microseconds) 164 * @corereq_high: core power request is active-high 165 * @sysclkreq_high: system clock request is active-high 166 * @combined_req: combined power request for CPU & core 167 * @cpu_pwr_good_en: CPU power good signal is enabled 168 * @lp0_vec_phys: physical base address of the LP0 warm boot code 169 * @lp0_vec_size: size of the LP0 warm boot code 170 * @powergates_available: Bitmap of available power gates 171 * @powergates_lock: mutex for power gate register access 172 */ 173 struct tegra_pmc { 174 struct device *dev; 175 void __iomem *base; 176 struct clk *clk; 177 struct dentry *debugfs; 178 179 const struct tegra_pmc_soc *soc; 180 181 unsigned long rate; 182 183 enum tegra_suspend_mode suspend_mode; 184 u32 cpu_good_time; 185 u32 cpu_off_time; 186 u32 core_osc_time; 187 u32 core_pmu_time; 188 u32 core_off_time; 189 bool corereq_high; 190 bool sysclkreq_high; 191 bool combined_req; 192 bool cpu_pwr_good_en; 193 u32 lp0_vec_phys; 194 u32 lp0_vec_size; 195 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 196 197 struct mutex powergates_lock; 198 }; 199 200 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 201 .base = NULL, 202 .suspend_mode = TEGRA_SUSPEND_NONE, 203 }; 204 205 static inline struct tegra_powergate * 206 to_powergate(struct generic_pm_domain *domain) 207 { 208 return container_of(domain, struct tegra_powergate, genpd); 209 } 210 211 static u32 tegra_pmc_readl(unsigned long offset) 212 { 213 return readl(pmc->base + offset); 214 } 215 216 static void tegra_pmc_writel(u32 value, unsigned long offset) 217 { 218 writel(value, pmc->base + offset); 219 } 220 221 static inline bool tegra_powergate_state(int id) 222 { 223 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 224 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; 225 else 226 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 227 } 228 229 static inline bool tegra_powergate_is_valid(int id) 230 { 231 return (pmc->soc && pmc->soc->powergates[id]); 232 } 233 234 static inline bool tegra_powergate_is_available(int id) 235 { 236 return test_bit(id, pmc->powergates_available); 237 } 238 239 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 240 { 241 unsigned int i; 242 243 if (!pmc || !pmc->soc || !name) 244 return -EINVAL; 245 246 for (i = 0; i < pmc->soc->num_powergates; i++) { 247 if (!tegra_powergate_is_valid(i)) 248 continue; 249 250 if (!strcmp(name, pmc->soc->powergates[i])) 251 return i; 252 } 253 254 dev_err(pmc->dev, "powergate %s not found\n", name); 255 256 return -ENODEV; 257 } 258 259 /** 260 * tegra_powergate_set() - set the state of a partition 261 * @id: partition ID 262 * @new_state: new state of the partition 263 */ 264 static int tegra_powergate_set(unsigned int id, bool new_state) 265 { 266 bool status; 267 int err; 268 269 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 270 return -EINVAL; 271 272 mutex_lock(&pmc->powergates_lock); 273 274 if (tegra_powergate_state(id) == new_state) { 275 mutex_unlock(&pmc->powergates_lock); 276 return 0; 277 } 278 279 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 280 281 err = readx_poll_timeout(tegra_powergate_state, id, status, 282 status == new_state, 10, 100000); 283 284 mutex_unlock(&pmc->powergates_lock); 285 286 return err; 287 } 288 289 static int __tegra_powergate_remove_clamping(unsigned int id) 290 { 291 u32 mask; 292 293 mutex_lock(&pmc->powergates_lock); 294 295 /* 296 * On Tegra124 and later, the clamps for the GPU are controlled by a 297 * separate register (with different semantics). 298 */ 299 if (id == TEGRA_POWERGATE_3D) { 300 if (pmc->soc->has_gpu_clamps) { 301 tegra_pmc_writel(0, GPU_RG_CNTRL); 302 goto out; 303 } 304 } 305 306 /* 307 * Tegra 2 has a bug where PCIE and VDE clamping masks are 308 * swapped relatively to the partition ids 309 */ 310 if (id == TEGRA_POWERGATE_VDEC) 311 mask = (1 << TEGRA_POWERGATE_PCIE); 312 else if (id == TEGRA_POWERGATE_PCIE) 313 mask = (1 << TEGRA_POWERGATE_VDEC); 314 else 315 mask = (1 << id); 316 317 tegra_pmc_writel(mask, REMOVE_CLAMPING); 318 319 out: 320 mutex_unlock(&pmc->powergates_lock); 321 322 return 0; 323 } 324 325 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 326 { 327 unsigned int i; 328 329 for (i = 0; i < pg->num_clks; i++) 330 clk_disable_unprepare(pg->clks[i]); 331 } 332 333 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 334 { 335 unsigned int i; 336 int err; 337 338 for (i = 0; i < pg->num_clks; i++) { 339 err = clk_prepare_enable(pg->clks[i]); 340 if (err) 341 goto out; 342 } 343 344 return 0; 345 346 out: 347 while (i--) 348 clk_disable_unprepare(pg->clks[i]); 349 350 return err; 351 } 352 353 static int tegra_powergate_reset_assert(struct tegra_powergate *pg) 354 { 355 unsigned int i; 356 int err; 357 358 for (i = 0; i < pg->num_resets; i++) { 359 err = reset_control_assert(pg->resets[i]); 360 if (err) 361 return err; 362 } 363 364 return 0; 365 } 366 367 static int tegra_powergate_reset_deassert(struct tegra_powergate *pg) 368 { 369 unsigned int i; 370 int err; 371 372 for (i = 0; i < pg->num_resets; i++) { 373 err = reset_control_deassert(pg->resets[i]); 374 if (err) 375 return err; 376 } 377 378 return 0; 379 } 380 381 static int tegra_powergate_power_up(struct tegra_powergate *pg, 382 bool disable_clocks) 383 { 384 int err; 385 386 err = tegra_powergate_reset_assert(pg); 387 if (err) 388 return err; 389 390 usleep_range(10, 20); 391 392 err = tegra_powergate_set(pg->id, true); 393 if (err < 0) 394 return err; 395 396 usleep_range(10, 20); 397 398 err = tegra_powergate_enable_clocks(pg); 399 if (err) 400 goto disable_clks; 401 402 usleep_range(10, 20); 403 404 err = __tegra_powergate_remove_clamping(pg->id); 405 if (err) 406 goto disable_clks; 407 408 usleep_range(10, 20); 409 410 err = tegra_powergate_reset_deassert(pg); 411 if (err) 412 goto powergate_off; 413 414 usleep_range(10, 20); 415 416 if (disable_clocks) 417 tegra_powergate_disable_clocks(pg); 418 419 return 0; 420 421 disable_clks: 422 tegra_powergate_disable_clocks(pg); 423 usleep_range(10, 20); 424 425 powergate_off: 426 tegra_powergate_set(pg->id, false); 427 428 return err; 429 } 430 431 static int tegra_powergate_power_down(struct tegra_powergate *pg) 432 { 433 int err; 434 435 err = tegra_powergate_enable_clocks(pg); 436 if (err) 437 return err; 438 439 usleep_range(10, 20); 440 441 err = tegra_powergate_reset_assert(pg); 442 if (err) 443 goto disable_clks; 444 445 usleep_range(10, 20); 446 447 tegra_powergate_disable_clocks(pg); 448 449 usleep_range(10, 20); 450 451 err = tegra_powergate_set(pg->id, false); 452 if (err) 453 goto assert_resets; 454 455 return 0; 456 457 assert_resets: 458 tegra_powergate_enable_clocks(pg); 459 usleep_range(10, 20); 460 tegra_powergate_reset_deassert(pg); 461 usleep_range(10, 20); 462 463 disable_clks: 464 tegra_powergate_disable_clocks(pg); 465 466 return err; 467 } 468 469 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 470 { 471 struct tegra_powergate *pg = to_powergate(domain); 472 struct tegra_pmc *pmc = pg->pmc; 473 int err; 474 475 err = tegra_powergate_power_up(pg, true); 476 if (err) 477 dev_err(pmc->dev, "failed to turn on PM domain %s: %d\n", 478 pg->genpd.name, err); 479 480 return err; 481 } 482 483 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 484 { 485 struct tegra_powergate *pg = to_powergate(domain); 486 struct tegra_pmc *pmc = pg->pmc; 487 int err; 488 489 err = tegra_powergate_power_down(pg); 490 if (err) 491 dev_err(pmc->dev, "failed to turn off PM domain %s: %d\n", 492 pg->genpd.name, err); 493 494 return err; 495 } 496 497 /** 498 * tegra_powergate_power_on() - power on partition 499 * @id: partition ID 500 */ 501 int tegra_powergate_power_on(unsigned int id) 502 { 503 if (!tegra_powergate_is_available(id)) 504 return -EINVAL; 505 506 return tegra_powergate_set(id, true); 507 } 508 509 /** 510 * tegra_powergate_power_off() - power off partition 511 * @id: partition ID 512 */ 513 int tegra_powergate_power_off(unsigned int id) 514 { 515 if (!tegra_powergate_is_available(id)) 516 return -EINVAL; 517 518 return tegra_powergate_set(id, false); 519 } 520 EXPORT_SYMBOL(tegra_powergate_power_off); 521 522 /** 523 * tegra_powergate_is_powered() - check if partition is powered 524 * @id: partition ID 525 */ 526 int tegra_powergate_is_powered(unsigned int id) 527 { 528 int status; 529 530 if (!tegra_powergate_is_valid(id)) 531 return -EINVAL; 532 533 mutex_lock(&pmc->powergates_lock); 534 status = tegra_powergate_state(id); 535 mutex_unlock(&pmc->powergates_lock); 536 537 return status; 538 } 539 540 /** 541 * tegra_powergate_remove_clamping() - remove power clamps for partition 542 * @id: partition ID 543 */ 544 int tegra_powergate_remove_clamping(unsigned int id) 545 { 546 if (!tegra_powergate_is_available(id)) 547 return -EINVAL; 548 549 return __tegra_powergate_remove_clamping(id); 550 } 551 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 552 553 /** 554 * tegra_powergate_sequence_power_up() - power up partition 555 * @id: partition ID 556 * @clk: clock for partition 557 * @rst: reset for partition 558 * 559 * Must be called with clk disabled, and returns with clk enabled. 560 */ 561 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 562 struct reset_control *rst) 563 { 564 struct tegra_powergate pg; 565 int err; 566 567 if (!tegra_powergate_is_available(id)) 568 return -EINVAL; 569 570 pg.id = id; 571 pg.clks = &clk; 572 pg.num_clks = 1; 573 pg.resets = &rst; 574 pg.num_resets = 1; 575 576 err = tegra_powergate_power_up(&pg, false); 577 if (err) 578 pr_err("failed to turn on partition %d: %d\n", id, err); 579 580 return err; 581 } 582 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 583 584 #ifdef CONFIG_SMP 585 /** 586 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 587 * @cpuid: CPU partition ID 588 * 589 * Returns the partition ID corresponding to the CPU partition ID or a 590 * negative error code on failure. 591 */ 592 static int tegra_get_cpu_powergate_id(unsigned int cpuid) 593 { 594 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 595 return pmc->soc->cpu_powergates[cpuid]; 596 597 return -EINVAL; 598 } 599 600 /** 601 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 602 * @cpuid: CPU partition ID 603 */ 604 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 605 { 606 int id; 607 608 id = tegra_get_cpu_powergate_id(cpuid); 609 if (id < 0) 610 return false; 611 612 return tegra_powergate_is_powered(id); 613 } 614 615 /** 616 * tegra_pmc_cpu_power_on() - power on CPU partition 617 * @cpuid: CPU partition ID 618 */ 619 int tegra_pmc_cpu_power_on(unsigned int cpuid) 620 { 621 int id; 622 623 id = tegra_get_cpu_powergate_id(cpuid); 624 if (id < 0) 625 return id; 626 627 return tegra_powergate_set(id, true); 628 } 629 630 /** 631 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 632 * @cpuid: CPU partition ID 633 */ 634 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 635 { 636 int id; 637 638 id = tegra_get_cpu_powergate_id(cpuid); 639 if (id < 0) 640 return id; 641 642 return tegra_powergate_remove_clamping(id); 643 } 644 #endif /* CONFIG_SMP */ 645 646 static int tegra_pmc_restart_notify(struct notifier_block *this, 647 unsigned long action, void *data) 648 { 649 const char *cmd = data; 650 u32 value; 651 652 value = tegra_pmc_readl(PMC_SCRATCH0); 653 value &= ~PMC_SCRATCH0_MODE_MASK; 654 655 if (cmd) { 656 if (strcmp(cmd, "recovery") == 0) 657 value |= PMC_SCRATCH0_MODE_RECOVERY; 658 659 if (strcmp(cmd, "bootloader") == 0) 660 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 661 662 if (strcmp(cmd, "forced-recovery") == 0) 663 value |= PMC_SCRATCH0_MODE_RCM; 664 } 665 666 tegra_pmc_writel(value, PMC_SCRATCH0); 667 668 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 669 value = tegra_pmc_readl(PMC_CNTRL); 670 value |= PMC_CNTRL_MAIN_RST; 671 tegra_pmc_writel(value, PMC_CNTRL); 672 673 return NOTIFY_DONE; 674 } 675 676 static struct notifier_block tegra_pmc_restart_handler = { 677 .notifier_call = tegra_pmc_restart_notify, 678 .priority = 128, 679 }; 680 681 static int powergate_show(struct seq_file *s, void *data) 682 { 683 unsigned int i; 684 int status; 685 686 seq_printf(s, " powergate powered\n"); 687 seq_printf(s, "------------------\n"); 688 689 for (i = 0; i < pmc->soc->num_powergates; i++) { 690 status = tegra_powergate_is_powered(i); 691 if (status < 0) 692 continue; 693 694 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 695 status ? "yes" : "no"); 696 } 697 698 return 0; 699 } 700 701 static int powergate_open(struct inode *inode, struct file *file) 702 { 703 return single_open(file, powergate_show, inode->i_private); 704 } 705 706 static const struct file_operations powergate_fops = { 707 .open = powergate_open, 708 .read = seq_read, 709 .llseek = seq_lseek, 710 .release = single_release, 711 }; 712 713 static int tegra_powergate_debugfs_init(void) 714 { 715 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 716 &powergate_fops); 717 if (!pmc->debugfs) 718 return -ENOMEM; 719 720 return 0; 721 } 722 723 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 724 struct device_node *np) 725 { 726 struct clk *clk; 727 unsigned int i, count; 728 int err; 729 730 count = of_count_phandle_with_args(np, "clocks", "#clock-cells"); 731 if (count == 0) 732 return -ENODEV; 733 734 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 735 if (!pg->clks) 736 return -ENOMEM; 737 738 for (i = 0; i < count; i++) { 739 pg->clks[i] = of_clk_get(np, i); 740 if (IS_ERR(pg->clks[i])) { 741 err = PTR_ERR(pg->clks[i]); 742 goto err; 743 } 744 } 745 746 pg->num_clks = count; 747 748 return 0; 749 750 err: 751 while (i--) 752 clk_put(pg->clks[i]); 753 754 kfree(pg->clks); 755 756 return err; 757 } 758 759 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 760 struct device_node *np, bool off) 761 { 762 struct reset_control *rst; 763 unsigned int i, count; 764 int err; 765 766 count = of_count_phandle_with_args(np, "resets", "#reset-cells"); 767 if (count == 0) 768 return -ENODEV; 769 770 pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL); 771 if (!pg->resets) 772 return -ENOMEM; 773 774 for (i = 0; i < count; i++) { 775 pg->resets[i] = of_reset_control_get_by_index(np, i); 776 if (IS_ERR(pg->resets[i])) { 777 err = PTR_ERR(pg->resets[i]); 778 goto error; 779 } 780 781 if (off) 782 err = reset_control_assert(pg->resets[i]); 783 else 784 err = reset_control_deassert(pg->resets[i]); 785 786 if (err) { 787 reset_control_put(pg->resets[i]); 788 goto error; 789 } 790 } 791 792 pg->num_resets = count; 793 794 return 0; 795 796 error: 797 while (i--) 798 reset_control_put(pg->resets[i]); 799 800 kfree(pg->resets); 801 802 return err; 803 } 804 805 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 806 { 807 struct tegra_powergate *pg; 808 int id, err; 809 bool off; 810 811 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 812 if (!pg) 813 return; 814 815 id = tegra_powergate_lookup(pmc, np->name); 816 if (id < 0) { 817 dev_err(pmc->dev, "powergate lookup failed for %s: %d\n", 818 np->name, id); 819 goto free_mem; 820 } 821 822 /* 823 * Clear the bit for this powergate so it cannot be managed 824 * directly via the legacy APIs for controlling powergates. 825 */ 826 clear_bit(id, pmc->powergates_available); 827 828 pg->id = id; 829 pg->genpd.name = np->name; 830 pg->genpd.power_off = tegra_genpd_power_off; 831 pg->genpd.power_on = tegra_genpd_power_on; 832 pg->pmc = pmc; 833 834 off = !tegra_powergate_is_powered(pg->id); 835 836 err = tegra_powergate_of_get_clks(pg, np); 837 if (err < 0) { 838 dev_err(pmc->dev, "failed to get clocks for %s: %d\n", 839 np->name, err); 840 goto set_available; 841 } 842 843 err = tegra_powergate_of_get_resets(pg, np, off); 844 if (err < 0) { 845 dev_err(pmc->dev, "failed to get resets for %s: %d\n", 846 np->name, err); 847 goto remove_clks; 848 } 849 850 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) 851 goto power_on_cleanup; 852 853 /* 854 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB 855 * host and super-speed partitions. Once the XHCI driver 856 * manages the partitions itself this code can be removed. Note 857 * that we don't register these partitions with the genpd core 858 * to avoid it from powering down the partitions as they appear 859 * to be unused. 860 */ 861 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) && 862 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) 863 goto power_on_cleanup; 864 865 pm_genpd_init(&pg->genpd, NULL, off); 866 867 err = of_genpd_add_provider_simple(np, &pg->genpd); 868 if (err < 0) { 869 dev_err(pmc->dev, "failed to add genpd provider for %s: %d\n", 870 np->name, err); 871 goto remove_resets; 872 } 873 874 dev_dbg(pmc->dev, "added power domain %s\n", pg->genpd.name); 875 876 return; 877 878 power_on_cleanup: 879 if (off) 880 WARN_ON(tegra_powergate_power_up(pg, true)); 881 882 remove_resets: 883 while (pg->num_resets--) 884 reset_control_put(pg->resets[pg->num_resets]); 885 886 kfree(pg->resets); 887 888 remove_clks: 889 while (pg->num_clks--) 890 clk_put(pg->clks[pg->num_clks]); 891 892 kfree(pg->clks); 893 894 set_available: 895 set_bit(id, pmc->powergates_available); 896 897 free_mem: 898 kfree(pg); 899 } 900 901 static void tegra_powergate_init(struct tegra_pmc *pmc, 902 struct device_node *parent) 903 { 904 struct device_node *np, *child; 905 unsigned int i; 906 907 /* Create a bitmap of the available and valid partitions */ 908 for (i = 0; i < pmc->soc->num_powergates; i++) 909 if (pmc->soc->powergates[i]) 910 set_bit(i, pmc->powergates_available); 911 912 np = of_get_child_by_name(parent, "powergates"); 913 if (!np) 914 return; 915 916 for_each_child_of_node(np, child) { 917 tegra_powergate_add(pmc, child); 918 of_node_put(child); 919 } 920 921 of_node_put(np); 922 } 923 924 static const struct tegra_io_pad_soc * 925 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 926 { 927 unsigned int i; 928 929 for (i = 0; i < pmc->soc->num_io_pads; i++) 930 if (pmc->soc->io_pads[i].id == id) 931 return &pmc->soc->io_pads[i]; 932 933 return NULL; 934 } 935 936 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, 937 unsigned long *status, unsigned int *bit) 938 { 939 const struct tegra_io_pad_soc *pad; 940 unsigned long rate, value; 941 942 pad = tegra_io_pad_find(pmc, id); 943 if (!pad) 944 return -ENOENT; 945 946 if (pad->dpd == UINT_MAX) 947 return -ENOTSUPP; 948 949 *bit = pad->dpd % 32; 950 951 if (pad->dpd < 32) { 952 *status = IO_DPD_STATUS; 953 *request = IO_DPD_REQ; 954 } else { 955 *status = IO_DPD2_STATUS; 956 *request = IO_DPD2_REQ; 957 } 958 959 rate = clk_get_rate(pmc->clk); 960 961 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 962 963 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 964 value = DIV_ROUND_UP(1000000000, rate); 965 value = DIV_ROUND_UP(200, value); 966 tegra_pmc_writel(value, SEL_DPD_TIM); 967 968 return 0; 969 } 970 971 static int tegra_io_pad_poll(unsigned long offset, u32 mask, 972 u32 val, unsigned long timeout) 973 { 974 u32 value; 975 976 timeout = jiffies + msecs_to_jiffies(timeout); 977 978 while (time_after(timeout, jiffies)) { 979 value = tegra_pmc_readl(offset); 980 if ((value & mask) == val) 981 return 0; 982 983 usleep_range(250, 1000); 984 } 985 986 return -ETIMEDOUT; 987 } 988 989 static void tegra_io_pad_unprepare(void) 990 { 991 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 992 } 993 994 /** 995 * tegra_io_pad_power_enable() - enable power to I/O pad 996 * @id: Tegra I/O pad ID for which to enable power 997 * 998 * Returns: 0 on success or a negative error code on failure. 999 */ 1000 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1001 { 1002 unsigned long request, status; 1003 unsigned int bit; 1004 int err; 1005 1006 mutex_lock(&pmc->powergates_lock); 1007 1008 err = tegra_io_pad_prepare(id, &request, &status, &bit); 1009 if (err < 0) { 1010 dev_err(pmc->dev, "tegra_io_pad_prepare() failed: %d\n", err); 1011 goto unlock; 1012 } 1013 1014 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | BIT(bit), request); 1015 1016 err = tegra_io_pad_poll(status, BIT(bit), 0, 250); 1017 if (err < 0) { 1018 dev_err(pmc->dev, "tegra_io_pad_poll() failed: %d\n", err); 1019 goto unlock; 1020 } 1021 1022 tegra_io_pad_unprepare(); 1023 1024 unlock: 1025 mutex_unlock(&pmc->powergates_lock); 1026 return err; 1027 } 1028 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1029 1030 /** 1031 * tegra_io_pad_power_disable() - disable power to I/O pad 1032 * @id: Tegra I/O pad ID for which to disable power 1033 * 1034 * Returns: 0 on success or a negative error code on failure. 1035 */ 1036 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1037 { 1038 unsigned long request, status; 1039 unsigned int bit; 1040 int err; 1041 1042 mutex_lock(&pmc->powergates_lock); 1043 1044 err = tegra_io_pad_prepare(id, &request, &status, &bit); 1045 if (err < 0) { 1046 dev_err(pmc->dev, "tegra_io_pad_prepare() failed: %d\n", err); 1047 goto unlock; 1048 } 1049 1050 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | BIT(bit), request); 1051 1052 err = tegra_io_pad_poll(status, BIT(bit), BIT(bit), 250); 1053 if (err < 0) { 1054 dev_err(pmc->dev, "tegra_io_pad_poll() failed: %d\n", err); 1055 goto unlock; 1056 } 1057 1058 tegra_io_pad_unprepare(); 1059 1060 unlock: 1061 mutex_unlock(&pmc->powergates_lock); 1062 return err; 1063 } 1064 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1065 1066 int tegra_io_pad_set_voltage(enum tegra_io_pad id, 1067 enum tegra_io_pad_voltage voltage) 1068 { 1069 const struct tegra_io_pad_soc *pad; 1070 u32 value; 1071 1072 pad = tegra_io_pad_find(pmc, id); 1073 if (!pad) 1074 return -ENOENT; 1075 1076 if (pad->voltage == UINT_MAX) 1077 return -ENOTSUPP; 1078 1079 mutex_lock(&pmc->powergates_lock); 1080 1081 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1082 value = tegra_pmc_readl(PMC_PWR_DET); 1083 value |= BIT(pad->voltage); 1084 tegra_pmc_writel(value, PMC_PWR_DET); 1085 1086 /* update I/O voltage */ 1087 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1088 1089 if (voltage == TEGRA_IO_PAD_1800000UV) 1090 value &= ~BIT(pad->voltage); 1091 else 1092 value |= BIT(pad->voltage); 1093 1094 tegra_pmc_writel(value, PMC_PWR_DET_VALUE); 1095 1096 mutex_unlock(&pmc->powergates_lock); 1097 1098 usleep_range(100, 250); 1099 1100 return 0; 1101 } 1102 EXPORT_SYMBOL(tegra_io_pad_set_voltage); 1103 1104 int tegra_io_pad_get_voltage(enum tegra_io_pad id) 1105 { 1106 const struct tegra_io_pad_soc *pad; 1107 u32 value; 1108 1109 pad = tegra_io_pad_find(pmc, id); 1110 if (!pad) 1111 return -ENOENT; 1112 1113 if (pad->voltage == UINT_MAX) 1114 return -ENOTSUPP; 1115 1116 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1117 1118 if ((value & BIT(pad->voltage)) == 0) 1119 return TEGRA_IO_PAD_1800000UV; 1120 1121 return TEGRA_IO_PAD_3300000UV; 1122 } 1123 EXPORT_SYMBOL(tegra_io_pad_get_voltage); 1124 1125 /** 1126 * tegra_io_rail_power_on() - enable power to I/O rail 1127 * @id: Tegra I/O pad ID for which to enable power 1128 * 1129 * See also: tegra_io_pad_power_enable() 1130 */ 1131 int tegra_io_rail_power_on(unsigned int id) 1132 { 1133 return tegra_io_pad_power_enable(id); 1134 } 1135 EXPORT_SYMBOL(tegra_io_rail_power_on); 1136 1137 /** 1138 * tegra_io_rail_power_off() - disable power to I/O rail 1139 * @id: Tegra I/O pad ID for which to disable power 1140 * 1141 * See also: tegra_io_pad_power_disable() 1142 */ 1143 int tegra_io_rail_power_off(unsigned int id) 1144 { 1145 return tegra_io_pad_power_disable(id); 1146 } 1147 EXPORT_SYMBOL(tegra_io_rail_power_off); 1148 1149 #ifdef CONFIG_PM_SLEEP 1150 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1151 { 1152 return pmc->suspend_mode; 1153 } 1154 1155 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1156 { 1157 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1158 return; 1159 1160 pmc->suspend_mode = mode; 1161 } 1162 1163 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1164 { 1165 unsigned long long rate = 0; 1166 u32 value; 1167 1168 switch (mode) { 1169 case TEGRA_SUSPEND_LP1: 1170 rate = 32768; 1171 break; 1172 1173 case TEGRA_SUSPEND_LP2: 1174 rate = clk_get_rate(pmc->clk); 1175 break; 1176 1177 default: 1178 break; 1179 } 1180 1181 if (WARN_ON_ONCE(rate == 0)) 1182 rate = 100000000; 1183 1184 if (rate != pmc->rate) { 1185 u64 ticks; 1186 1187 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1188 do_div(ticks, USEC_PER_SEC); 1189 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 1190 1191 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1192 do_div(ticks, USEC_PER_SEC); 1193 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 1194 1195 wmb(); 1196 1197 pmc->rate = rate; 1198 } 1199 1200 value = tegra_pmc_readl(PMC_CNTRL); 1201 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1202 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1203 tegra_pmc_writel(value, PMC_CNTRL); 1204 } 1205 #endif 1206 1207 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1208 { 1209 u32 value, values[2]; 1210 1211 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1212 } else { 1213 switch (value) { 1214 case 0: 1215 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1216 break; 1217 1218 case 1: 1219 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1220 break; 1221 1222 case 2: 1223 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1224 break; 1225 1226 default: 1227 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1228 break; 1229 } 1230 } 1231 1232 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1233 1234 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1235 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1236 1237 pmc->cpu_good_time = value; 1238 1239 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1240 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1241 1242 pmc->cpu_off_time = value; 1243 1244 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1245 values, ARRAY_SIZE(values))) 1246 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1247 1248 pmc->core_osc_time = values[0]; 1249 pmc->core_pmu_time = values[1]; 1250 1251 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1252 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1253 1254 pmc->core_off_time = value; 1255 1256 pmc->corereq_high = of_property_read_bool(np, 1257 "nvidia,core-power-req-active-high"); 1258 1259 pmc->sysclkreq_high = of_property_read_bool(np, 1260 "nvidia,sys-clock-req-active-high"); 1261 1262 pmc->combined_req = of_property_read_bool(np, 1263 "nvidia,combined-power-req"); 1264 1265 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1266 "nvidia,cpu-pwr-good-en"); 1267 1268 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1269 ARRAY_SIZE(values))) 1270 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1271 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1272 1273 pmc->lp0_vec_phys = values[0]; 1274 pmc->lp0_vec_size = values[1]; 1275 1276 return 0; 1277 } 1278 1279 static void tegra_pmc_init(struct tegra_pmc *pmc) 1280 { 1281 u32 value; 1282 1283 /* Always enable CPU power request */ 1284 value = tegra_pmc_readl(PMC_CNTRL); 1285 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1286 tegra_pmc_writel(value, PMC_CNTRL); 1287 1288 value = tegra_pmc_readl(PMC_CNTRL); 1289 1290 if (pmc->sysclkreq_high) 1291 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 1292 else 1293 value |= PMC_CNTRL_SYSCLK_POLARITY; 1294 1295 /* configure the output polarity while the request is tristated */ 1296 tegra_pmc_writel(value, PMC_CNTRL); 1297 1298 /* now enable the request */ 1299 value = tegra_pmc_readl(PMC_CNTRL); 1300 value |= PMC_CNTRL_SYSCLK_OE; 1301 tegra_pmc_writel(value, PMC_CNTRL); 1302 } 1303 1304 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1305 { 1306 static const char disabled[] = "emergency thermal reset disabled"; 1307 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1308 struct device *dev = pmc->dev; 1309 struct device_node *np; 1310 u32 value, checksum; 1311 1312 if (!pmc->soc->has_tsense_reset) 1313 return; 1314 1315 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1316 if (!np) { 1317 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1318 return; 1319 } 1320 1321 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1322 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1323 goto out; 1324 } 1325 1326 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1327 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1328 goto out; 1329 } 1330 1331 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1332 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1333 goto out; 1334 } 1335 1336 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1337 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1338 goto out; 1339 } 1340 1341 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1342 pinmux = 0; 1343 1344 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1345 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1346 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1347 1348 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1349 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1350 tegra_pmc_writel(value, PMC_SCRATCH54); 1351 1352 value = PMC_SCRATCH55_RESET_TEGRA; 1353 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1354 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1355 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1356 1357 /* 1358 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1359 * contain the checksum and are currently zero, so they are not added. 1360 */ 1361 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1362 + ((value >> 24) & 0xff); 1363 checksum &= 0xff; 1364 checksum = 0x100 - checksum; 1365 1366 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1367 1368 tegra_pmc_writel(value, PMC_SCRATCH55); 1369 1370 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1371 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1372 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1373 1374 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1375 1376 out: 1377 of_node_put(np); 1378 } 1379 1380 static int tegra_pmc_probe(struct platform_device *pdev) 1381 { 1382 void __iomem *base; 1383 struct resource *res; 1384 int err; 1385 1386 /* 1387 * Early initialisation should have configured an initial 1388 * register mapping and setup the soc data pointer. If these 1389 * are not valid then something went badly wrong! 1390 */ 1391 if (WARN_ON(!pmc->base || !pmc->soc)) 1392 return -ENODEV; 1393 1394 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1395 if (err < 0) 1396 return err; 1397 1398 /* take over the memory region from the early initialization */ 1399 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1400 base = devm_ioremap_resource(&pdev->dev, res); 1401 if (IS_ERR(base)) 1402 return PTR_ERR(base); 1403 1404 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1405 if (IS_ERR(pmc->clk)) { 1406 err = PTR_ERR(pmc->clk); 1407 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1408 return err; 1409 } 1410 1411 pmc->dev = &pdev->dev; 1412 1413 tegra_pmc_init(pmc); 1414 1415 tegra_pmc_init_tsense_reset(pmc); 1416 1417 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1418 err = tegra_powergate_debugfs_init(); 1419 if (err < 0) 1420 return err; 1421 } 1422 1423 err = register_restart_handler(&tegra_pmc_restart_handler); 1424 if (err) { 1425 debugfs_remove(pmc->debugfs); 1426 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 1427 err); 1428 return err; 1429 } 1430 1431 mutex_lock(&pmc->powergates_lock); 1432 iounmap(pmc->base); 1433 pmc->base = base; 1434 mutex_unlock(&pmc->powergates_lock); 1435 1436 return 0; 1437 } 1438 1439 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1440 static int tegra_pmc_suspend(struct device *dev) 1441 { 1442 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 1443 1444 return 0; 1445 } 1446 1447 static int tegra_pmc_resume(struct device *dev) 1448 { 1449 tegra_pmc_writel(0x0, PMC_SCRATCH41); 1450 1451 return 0; 1452 } 1453 1454 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 1455 1456 #endif 1457 1458 static const char * const tegra20_powergates[] = { 1459 [TEGRA_POWERGATE_CPU] = "cpu", 1460 [TEGRA_POWERGATE_3D] = "3d", 1461 [TEGRA_POWERGATE_VENC] = "venc", 1462 [TEGRA_POWERGATE_VDEC] = "vdec", 1463 [TEGRA_POWERGATE_PCIE] = "pcie", 1464 [TEGRA_POWERGATE_L2] = "l2", 1465 [TEGRA_POWERGATE_MPE] = "mpe", 1466 }; 1467 1468 static const struct tegra_pmc_soc tegra20_pmc_soc = { 1469 .num_powergates = ARRAY_SIZE(tegra20_powergates), 1470 .powergates = tegra20_powergates, 1471 .num_cpu_powergates = 0, 1472 .cpu_powergates = NULL, 1473 .has_tsense_reset = false, 1474 .has_gpu_clamps = false, 1475 }; 1476 1477 static const char * const tegra30_powergates[] = { 1478 [TEGRA_POWERGATE_CPU] = "cpu0", 1479 [TEGRA_POWERGATE_3D] = "3d0", 1480 [TEGRA_POWERGATE_VENC] = "venc", 1481 [TEGRA_POWERGATE_VDEC] = "vdec", 1482 [TEGRA_POWERGATE_PCIE] = "pcie", 1483 [TEGRA_POWERGATE_L2] = "l2", 1484 [TEGRA_POWERGATE_MPE] = "mpe", 1485 [TEGRA_POWERGATE_HEG] = "heg", 1486 [TEGRA_POWERGATE_SATA] = "sata", 1487 [TEGRA_POWERGATE_CPU1] = "cpu1", 1488 [TEGRA_POWERGATE_CPU2] = "cpu2", 1489 [TEGRA_POWERGATE_CPU3] = "cpu3", 1490 [TEGRA_POWERGATE_CELP] = "celp", 1491 [TEGRA_POWERGATE_3D1] = "3d1", 1492 }; 1493 1494 static const u8 tegra30_cpu_powergates[] = { 1495 TEGRA_POWERGATE_CPU, 1496 TEGRA_POWERGATE_CPU1, 1497 TEGRA_POWERGATE_CPU2, 1498 TEGRA_POWERGATE_CPU3, 1499 }; 1500 1501 static const struct tegra_pmc_soc tegra30_pmc_soc = { 1502 .num_powergates = ARRAY_SIZE(tegra30_powergates), 1503 .powergates = tegra30_powergates, 1504 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 1505 .cpu_powergates = tegra30_cpu_powergates, 1506 .has_tsense_reset = true, 1507 .has_gpu_clamps = false, 1508 }; 1509 1510 static const char * const tegra114_powergates[] = { 1511 [TEGRA_POWERGATE_CPU] = "crail", 1512 [TEGRA_POWERGATE_3D] = "3d", 1513 [TEGRA_POWERGATE_VENC] = "venc", 1514 [TEGRA_POWERGATE_VDEC] = "vdec", 1515 [TEGRA_POWERGATE_MPE] = "mpe", 1516 [TEGRA_POWERGATE_HEG] = "heg", 1517 [TEGRA_POWERGATE_CPU1] = "cpu1", 1518 [TEGRA_POWERGATE_CPU2] = "cpu2", 1519 [TEGRA_POWERGATE_CPU3] = "cpu3", 1520 [TEGRA_POWERGATE_CELP] = "celp", 1521 [TEGRA_POWERGATE_CPU0] = "cpu0", 1522 [TEGRA_POWERGATE_C0NC] = "c0nc", 1523 [TEGRA_POWERGATE_C1NC] = "c1nc", 1524 [TEGRA_POWERGATE_DIS] = "dis", 1525 [TEGRA_POWERGATE_DISB] = "disb", 1526 [TEGRA_POWERGATE_XUSBA] = "xusba", 1527 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1528 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1529 }; 1530 1531 static const u8 tegra114_cpu_powergates[] = { 1532 TEGRA_POWERGATE_CPU0, 1533 TEGRA_POWERGATE_CPU1, 1534 TEGRA_POWERGATE_CPU2, 1535 TEGRA_POWERGATE_CPU3, 1536 }; 1537 1538 static const struct tegra_pmc_soc tegra114_pmc_soc = { 1539 .num_powergates = ARRAY_SIZE(tegra114_powergates), 1540 .powergates = tegra114_powergates, 1541 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 1542 .cpu_powergates = tegra114_cpu_powergates, 1543 .has_tsense_reset = true, 1544 .has_gpu_clamps = false, 1545 }; 1546 1547 static const char * const tegra124_powergates[] = { 1548 [TEGRA_POWERGATE_CPU] = "crail", 1549 [TEGRA_POWERGATE_3D] = "3d", 1550 [TEGRA_POWERGATE_VENC] = "venc", 1551 [TEGRA_POWERGATE_PCIE] = "pcie", 1552 [TEGRA_POWERGATE_VDEC] = "vdec", 1553 [TEGRA_POWERGATE_MPE] = "mpe", 1554 [TEGRA_POWERGATE_HEG] = "heg", 1555 [TEGRA_POWERGATE_SATA] = "sata", 1556 [TEGRA_POWERGATE_CPU1] = "cpu1", 1557 [TEGRA_POWERGATE_CPU2] = "cpu2", 1558 [TEGRA_POWERGATE_CPU3] = "cpu3", 1559 [TEGRA_POWERGATE_CELP] = "celp", 1560 [TEGRA_POWERGATE_CPU0] = "cpu0", 1561 [TEGRA_POWERGATE_C0NC] = "c0nc", 1562 [TEGRA_POWERGATE_C1NC] = "c1nc", 1563 [TEGRA_POWERGATE_SOR] = "sor", 1564 [TEGRA_POWERGATE_DIS] = "dis", 1565 [TEGRA_POWERGATE_DISB] = "disb", 1566 [TEGRA_POWERGATE_XUSBA] = "xusba", 1567 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1568 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1569 [TEGRA_POWERGATE_VIC] = "vic", 1570 [TEGRA_POWERGATE_IRAM] = "iram", 1571 }; 1572 1573 static const u8 tegra124_cpu_powergates[] = { 1574 TEGRA_POWERGATE_CPU0, 1575 TEGRA_POWERGATE_CPU1, 1576 TEGRA_POWERGATE_CPU2, 1577 TEGRA_POWERGATE_CPU3, 1578 }; 1579 1580 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 1581 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 1582 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX }, 1583 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX }, 1584 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX }, 1585 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1586 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1587 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, 1588 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1589 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, 1590 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, 1591 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, 1592 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, 1593 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1594 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX }, 1595 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, 1596 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1597 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX }, 1598 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1599 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, 1600 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1601 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 1602 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX }, 1603 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX }, 1604 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX }, 1605 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX }, 1606 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 1607 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1608 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1609 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1610 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1611 }; 1612 1613 static const struct tegra_pmc_soc tegra124_pmc_soc = { 1614 .num_powergates = ARRAY_SIZE(tegra124_powergates), 1615 .powergates = tegra124_powergates, 1616 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 1617 .cpu_powergates = tegra124_cpu_powergates, 1618 .has_tsense_reset = true, 1619 .has_gpu_clamps = true, 1620 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 1621 .io_pads = tegra124_io_pads, 1622 }; 1623 1624 static const char * const tegra210_powergates[] = { 1625 [TEGRA_POWERGATE_CPU] = "crail", 1626 [TEGRA_POWERGATE_3D] = "3d", 1627 [TEGRA_POWERGATE_VENC] = "venc", 1628 [TEGRA_POWERGATE_PCIE] = "pcie", 1629 [TEGRA_POWERGATE_MPE] = "mpe", 1630 [TEGRA_POWERGATE_SATA] = "sata", 1631 [TEGRA_POWERGATE_CPU1] = "cpu1", 1632 [TEGRA_POWERGATE_CPU2] = "cpu2", 1633 [TEGRA_POWERGATE_CPU3] = "cpu3", 1634 [TEGRA_POWERGATE_CPU0] = "cpu0", 1635 [TEGRA_POWERGATE_C0NC] = "c0nc", 1636 [TEGRA_POWERGATE_SOR] = "sor", 1637 [TEGRA_POWERGATE_DIS] = "dis", 1638 [TEGRA_POWERGATE_DISB] = "disb", 1639 [TEGRA_POWERGATE_XUSBA] = "xusba", 1640 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1641 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1642 [TEGRA_POWERGATE_VIC] = "vic", 1643 [TEGRA_POWERGATE_IRAM] = "iram", 1644 [TEGRA_POWERGATE_NVDEC] = "nvdec", 1645 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 1646 [TEGRA_POWERGATE_AUD] = "aud", 1647 [TEGRA_POWERGATE_DFD] = "dfd", 1648 [TEGRA_POWERGATE_VE2] = "ve2", 1649 }; 1650 1651 static const u8 tegra210_cpu_powergates[] = { 1652 TEGRA_POWERGATE_CPU0, 1653 TEGRA_POWERGATE_CPU1, 1654 TEGRA_POWERGATE_CPU2, 1655 TEGRA_POWERGATE_CPU3, 1656 }; 1657 1658 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 1659 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 }, 1660 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 }, 1661 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 }, 1662 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1663 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1664 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX }, 1665 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX }, 1666 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, 1667 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX }, 1668 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 }, 1669 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX }, 1670 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 }, 1671 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX }, 1672 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1673 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, 1674 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, 1675 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, 1676 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX }, 1677 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX }, 1678 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 }, 1679 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, 1680 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1681 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, 1682 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1683 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1684 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, 1685 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1686 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 }, 1687 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 }, 1688 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 }, 1689 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 }, 1690 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 }, 1691 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 }, 1692 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1693 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1694 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1695 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX }, 1696 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1697 }; 1698 1699 static const struct tegra_pmc_soc tegra210_pmc_soc = { 1700 .num_powergates = ARRAY_SIZE(tegra210_powergates), 1701 .powergates = tegra210_powergates, 1702 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 1703 .cpu_powergates = tegra210_cpu_powergates, 1704 .has_tsense_reset = true, 1705 .has_gpu_clamps = true, 1706 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 1707 .io_pads = tegra210_io_pads, 1708 }; 1709 1710 static const struct of_device_id tegra_pmc_match[] = { 1711 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 1712 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 1713 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 1714 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 1715 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 1716 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 1717 { } 1718 }; 1719 1720 static struct platform_driver tegra_pmc_driver = { 1721 .driver = { 1722 .name = "tegra-pmc", 1723 .suppress_bind_attrs = true, 1724 .of_match_table = tegra_pmc_match, 1725 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1726 .pm = &tegra_pmc_pm_ops, 1727 #endif 1728 }, 1729 .probe = tegra_pmc_probe, 1730 }; 1731 builtin_platform_driver(tegra_pmc_driver); 1732 1733 /* 1734 * Early initialization to allow access to registers in the very early boot 1735 * process. 1736 */ 1737 static int __init tegra_pmc_early_init(void) 1738 { 1739 const struct of_device_id *match; 1740 struct device_node *np; 1741 struct resource regs; 1742 bool invert; 1743 u32 value; 1744 1745 mutex_init(&pmc->powergates_lock); 1746 1747 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 1748 if (!np) { 1749 /* 1750 * Fall back to legacy initialization for 32-bit ARM only. All 1751 * 64-bit ARM device tree files for Tegra are required to have 1752 * a PMC node. 1753 * 1754 * This is for backwards-compatibility with old device trees 1755 * that didn't contain a PMC node. Note that in this case the 1756 * SoC data can't be matched and therefore powergating is 1757 * disabled. 1758 */ 1759 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 1760 pr_warn("DT node not found, powergating disabled\n"); 1761 1762 regs.start = 0x7000e400; 1763 regs.end = 0x7000e7ff; 1764 regs.flags = IORESOURCE_MEM; 1765 1766 pr_warn("Using memory region %pR\n", ®s); 1767 } else { 1768 /* 1769 * At this point we're not running on Tegra, so play 1770 * nice with multi-platform kernels. 1771 */ 1772 return 0; 1773 } 1774 } else { 1775 /* 1776 * Extract information from the device tree if we've found a 1777 * matching node. 1778 */ 1779 if (of_address_to_resource(np, 0, ®s) < 0) { 1780 pr_err("failed to get PMC registers\n"); 1781 of_node_put(np); 1782 return -ENXIO; 1783 } 1784 } 1785 1786 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 1787 if (!pmc->base) { 1788 pr_err("failed to map PMC registers\n"); 1789 of_node_put(np); 1790 return -ENXIO; 1791 } 1792 1793 if (np) { 1794 pmc->soc = match->data; 1795 1796 tegra_powergate_init(pmc, np); 1797 1798 /* 1799 * Invert the interrupt polarity if a PMC device tree node 1800 * exists and contains the nvidia,invert-interrupt property. 1801 */ 1802 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 1803 1804 value = tegra_pmc_readl(PMC_CNTRL); 1805 1806 if (invert) 1807 value |= PMC_CNTRL_INTR_POLARITY; 1808 else 1809 value &= ~PMC_CNTRL_INTR_POLARITY; 1810 1811 tegra_pmc_writel(value, PMC_CNTRL); 1812 1813 of_node_put(np); 1814 } 1815 1816 return 0; 1817 } 1818 early_initcall(tegra_pmc_early_init); 1819