pmc.c (57ba33d56884bed7f7043b37b668bb2067abf13b) pmc.c (eac9c48aac0822c2621aa6f3a03b501cd6524bf6)
1/*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>

--- 2219 unchanged lines hidden (view full) ---

2228 .init = NULL,
2229 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2230 .reset_sources = tegra186_reset_sources,
2231 .num_reset_sources = 14,
2232 .reset_levels = tegra186_reset_levels,
2233 .num_reset_levels = 3,
2234};
2235
1/*
2 * drivers/soc/tegra/pmc.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>

--- 2219 unchanged lines hidden (view full) ---

2228 .init = NULL,
2229 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2230 .reset_sources = tegra186_reset_sources,
2231 .num_reset_sources = 14,
2232 .reset_levels = tegra186_reset_levels,
2233 .num_reset_levels = 3,
2234};
2235
2236static const struct tegra_io_pad_soc tegra194_io_pads[] = {
2237 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
2238 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
2239 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
2240 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
2241 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
2242 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
2243 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
2244 { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX },
2245 { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX },
2246 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX },
2247 { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX },
2248 { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX },
2249 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
2250 { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX },
2251 { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX },
2252 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
2253 { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX },
2254 { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX },
2255 { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX },
2256 { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX },
2257 { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX },
2258 { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX },
2259 { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX },
2260 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
2261 { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX },
2262 { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX },
2263 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
2264 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
2265 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
2266 { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX },
2267 { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX },
2268 { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX },
2269 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
2270 { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX },
2271 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
2272 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
2273 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
2274 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
2275 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
2276 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
2277 { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX },
2278 { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX },
2279 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
2280 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX },
2281 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX },
2282 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
2283 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX },
2284};
2285
2286static const struct tegra_pmc_soc tegra194_pmc_soc = {
2287 .num_powergates = 0,
2288 .powergates = NULL,
2289 .num_cpu_powergates = 0,
2290 .cpu_powergates = NULL,
2291 .has_tsense_reset = false,
2292 .has_gpu_clamps = false,
2293 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
2294 .io_pads = tegra194_io_pads,
2295 .regs = &tegra186_pmc_regs,
2296 .init = NULL,
2297 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2298};
2299
2236static const struct of_device_id tegra_pmc_match[] = {
2300static const struct of_device_id tegra_pmc_match[] = {
2237 { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc },
2301 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
2238 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
2239 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
2240 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
2241 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
2242 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
2243 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
2244 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
2245 { }

--- 93 unchanged lines hidden --- 		2302 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
2303 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
2304 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
2305 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
2306 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
2307 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
2308 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
2309 { }

--- 93 unchanged lines hidden ---