1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. 6 * 7 * Author: 8 * Colin Cross <ccross@google.com> 9 * 10 * This software is licensed under the terms of the GNU General Public 11 * License version 2, as published by the Free Software Foundation, and 12 * may be copied, distributed, and modified under those terms. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 */ 20 21 #define pr_fmt(fmt) "tegra-pmc: " fmt 22 23 #include <linux/kernel.h> 24 #include <linux/clk.h> 25 #include <linux/clk/tegra.h> 26 #include <linux/debugfs.h> 27 #include <linux/delay.h> 28 #include <linux/err.h> 29 #include <linux/export.h> 30 #include <linux/init.h> 31 #include <linux/io.h> 32 #include <linux/iopoll.h> 33 #include <linux/of.h> 34 #include <linux/of_address.h> 35 #include <linux/of_clk.h> 36 #include <linux/of_platform.h> 37 #include <linux/pinctrl/pinctrl.h> 38 #include <linux/pinctrl/pinconf.h> 39 #include <linux/pinctrl/pinconf-generic.h> 40 #include <linux/platform_device.h> 41 #include <linux/pm_domain.h> 42 #include <linux/reboot.h> 43 #include <linux/reset.h> 44 #include <linux/seq_file.h> 45 #include <linux/slab.h> 46 #include <linux/spinlock.h> 47 48 #include <soc/tegra/common.h> 49 #include <soc/tegra/fuse.h> 50 #include <soc/tegra/pmc.h> 51 52 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 53 54 #define PMC_CNTRL 0x0 55 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 56 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 57 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 58 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 59 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 60 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 61 #define PMC_CNTRL_MAIN_RST BIT(4) 62 63 #define DPD_SAMPLE 0x020 64 #define DPD_SAMPLE_ENABLE BIT(0) 65 #define DPD_SAMPLE_DISABLE (0 << 0) 66 67 #define PWRGATE_TOGGLE 0x30 68 #define PWRGATE_TOGGLE_START BIT(8) 69 70 #define REMOVE_CLAMPING 0x34 71 72 #define PWRGATE_STATUS 0x38 73 74 #define PMC_IMPL_E_33V_PWR 0x40 75 76 #define PMC_PWR_DET 0x48 77 78 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 79 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 80 #define PMC_SCRATCH0_MODE_RCM BIT(1) 81 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 82 PMC_SCRATCH0_MODE_BOOTLOADER | \ 83 PMC_SCRATCH0_MODE_RCM) 84 85 #define PMC_CPUPWRGOOD_TIMER 0xc8 86 #define PMC_CPUPWROFF_TIMER 0xcc 87 88 #define PMC_PWR_DET_VALUE 0xe4 89 90 #define PMC_SCRATCH41 0x140 91 92 #define PMC_SENSOR_CTRL 0x1b0 93 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 94 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 95 96 #define PMC_RST_STATUS_POR 0 97 #define PMC_RST_STATUS_WATCHDOG 1 98 #define PMC_RST_STATUS_SENSOR 2 99 #define PMC_RST_STATUS_SW_MAIN 3 100 #define PMC_RST_STATUS_LP0 4 101 #define PMC_RST_STATUS_AOTAG 5 102 103 #define IO_DPD_REQ 0x1b8 104 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 105 #define IO_DPD_REQ_CODE_OFF (1U << 30) 106 #define IO_DPD_REQ_CODE_ON (2U << 30) 107 #define IO_DPD_REQ_CODE_MASK (3U << 30) 108 109 #define IO_DPD_STATUS 0x1bc 110 #define IO_DPD2_REQ 0x1c0 111 #define IO_DPD2_STATUS 0x1c4 112 #define SEL_DPD_TIM 0x1c8 113 114 #define PMC_SCRATCH54 0x258 115 #define PMC_SCRATCH54_DATA_SHIFT 8 116 #define PMC_SCRATCH54_ADDR_SHIFT 0 117 118 #define PMC_SCRATCH55 0x25c 119 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 120 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 121 #define PMC_SCRATCH55_PINMUX_SHIFT 24 122 #define PMC_SCRATCH55_16BITOP BIT(15) 123 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 124 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 125 126 #define GPU_RG_CNTRL 0x2d4 127 128 /* Tegra186 and later */ 129 #define WAKE_AOWAKE_CTRL 0x4f4 130 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 131 132 struct tegra_powergate { 133 struct generic_pm_domain genpd; 134 struct tegra_pmc *pmc; 135 unsigned int id; 136 struct clk **clks; 137 unsigned int num_clks; 138 struct reset_control *reset; 139 }; 140 141 struct tegra_io_pad_soc { 142 enum tegra_io_pad id; 143 unsigned int dpd; 144 unsigned int voltage; 145 const char *name; 146 }; 147 148 struct tegra_pmc_regs { 149 unsigned int scratch0; 150 unsigned int dpd_req; 151 unsigned int dpd_status; 152 unsigned int dpd2_req; 153 unsigned int dpd2_status; 154 unsigned int rst_status; 155 unsigned int rst_source_shift; 156 unsigned int rst_source_mask; 157 unsigned int rst_level_shift; 158 unsigned int rst_level_mask; 159 }; 160 161 struct tegra_pmc_soc { 162 unsigned int num_powergates; 163 const char *const *powergates; 164 unsigned int num_cpu_powergates; 165 const u8 *cpu_powergates; 166 167 bool has_tsense_reset; 168 bool has_gpu_clamps; 169 bool needs_mbist_war; 170 bool has_impl_33v_pwr; 171 172 const struct tegra_io_pad_soc *io_pads; 173 unsigned int num_io_pads; 174 175 const struct pinctrl_pin_desc *pin_descs; 176 unsigned int num_pin_descs; 177 178 const struct tegra_pmc_regs *regs; 179 void (*init)(struct tegra_pmc *pmc); 180 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 181 struct device_node *np, 182 bool invert); 183 184 const char * const *reset_sources; 185 unsigned int num_reset_sources; 186 const char * const *reset_levels; 187 unsigned int num_reset_levels; 188 }; 189 190 static const char * const tegra186_reset_sources[] = { 191 "SYS_RESET", 192 "AOWDT", 193 "MCCPLEXWDT", 194 "BPMPWDT", 195 "SCEWDT", 196 "SPEWDT", 197 "APEWDT", 198 "BCCPLEXWDT", 199 "SENSOR", 200 "AOTAG", 201 "VFSENSOR", 202 "SWREST", 203 "SC7", 204 "HSM", 205 "CORESIGHT" 206 }; 207 208 static const char * const tegra186_reset_levels[] = { 209 "L0", "L1", "L2", "WARM" 210 }; 211 212 static const char * const tegra30_reset_sources[] = { 213 "POWER_ON_RESET", 214 "WATCHDOG", 215 "SENSOR", 216 "SW_MAIN", 217 "LP0", 218 "AOTAG" 219 }; 220 221 /** 222 * struct tegra_pmc - NVIDIA Tegra PMC 223 * @dev: pointer to PMC device structure 224 * @base: pointer to I/O remapped register region 225 * @clk: pointer to pclk clock 226 * @soc: pointer to SoC data structure 227 * @debugfs: pointer to debugfs entry 228 * @rate: currently configured rate of pclk 229 * @suspend_mode: lowest suspend mode available 230 * @cpu_good_time: CPU power good time (in microseconds) 231 * @cpu_off_time: CPU power off time (in microsecends) 232 * @core_osc_time: core power good OSC time (in microseconds) 233 * @core_pmu_time: core power good PMU time (in microseconds) 234 * @core_off_time: core power off time (in microseconds) 235 * @corereq_high: core power request is active-high 236 * @sysclkreq_high: system clock request is active-high 237 * @combined_req: combined power request for CPU & core 238 * @cpu_pwr_good_en: CPU power good signal is enabled 239 * @lp0_vec_phys: physical base address of the LP0 warm boot code 240 * @lp0_vec_size: size of the LP0 warm boot code 241 * @powergates_available: Bitmap of available power gates 242 * @powergates_lock: mutex for power gate register access 243 */ 244 struct tegra_pmc { 245 struct device *dev; 246 void __iomem *base; 247 void __iomem *wake; 248 void __iomem *aotag; 249 void __iomem *scratch; 250 struct clk *clk; 251 struct dentry *debugfs; 252 253 const struct tegra_pmc_soc *soc; 254 255 unsigned long rate; 256 257 enum tegra_suspend_mode suspend_mode; 258 u32 cpu_good_time; 259 u32 cpu_off_time; 260 u32 core_osc_time; 261 u32 core_pmu_time; 262 u32 core_off_time; 263 bool corereq_high; 264 bool sysclkreq_high; 265 bool combined_req; 266 bool cpu_pwr_good_en; 267 u32 lp0_vec_phys; 268 u32 lp0_vec_size; 269 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 270 271 struct mutex powergates_lock; 272 273 struct pinctrl_dev *pctl_dev; 274 }; 275 276 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 277 .base = NULL, 278 .suspend_mode = TEGRA_SUSPEND_NONE, 279 }; 280 281 static inline struct tegra_powergate * 282 to_powergate(struct generic_pm_domain *domain) 283 { 284 return container_of(domain, struct tegra_powergate, genpd); 285 } 286 287 static u32 tegra_pmc_readl(unsigned long offset) 288 { 289 return readl(pmc->base + offset); 290 } 291 292 static void tegra_pmc_writel(u32 value, unsigned long offset) 293 { 294 writel(value, pmc->base + offset); 295 } 296 297 static inline bool tegra_powergate_state(int id) 298 { 299 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 300 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; 301 else 302 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 303 } 304 305 static inline bool tegra_powergate_is_valid(int id) 306 { 307 return (pmc->soc && pmc->soc->powergates[id]); 308 } 309 310 static inline bool tegra_powergate_is_available(int id) 311 { 312 return test_bit(id, pmc->powergates_available); 313 } 314 315 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 316 { 317 unsigned int i; 318 319 if (!pmc || !pmc->soc || !name) 320 return -EINVAL; 321 322 for (i = 0; i < pmc->soc->num_powergates; i++) { 323 if (!tegra_powergate_is_valid(i)) 324 continue; 325 326 if (!strcmp(name, pmc->soc->powergates[i])) 327 return i; 328 } 329 330 return -ENODEV; 331 } 332 333 /** 334 * tegra_powergate_set() - set the state of a partition 335 * @id: partition ID 336 * @new_state: new state of the partition 337 */ 338 static int tegra_powergate_set(unsigned int id, bool new_state) 339 { 340 bool status; 341 int err; 342 343 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 344 return -EINVAL; 345 346 mutex_lock(&pmc->powergates_lock); 347 348 if (tegra_powergate_state(id) == new_state) { 349 mutex_unlock(&pmc->powergates_lock); 350 return 0; 351 } 352 353 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 354 355 err = readx_poll_timeout(tegra_powergate_state, id, status, 356 status == new_state, 10, 100000); 357 358 mutex_unlock(&pmc->powergates_lock); 359 360 return err; 361 } 362 363 static int __tegra_powergate_remove_clamping(unsigned int id) 364 { 365 u32 mask; 366 367 mutex_lock(&pmc->powergates_lock); 368 369 /* 370 * On Tegra124 and later, the clamps for the GPU are controlled by a 371 * separate register (with different semantics). 372 */ 373 if (id == TEGRA_POWERGATE_3D) { 374 if (pmc->soc->has_gpu_clamps) { 375 tegra_pmc_writel(0, GPU_RG_CNTRL); 376 goto out; 377 } 378 } 379 380 /* 381 * Tegra 2 has a bug where PCIE and VDE clamping masks are 382 * swapped relatively to the partition ids 383 */ 384 if (id == TEGRA_POWERGATE_VDEC) 385 mask = (1 << TEGRA_POWERGATE_PCIE); 386 else if (id == TEGRA_POWERGATE_PCIE) 387 mask = (1 << TEGRA_POWERGATE_VDEC); 388 else 389 mask = (1 << id); 390 391 tegra_pmc_writel(mask, REMOVE_CLAMPING); 392 393 out: 394 mutex_unlock(&pmc->powergates_lock); 395 396 return 0; 397 } 398 399 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 400 { 401 unsigned int i; 402 403 for (i = 0; i < pg->num_clks; i++) 404 clk_disable_unprepare(pg->clks[i]); 405 } 406 407 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 408 { 409 unsigned int i; 410 int err; 411 412 for (i = 0; i < pg->num_clks; i++) { 413 err = clk_prepare_enable(pg->clks[i]); 414 if (err) 415 goto out; 416 } 417 418 return 0; 419 420 out: 421 while (i--) 422 clk_disable_unprepare(pg->clks[i]); 423 424 return err; 425 } 426 427 int __weak tegra210_clk_handle_mbist_war(unsigned int id) 428 { 429 return 0; 430 } 431 432 static int tegra_powergate_power_up(struct tegra_powergate *pg, 433 bool disable_clocks) 434 { 435 int err; 436 437 err = reset_control_assert(pg->reset); 438 if (err) 439 return err; 440 441 usleep_range(10, 20); 442 443 err = tegra_powergate_set(pg->id, true); 444 if (err < 0) 445 return err; 446 447 usleep_range(10, 20); 448 449 err = tegra_powergate_enable_clocks(pg); 450 if (err) 451 goto disable_clks; 452 453 usleep_range(10, 20); 454 455 err = __tegra_powergate_remove_clamping(pg->id); 456 if (err) 457 goto disable_clks; 458 459 usleep_range(10, 20); 460 461 err = reset_control_deassert(pg->reset); 462 if (err) 463 goto powergate_off; 464 465 usleep_range(10, 20); 466 467 if (pg->pmc->soc->needs_mbist_war) 468 err = tegra210_clk_handle_mbist_war(pg->id); 469 if (err) 470 goto disable_clks; 471 472 if (disable_clocks) 473 tegra_powergate_disable_clocks(pg); 474 475 return 0; 476 477 disable_clks: 478 tegra_powergate_disable_clocks(pg); 479 usleep_range(10, 20); 480 481 powergate_off: 482 tegra_powergate_set(pg->id, false); 483 484 return err; 485 } 486 487 static int tegra_powergate_power_down(struct tegra_powergate *pg) 488 { 489 int err; 490 491 err = tegra_powergate_enable_clocks(pg); 492 if (err) 493 return err; 494 495 usleep_range(10, 20); 496 497 err = reset_control_assert(pg->reset); 498 if (err) 499 goto disable_clks; 500 501 usleep_range(10, 20); 502 503 tegra_powergate_disable_clocks(pg); 504 505 usleep_range(10, 20); 506 507 err = tegra_powergate_set(pg->id, false); 508 if (err) 509 goto assert_resets; 510 511 return 0; 512 513 assert_resets: 514 tegra_powergate_enable_clocks(pg); 515 usleep_range(10, 20); 516 reset_control_deassert(pg->reset); 517 usleep_range(10, 20); 518 519 disable_clks: 520 tegra_powergate_disable_clocks(pg); 521 522 return err; 523 } 524 525 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 526 { 527 struct tegra_powergate *pg = to_powergate(domain); 528 int err; 529 530 err = tegra_powergate_power_up(pg, true); 531 if (err) 532 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name, 533 err); 534 535 return err; 536 } 537 538 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 539 { 540 struct tegra_powergate *pg = to_powergate(domain); 541 int err; 542 543 err = tegra_powergate_power_down(pg); 544 if (err) 545 pr_err("failed to turn off PM domain %s: %d\n", 546 pg->genpd.name, err); 547 548 return err; 549 } 550 551 /** 552 * tegra_powergate_power_on() - power on partition 553 * @id: partition ID 554 */ 555 int tegra_powergate_power_on(unsigned int id) 556 { 557 if (!tegra_powergate_is_available(id)) 558 return -EINVAL; 559 560 return tegra_powergate_set(id, true); 561 } 562 563 /** 564 * tegra_powergate_power_off() - power off partition 565 * @id: partition ID 566 */ 567 int tegra_powergate_power_off(unsigned int id) 568 { 569 if (!tegra_powergate_is_available(id)) 570 return -EINVAL; 571 572 return tegra_powergate_set(id, false); 573 } 574 EXPORT_SYMBOL(tegra_powergate_power_off); 575 576 /** 577 * tegra_powergate_is_powered() - check if partition is powered 578 * @id: partition ID 579 */ 580 int tegra_powergate_is_powered(unsigned int id) 581 { 582 if (!tegra_powergate_is_valid(id)) 583 return -EINVAL; 584 585 return tegra_powergate_state(id); 586 } 587 588 /** 589 * tegra_powergate_remove_clamping() - remove power clamps for partition 590 * @id: partition ID 591 */ 592 int tegra_powergate_remove_clamping(unsigned int id) 593 { 594 if (!tegra_powergate_is_available(id)) 595 return -EINVAL; 596 597 return __tegra_powergate_remove_clamping(id); 598 } 599 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 600 601 /** 602 * tegra_powergate_sequence_power_up() - power up partition 603 * @id: partition ID 604 * @clk: clock for partition 605 * @rst: reset for partition 606 * 607 * Must be called with clk disabled, and returns with clk enabled. 608 */ 609 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 610 struct reset_control *rst) 611 { 612 struct tegra_powergate *pg; 613 int err; 614 615 if (!tegra_powergate_is_available(id)) 616 return -EINVAL; 617 618 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 619 if (!pg) 620 return -ENOMEM; 621 622 pg->id = id; 623 pg->clks = &clk; 624 pg->num_clks = 1; 625 pg->reset = rst; 626 pg->pmc = pmc; 627 628 err = tegra_powergate_power_up(pg, false); 629 if (err) 630 pr_err("failed to turn on partition %d: %d\n", id, err); 631 632 kfree(pg); 633 634 return err; 635 } 636 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 637 638 #ifdef CONFIG_SMP 639 /** 640 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 641 * @cpuid: CPU partition ID 642 * 643 * Returns the partition ID corresponding to the CPU partition ID or a 644 * negative error code on failure. 645 */ 646 static int tegra_get_cpu_powergate_id(unsigned int cpuid) 647 { 648 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 649 return pmc->soc->cpu_powergates[cpuid]; 650 651 return -EINVAL; 652 } 653 654 /** 655 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 656 * @cpuid: CPU partition ID 657 */ 658 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 659 { 660 int id; 661 662 id = tegra_get_cpu_powergate_id(cpuid); 663 if (id < 0) 664 return false; 665 666 return tegra_powergate_is_powered(id); 667 } 668 669 /** 670 * tegra_pmc_cpu_power_on() - power on CPU partition 671 * @cpuid: CPU partition ID 672 */ 673 int tegra_pmc_cpu_power_on(unsigned int cpuid) 674 { 675 int id; 676 677 id = tegra_get_cpu_powergate_id(cpuid); 678 if (id < 0) 679 return id; 680 681 return tegra_powergate_set(id, true); 682 } 683 684 /** 685 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 686 * @cpuid: CPU partition ID 687 */ 688 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 689 { 690 int id; 691 692 id = tegra_get_cpu_powergate_id(cpuid); 693 if (id < 0) 694 return id; 695 696 return tegra_powergate_remove_clamping(id); 697 } 698 #endif /* CONFIG_SMP */ 699 700 static int tegra_pmc_restart_notify(struct notifier_block *this, 701 unsigned long action, void *data) 702 { 703 const char *cmd = data; 704 u32 value; 705 706 value = readl(pmc->scratch + pmc->soc->regs->scratch0); 707 value &= ~PMC_SCRATCH0_MODE_MASK; 708 709 if (cmd) { 710 if (strcmp(cmd, "recovery") == 0) 711 value |= PMC_SCRATCH0_MODE_RECOVERY; 712 713 if (strcmp(cmd, "bootloader") == 0) 714 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 715 716 if (strcmp(cmd, "forced-recovery") == 0) 717 value |= PMC_SCRATCH0_MODE_RCM; 718 } 719 720 writel(value, pmc->scratch + pmc->soc->regs->scratch0); 721 722 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 723 value = tegra_pmc_readl(PMC_CNTRL); 724 value |= PMC_CNTRL_MAIN_RST; 725 tegra_pmc_writel(value, PMC_CNTRL); 726 727 return NOTIFY_DONE; 728 } 729 730 static struct notifier_block tegra_pmc_restart_handler = { 731 .notifier_call = tegra_pmc_restart_notify, 732 .priority = 128, 733 }; 734 735 static int powergate_show(struct seq_file *s, void *data) 736 { 737 unsigned int i; 738 int status; 739 740 seq_printf(s, " powergate powered\n"); 741 seq_printf(s, "------------------\n"); 742 743 for (i = 0; i < pmc->soc->num_powergates; i++) { 744 status = tegra_powergate_is_powered(i); 745 if (status < 0) 746 continue; 747 748 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 749 status ? "yes" : "no"); 750 } 751 752 return 0; 753 } 754 755 DEFINE_SHOW_ATTRIBUTE(powergate); 756 757 static int tegra_powergate_debugfs_init(void) 758 { 759 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 760 &powergate_fops); 761 if (!pmc->debugfs) 762 return -ENOMEM; 763 764 return 0; 765 } 766 767 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 768 struct device_node *np) 769 { 770 struct clk *clk; 771 unsigned int i, count; 772 int err; 773 774 count = of_clk_get_parent_count(np); 775 if (count == 0) 776 return -ENODEV; 777 778 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 779 if (!pg->clks) 780 return -ENOMEM; 781 782 for (i = 0; i < count; i++) { 783 pg->clks[i] = of_clk_get(np, i); 784 if (IS_ERR(pg->clks[i])) { 785 err = PTR_ERR(pg->clks[i]); 786 goto err; 787 } 788 } 789 790 pg->num_clks = count; 791 792 return 0; 793 794 err: 795 while (i--) 796 clk_put(pg->clks[i]); 797 798 kfree(pg->clks); 799 800 return err; 801 } 802 803 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 804 struct device_node *np, bool off) 805 { 806 int err; 807 808 pg->reset = of_reset_control_array_get_exclusive(np); 809 if (IS_ERR(pg->reset)) { 810 err = PTR_ERR(pg->reset); 811 pr_err("failed to get device resets: %d\n", err); 812 return err; 813 } 814 815 if (off) 816 err = reset_control_assert(pg->reset); 817 else 818 err = reset_control_deassert(pg->reset); 819 820 if (err) 821 reset_control_put(pg->reset); 822 823 return err; 824 } 825 826 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 827 { 828 struct tegra_powergate *pg; 829 int id, err; 830 bool off; 831 832 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 833 if (!pg) 834 return; 835 836 id = tegra_powergate_lookup(pmc, np->name); 837 if (id < 0) { 838 pr_err("powergate lookup failed for %pOFn: %d\n", np, id); 839 goto free_mem; 840 } 841 842 /* 843 * Clear the bit for this powergate so it cannot be managed 844 * directly via the legacy APIs for controlling powergates. 845 */ 846 clear_bit(id, pmc->powergates_available); 847 848 pg->id = id; 849 pg->genpd.name = np->name; 850 pg->genpd.power_off = tegra_genpd_power_off; 851 pg->genpd.power_on = tegra_genpd_power_on; 852 pg->pmc = pmc; 853 854 off = !tegra_powergate_is_powered(pg->id); 855 856 err = tegra_powergate_of_get_clks(pg, np); 857 if (err < 0) { 858 pr_err("failed to get clocks for %pOFn: %d\n", np, err); 859 goto set_available; 860 } 861 862 err = tegra_powergate_of_get_resets(pg, np, off); 863 if (err < 0) { 864 pr_err("failed to get resets for %pOFn: %d\n", np, err); 865 goto remove_clks; 866 } 867 868 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 869 if (off) 870 WARN_ON(tegra_powergate_power_up(pg, true)); 871 872 goto remove_resets; 873 } 874 875 err = pm_genpd_init(&pg->genpd, NULL, off); 876 if (err < 0) { 877 pr_err("failed to initialise PM domain %pOFn: %d\n", np, 878 err); 879 goto remove_resets; 880 } 881 882 err = of_genpd_add_provider_simple(np, &pg->genpd); 883 if (err < 0) { 884 pr_err("failed to add PM domain provider for %pOFn: %d\n", 885 np, err); 886 goto remove_genpd; 887 } 888 889 pr_debug("added PM domain %s\n", pg->genpd.name); 890 891 return; 892 893 remove_genpd: 894 pm_genpd_remove(&pg->genpd); 895 896 remove_resets: 897 reset_control_put(pg->reset); 898 899 remove_clks: 900 while (pg->num_clks--) 901 clk_put(pg->clks[pg->num_clks]); 902 903 kfree(pg->clks); 904 905 set_available: 906 set_bit(id, pmc->powergates_available); 907 908 free_mem: 909 kfree(pg); 910 } 911 912 static void tegra_powergate_init(struct tegra_pmc *pmc, 913 struct device_node *parent) 914 { 915 struct device_node *np, *child; 916 unsigned int i; 917 918 /* Create a bitmap of the available and valid partitions */ 919 for (i = 0; i < pmc->soc->num_powergates; i++) 920 if (pmc->soc->powergates[i]) 921 set_bit(i, pmc->powergates_available); 922 923 np = of_get_child_by_name(parent, "powergates"); 924 if (!np) 925 return; 926 927 for_each_child_of_node(np, child) 928 tegra_powergate_add(pmc, child); 929 930 of_node_put(np); 931 } 932 933 static const struct tegra_io_pad_soc * 934 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 935 { 936 unsigned int i; 937 938 for (i = 0; i < pmc->soc->num_io_pads; i++) 939 if (pmc->soc->io_pads[i].id == id) 940 return &pmc->soc->io_pads[i]; 941 942 return NULL; 943 } 944 945 static int tegra_io_pad_get_dpd_register_bit(enum tegra_io_pad id, 946 unsigned long *request, 947 unsigned long *status, 948 u32 *mask) 949 { 950 const struct tegra_io_pad_soc *pad; 951 952 pad = tegra_io_pad_find(pmc, id); 953 if (!pad) { 954 pr_err("invalid I/O pad ID %u\n", id); 955 return -ENOENT; 956 } 957 958 if (pad->dpd == UINT_MAX) 959 return -ENOTSUPP; 960 961 *mask = BIT(pad->dpd % 32); 962 963 if (pad->dpd < 32) { 964 *status = pmc->soc->regs->dpd_status; 965 *request = pmc->soc->regs->dpd_req; 966 } else { 967 *status = pmc->soc->regs->dpd2_status; 968 *request = pmc->soc->regs->dpd2_req; 969 } 970 971 return 0; 972 } 973 974 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, 975 unsigned long *status, u32 *mask) 976 { 977 unsigned long rate, value; 978 int err; 979 980 err = tegra_io_pad_get_dpd_register_bit(id, request, status, mask); 981 if (err) 982 return err; 983 984 if (pmc->clk) { 985 rate = clk_get_rate(pmc->clk); 986 if (!rate) { 987 pr_err("failed to get clock rate\n"); 988 return -ENODEV; 989 } 990 991 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 992 993 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 994 value = DIV_ROUND_UP(1000000000, rate); 995 value = DIV_ROUND_UP(200, value); 996 tegra_pmc_writel(value, SEL_DPD_TIM); 997 } 998 999 return 0; 1000 } 1001 1002 static int tegra_io_pad_poll(unsigned long offset, u32 mask, 1003 u32 val, unsigned long timeout) 1004 { 1005 u32 value; 1006 1007 timeout = jiffies + msecs_to_jiffies(timeout); 1008 1009 while (time_after(timeout, jiffies)) { 1010 value = tegra_pmc_readl(offset); 1011 if ((value & mask) == val) 1012 return 0; 1013 1014 usleep_range(250, 1000); 1015 } 1016 1017 return -ETIMEDOUT; 1018 } 1019 1020 static void tegra_io_pad_unprepare(void) 1021 { 1022 if (pmc->clk) 1023 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1024 } 1025 1026 /** 1027 * tegra_io_pad_power_enable() - enable power to I/O pad 1028 * @id: Tegra I/O pad ID for which to enable power 1029 * 1030 * Returns: 0 on success or a negative error code on failure. 1031 */ 1032 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1033 { 1034 unsigned long request, status; 1035 u32 mask; 1036 int err; 1037 1038 mutex_lock(&pmc->powergates_lock); 1039 1040 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1041 if (err < 0) { 1042 pr_err("failed to prepare I/O pad: %d\n", err); 1043 goto unlock; 1044 } 1045 1046 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request); 1047 1048 err = tegra_io_pad_poll(status, mask, 0, 250); 1049 if (err < 0) { 1050 pr_err("failed to enable I/O pad: %d\n", err); 1051 goto unlock; 1052 } 1053 1054 tegra_io_pad_unprepare(); 1055 1056 unlock: 1057 mutex_unlock(&pmc->powergates_lock); 1058 return err; 1059 } 1060 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1061 1062 /** 1063 * tegra_io_pad_power_disable() - disable power to I/O pad 1064 * @id: Tegra I/O pad ID for which to disable power 1065 * 1066 * Returns: 0 on success or a negative error code on failure. 1067 */ 1068 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1069 { 1070 unsigned long request, status; 1071 u32 mask; 1072 int err; 1073 1074 mutex_lock(&pmc->powergates_lock); 1075 1076 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1077 if (err < 0) { 1078 pr_err("failed to prepare I/O pad: %d\n", err); 1079 goto unlock; 1080 } 1081 1082 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request); 1083 1084 err = tegra_io_pad_poll(status, mask, mask, 250); 1085 if (err < 0) { 1086 pr_err("failed to disable I/O pad: %d\n", err); 1087 goto unlock; 1088 } 1089 1090 tegra_io_pad_unprepare(); 1091 1092 unlock: 1093 mutex_unlock(&pmc->powergates_lock); 1094 return err; 1095 } 1096 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1097 1098 static int tegra_io_pad_is_powered(enum tegra_io_pad id) 1099 { 1100 unsigned long request, status; 1101 u32 mask, value; 1102 int err; 1103 1104 err = tegra_io_pad_get_dpd_register_bit(id, &request, &status, &mask); 1105 if (err) 1106 return err; 1107 1108 value = tegra_pmc_readl(status); 1109 1110 return !(value & mask); 1111 } 1112 1113 static int tegra_io_pad_set_voltage(enum tegra_io_pad id, int voltage) 1114 { 1115 const struct tegra_io_pad_soc *pad; 1116 u32 value; 1117 1118 pad = tegra_io_pad_find(pmc, id); 1119 if (!pad) 1120 return -ENOENT; 1121 1122 if (pad->voltage == UINT_MAX) 1123 return -ENOTSUPP; 1124 1125 mutex_lock(&pmc->powergates_lock); 1126 1127 if (pmc->soc->has_impl_33v_pwr) { 1128 value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR); 1129 1130 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1131 value &= ~BIT(pad->voltage); 1132 else 1133 value |= BIT(pad->voltage); 1134 1135 tegra_pmc_writel(value, PMC_IMPL_E_33V_PWR); 1136 } else { 1137 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1138 value = tegra_pmc_readl(PMC_PWR_DET); 1139 value |= BIT(pad->voltage); 1140 tegra_pmc_writel(value, PMC_PWR_DET); 1141 1142 /* update I/O voltage */ 1143 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1144 1145 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1146 value &= ~BIT(pad->voltage); 1147 else 1148 value |= BIT(pad->voltage); 1149 1150 tegra_pmc_writel(value, PMC_PWR_DET_VALUE); 1151 } 1152 1153 mutex_unlock(&pmc->powergates_lock); 1154 1155 usleep_range(100, 250); 1156 1157 return 0; 1158 } 1159 1160 static int tegra_io_pad_get_voltage(enum tegra_io_pad id) 1161 { 1162 const struct tegra_io_pad_soc *pad; 1163 u32 value; 1164 1165 pad = tegra_io_pad_find(pmc, id); 1166 if (!pad) 1167 return -ENOENT; 1168 1169 if (pad->voltage == UINT_MAX) 1170 return -ENOTSUPP; 1171 1172 if (pmc->soc->has_impl_33v_pwr) 1173 value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR); 1174 else 1175 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1176 1177 if ((value & BIT(pad->voltage)) == 0) 1178 return TEGRA_IO_PAD_VOLTAGE_1V8; 1179 1180 return TEGRA_IO_PAD_VOLTAGE_3V3; 1181 } 1182 1183 /** 1184 * tegra_io_rail_power_on() - enable power to I/O rail 1185 * @id: Tegra I/O pad ID for which to enable power 1186 * 1187 * See also: tegra_io_pad_power_enable() 1188 */ 1189 int tegra_io_rail_power_on(unsigned int id) 1190 { 1191 return tegra_io_pad_power_enable(id); 1192 } 1193 EXPORT_SYMBOL(tegra_io_rail_power_on); 1194 1195 /** 1196 * tegra_io_rail_power_off() - disable power to I/O rail 1197 * @id: Tegra I/O pad ID for which to disable power 1198 * 1199 * See also: tegra_io_pad_power_disable() 1200 */ 1201 int tegra_io_rail_power_off(unsigned int id) 1202 { 1203 return tegra_io_pad_power_disable(id); 1204 } 1205 EXPORT_SYMBOL(tegra_io_rail_power_off); 1206 1207 #ifdef CONFIG_PM_SLEEP 1208 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1209 { 1210 return pmc->suspend_mode; 1211 } 1212 1213 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1214 { 1215 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1216 return; 1217 1218 pmc->suspend_mode = mode; 1219 } 1220 1221 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1222 { 1223 unsigned long long rate = 0; 1224 u32 value; 1225 1226 switch (mode) { 1227 case TEGRA_SUSPEND_LP1: 1228 rate = 32768; 1229 break; 1230 1231 case TEGRA_SUSPEND_LP2: 1232 rate = clk_get_rate(pmc->clk); 1233 break; 1234 1235 default: 1236 break; 1237 } 1238 1239 if (WARN_ON_ONCE(rate == 0)) 1240 rate = 100000000; 1241 1242 if (rate != pmc->rate) { 1243 u64 ticks; 1244 1245 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1246 do_div(ticks, USEC_PER_SEC); 1247 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 1248 1249 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1250 do_div(ticks, USEC_PER_SEC); 1251 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 1252 1253 wmb(); 1254 1255 pmc->rate = rate; 1256 } 1257 1258 value = tegra_pmc_readl(PMC_CNTRL); 1259 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1260 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1261 tegra_pmc_writel(value, PMC_CNTRL); 1262 } 1263 #endif 1264 1265 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1266 { 1267 u32 value, values[2]; 1268 1269 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1270 } else { 1271 switch (value) { 1272 case 0: 1273 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1274 break; 1275 1276 case 1: 1277 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1278 break; 1279 1280 case 2: 1281 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1282 break; 1283 1284 default: 1285 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1286 break; 1287 } 1288 } 1289 1290 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1291 1292 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1293 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1294 1295 pmc->cpu_good_time = value; 1296 1297 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1298 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1299 1300 pmc->cpu_off_time = value; 1301 1302 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1303 values, ARRAY_SIZE(values))) 1304 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1305 1306 pmc->core_osc_time = values[0]; 1307 pmc->core_pmu_time = values[1]; 1308 1309 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1310 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1311 1312 pmc->core_off_time = value; 1313 1314 pmc->corereq_high = of_property_read_bool(np, 1315 "nvidia,core-power-req-active-high"); 1316 1317 pmc->sysclkreq_high = of_property_read_bool(np, 1318 "nvidia,sys-clock-req-active-high"); 1319 1320 pmc->combined_req = of_property_read_bool(np, 1321 "nvidia,combined-power-req"); 1322 1323 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1324 "nvidia,cpu-pwr-good-en"); 1325 1326 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1327 ARRAY_SIZE(values))) 1328 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1329 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1330 1331 pmc->lp0_vec_phys = values[0]; 1332 pmc->lp0_vec_size = values[1]; 1333 1334 return 0; 1335 } 1336 1337 static void tegra_pmc_init(struct tegra_pmc *pmc) 1338 { 1339 if (pmc->soc->init) 1340 pmc->soc->init(pmc); 1341 } 1342 1343 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1344 { 1345 static const char disabled[] = "emergency thermal reset disabled"; 1346 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1347 struct device *dev = pmc->dev; 1348 struct device_node *np; 1349 u32 value, checksum; 1350 1351 if (!pmc->soc->has_tsense_reset) 1352 return; 1353 1354 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1355 if (!np) { 1356 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1357 return; 1358 } 1359 1360 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1361 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1362 goto out; 1363 } 1364 1365 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1366 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1367 goto out; 1368 } 1369 1370 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1371 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1372 goto out; 1373 } 1374 1375 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1376 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1377 goto out; 1378 } 1379 1380 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1381 pinmux = 0; 1382 1383 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1384 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1385 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1386 1387 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1388 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1389 tegra_pmc_writel(value, PMC_SCRATCH54); 1390 1391 value = PMC_SCRATCH55_RESET_TEGRA; 1392 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1393 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1394 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1395 1396 /* 1397 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1398 * contain the checksum and are currently zero, so they are not added. 1399 */ 1400 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1401 + ((value >> 24) & 0xff); 1402 checksum &= 0xff; 1403 checksum = 0x100 - checksum; 1404 1405 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1406 1407 tegra_pmc_writel(value, PMC_SCRATCH55); 1408 1409 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1410 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1411 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1412 1413 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1414 1415 out: 1416 of_node_put(np); 1417 } 1418 1419 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 1420 { 1421 return pmc->soc->num_io_pads; 1422 } 1423 1424 static const char *tegra_io_pad_pinctrl_get_group_name( 1425 struct pinctrl_dev *pctl, unsigned int group) 1426 { 1427 return pmc->soc->io_pads[group].name; 1428 } 1429 1430 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 1431 unsigned int group, 1432 const unsigned int **pins, 1433 unsigned int *num_pins) 1434 { 1435 *pins = &pmc->soc->io_pads[group].id; 1436 *num_pins = 1; 1437 return 0; 1438 } 1439 1440 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 1441 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 1442 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 1443 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 1444 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1445 .dt_free_map = pinconf_generic_dt_free_map, 1446 }; 1447 1448 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 1449 unsigned int pin, unsigned long *config) 1450 { 1451 const struct tegra_io_pad_soc *pad = tegra_io_pad_find(pmc, pin); 1452 enum pin_config_param param = pinconf_to_config_param(*config); 1453 int ret; 1454 u32 arg; 1455 1456 if (!pad) 1457 return -EINVAL; 1458 1459 switch (param) { 1460 case PIN_CONFIG_POWER_SOURCE: 1461 ret = tegra_io_pad_get_voltage(pad->id); 1462 if (ret < 0) 1463 return ret; 1464 arg = ret; 1465 break; 1466 case PIN_CONFIG_LOW_POWER_MODE: 1467 ret = tegra_io_pad_is_powered(pad->id); 1468 if (ret < 0) 1469 return ret; 1470 arg = !ret; 1471 break; 1472 default: 1473 return -EINVAL; 1474 } 1475 1476 *config = pinconf_to_config_packed(param, arg); 1477 1478 return 0; 1479 } 1480 1481 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 1482 unsigned int pin, unsigned long *configs, 1483 unsigned int num_configs) 1484 { 1485 const struct tegra_io_pad_soc *pad = tegra_io_pad_find(pmc, pin); 1486 enum pin_config_param param; 1487 unsigned int i; 1488 int err; 1489 u32 arg; 1490 1491 if (!pad) 1492 return -EINVAL; 1493 1494 for (i = 0; i < num_configs; ++i) { 1495 param = pinconf_to_config_param(configs[i]); 1496 arg = pinconf_to_config_argument(configs[i]); 1497 1498 switch (param) { 1499 case PIN_CONFIG_LOW_POWER_MODE: 1500 if (arg) 1501 err = tegra_io_pad_power_disable(pad->id); 1502 else 1503 err = tegra_io_pad_power_enable(pad->id); 1504 if (err) 1505 return err; 1506 break; 1507 case PIN_CONFIG_POWER_SOURCE: 1508 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 1509 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 1510 return -EINVAL; 1511 err = tegra_io_pad_set_voltage(pad->id, arg); 1512 if (err) 1513 return err; 1514 break; 1515 default: 1516 return -EINVAL; 1517 } 1518 } 1519 1520 return 0; 1521 } 1522 1523 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 1524 .pin_config_get = tegra_io_pad_pinconf_get, 1525 .pin_config_set = tegra_io_pad_pinconf_set, 1526 .is_generic = true, 1527 }; 1528 1529 static struct pinctrl_desc tegra_pmc_pctl_desc = { 1530 .pctlops = &tegra_io_pad_pinctrl_ops, 1531 .confops = &tegra_io_pad_pinconf_ops, 1532 }; 1533 1534 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 1535 { 1536 int err = 0; 1537 1538 if (!pmc->soc->num_pin_descs) 1539 return 0; 1540 1541 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 1542 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 1543 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 1544 1545 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 1546 pmc); 1547 if (IS_ERR(pmc->pctl_dev)) { 1548 err = PTR_ERR(pmc->pctl_dev); 1549 dev_err(pmc->dev, "unable to register pinctrl, %d\n", err); 1550 } 1551 1552 return err; 1553 } 1554 1555 static ssize_t reset_reason_show(struct device *dev, 1556 struct device_attribute *attr, char *buf) 1557 { 1558 u32 value, rst_src; 1559 1560 value = tegra_pmc_readl(pmc->soc->regs->rst_status); 1561 rst_src = (value & pmc->soc->regs->rst_source_mask) >> 1562 pmc->soc->regs->rst_source_shift; 1563 1564 return sprintf(buf, "%s\n", pmc->soc->reset_sources[rst_src]); 1565 } 1566 1567 static DEVICE_ATTR_RO(reset_reason); 1568 1569 static ssize_t reset_level_show(struct device *dev, 1570 struct device_attribute *attr, char *buf) 1571 { 1572 u32 value, rst_lvl; 1573 1574 value = tegra_pmc_readl(pmc->soc->regs->rst_status); 1575 rst_lvl = (value & pmc->soc->regs->rst_level_mask) >> 1576 pmc->soc->regs->rst_level_shift; 1577 1578 return sprintf(buf, "%s\n", pmc->soc->reset_levels[rst_lvl]); 1579 } 1580 1581 static DEVICE_ATTR_RO(reset_level); 1582 1583 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 1584 { 1585 struct device *dev = pmc->dev; 1586 int err = 0; 1587 1588 if (pmc->soc->reset_sources) { 1589 err = device_create_file(dev, &dev_attr_reset_reason); 1590 if (err < 0) 1591 dev_warn(dev, 1592 "failed to create attr \"reset_reason\": %d\n", 1593 err); 1594 } 1595 1596 if (pmc->soc->reset_levels) { 1597 err = device_create_file(dev, &dev_attr_reset_level); 1598 if (err < 0) 1599 dev_warn(dev, 1600 "failed to create attr \"reset_level\": %d\n", 1601 err); 1602 } 1603 } 1604 1605 static int tegra_pmc_probe(struct platform_device *pdev) 1606 { 1607 void __iomem *base; 1608 struct resource *res; 1609 int err; 1610 1611 /* 1612 * Early initialisation should have configured an initial 1613 * register mapping and setup the soc data pointer. If these 1614 * are not valid then something went badly wrong! 1615 */ 1616 if (WARN_ON(!pmc->base || !pmc->soc)) 1617 return -ENODEV; 1618 1619 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1620 if (err < 0) 1621 return err; 1622 1623 /* take over the memory region from the early initialization */ 1624 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1625 base = devm_ioremap_resource(&pdev->dev, res); 1626 if (IS_ERR(base)) 1627 return PTR_ERR(base); 1628 1629 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 1630 if (res) { 1631 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 1632 if (IS_ERR(pmc->wake)) 1633 return PTR_ERR(pmc->wake); 1634 } else { 1635 pmc->wake = base; 1636 } 1637 1638 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 1639 if (res) { 1640 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 1641 if (IS_ERR(pmc->aotag)) 1642 return PTR_ERR(pmc->aotag); 1643 } else { 1644 pmc->aotag = base; 1645 } 1646 1647 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 1648 if (res) { 1649 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 1650 if (IS_ERR(pmc->scratch)) 1651 return PTR_ERR(pmc->scratch); 1652 } else { 1653 pmc->scratch = base; 1654 } 1655 1656 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1657 if (IS_ERR(pmc->clk)) { 1658 err = PTR_ERR(pmc->clk); 1659 1660 if (err != -ENOENT) { 1661 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1662 return err; 1663 } 1664 1665 pmc->clk = NULL; 1666 } 1667 1668 pmc->dev = &pdev->dev; 1669 1670 tegra_pmc_init(pmc); 1671 1672 tegra_pmc_init_tsense_reset(pmc); 1673 1674 tegra_pmc_reset_sysfs_init(pmc); 1675 1676 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1677 err = tegra_powergate_debugfs_init(); 1678 if (err < 0) 1679 return err; 1680 } 1681 1682 err = register_restart_handler(&tegra_pmc_restart_handler); 1683 if (err) { 1684 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 1685 err); 1686 goto cleanup_debugfs; 1687 } 1688 1689 err = tegra_pmc_pinctrl_init(pmc); 1690 if (err) 1691 goto cleanup_restart_handler; 1692 1693 mutex_lock(&pmc->powergates_lock); 1694 iounmap(pmc->base); 1695 pmc->base = base; 1696 mutex_unlock(&pmc->powergates_lock); 1697 1698 return 0; 1699 1700 cleanup_restart_handler: 1701 unregister_restart_handler(&tegra_pmc_restart_handler); 1702 cleanup_debugfs: 1703 debugfs_remove(pmc->debugfs); 1704 return err; 1705 } 1706 1707 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1708 static int tegra_pmc_suspend(struct device *dev) 1709 { 1710 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 1711 1712 return 0; 1713 } 1714 1715 static int tegra_pmc_resume(struct device *dev) 1716 { 1717 tegra_pmc_writel(0x0, PMC_SCRATCH41); 1718 1719 return 0; 1720 } 1721 1722 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 1723 1724 #endif 1725 1726 static const char * const tegra20_powergates[] = { 1727 [TEGRA_POWERGATE_CPU] = "cpu", 1728 [TEGRA_POWERGATE_3D] = "3d", 1729 [TEGRA_POWERGATE_VENC] = "venc", 1730 [TEGRA_POWERGATE_VDEC] = "vdec", 1731 [TEGRA_POWERGATE_PCIE] = "pcie", 1732 [TEGRA_POWERGATE_L2] = "l2", 1733 [TEGRA_POWERGATE_MPE] = "mpe", 1734 }; 1735 1736 static const struct tegra_pmc_regs tegra20_pmc_regs = { 1737 .scratch0 = 0x50, 1738 .dpd_req = 0x1b8, 1739 .dpd_status = 0x1bc, 1740 .dpd2_req = 0x1c0, 1741 .dpd2_status = 0x1c4, 1742 .rst_status = 0x1b4, 1743 .rst_source_shift = 0x0, 1744 .rst_source_mask = 0x7, 1745 .rst_level_shift = 0x0, 1746 .rst_level_mask = 0x0, 1747 }; 1748 1749 static void tegra20_pmc_init(struct tegra_pmc *pmc) 1750 { 1751 u32 value; 1752 1753 /* Always enable CPU power request */ 1754 value = tegra_pmc_readl(PMC_CNTRL); 1755 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1756 tegra_pmc_writel(value, PMC_CNTRL); 1757 1758 value = tegra_pmc_readl(PMC_CNTRL); 1759 1760 if (pmc->sysclkreq_high) 1761 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 1762 else 1763 value |= PMC_CNTRL_SYSCLK_POLARITY; 1764 1765 /* configure the output polarity while the request is tristated */ 1766 tegra_pmc_writel(value, PMC_CNTRL); 1767 1768 /* now enable the request */ 1769 value = tegra_pmc_readl(PMC_CNTRL); 1770 value |= PMC_CNTRL_SYSCLK_OE; 1771 tegra_pmc_writel(value, PMC_CNTRL); 1772 } 1773 1774 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1775 struct device_node *np, 1776 bool invert) 1777 { 1778 u32 value; 1779 1780 value = tegra_pmc_readl(PMC_CNTRL); 1781 1782 if (invert) 1783 value |= PMC_CNTRL_INTR_POLARITY; 1784 else 1785 value &= ~PMC_CNTRL_INTR_POLARITY; 1786 1787 tegra_pmc_writel(value, PMC_CNTRL); 1788 } 1789 1790 static const struct tegra_pmc_soc tegra20_pmc_soc = { 1791 .num_powergates = ARRAY_SIZE(tegra20_powergates), 1792 .powergates = tegra20_powergates, 1793 .num_cpu_powergates = 0, 1794 .cpu_powergates = NULL, 1795 .has_tsense_reset = false, 1796 .has_gpu_clamps = false, 1797 .num_io_pads = 0, 1798 .io_pads = NULL, 1799 .num_pin_descs = 0, 1800 .pin_descs = NULL, 1801 .regs = &tegra20_pmc_regs, 1802 .init = tegra20_pmc_init, 1803 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1804 .reset_sources = NULL, 1805 .num_reset_sources = 0, 1806 .reset_levels = NULL, 1807 .num_reset_levels = 0, 1808 }; 1809 1810 static const char * const tegra30_powergates[] = { 1811 [TEGRA_POWERGATE_CPU] = "cpu0", 1812 [TEGRA_POWERGATE_3D] = "3d0", 1813 [TEGRA_POWERGATE_VENC] = "venc", 1814 [TEGRA_POWERGATE_VDEC] = "vdec", 1815 [TEGRA_POWERGATE_PCIE] = "pcie", 1816 [TEGRA_POWERGATE_L2] = "l2", 1817 [TEGRA_POWERGATE_MPE] = "mpe", 1818 [TEGRA_POWERGATE_HEG] = "heg", 1819 [TEGRA_POWERGATE_SATA] = "sata", 1820 [TEGRA_POWERGATE_CPU1] = "cpu1", 1821 [TEGRA_POWERGATE_CPU2] = "cpu2", 1822 [TEGRA_POWERGATE_CPU3] = "cpu3", 1823 [TEGRA_POWERGATE_CELP] = "celp", 1824 [TEGRA_POWERGATE_3D1] = "3d1", 1825 }; 1826 1827 static const u8 tegra30_cpu_powergates[] = { 1828 TEGRA_POWERGATE_CPU, 1829 TEGRA_POWERGATE_CPU1, 1830 TEGRA_POWERGATE_CPU2, 1831 TEGRA_POWERGATE_CPU3, 1832 }; 1833 1834 static const struct tegra_pmc_soc tegra30_pmc_soc = { 1835 .num_powergates = ARRAY_SIZE(tegra30_powergates), 1836 .powergates = tegra30_powergates, 1837 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 1838 .cpu_powergates = tegra30_cpu_powergates, 1839 .has_tsense_reset = true, 1840 .has_gpu_clamps = false, 1841 .has_impl_33v_pwr = false, 1842 .num_io_pads = 0, 1843 .io_pads = NULL, 1844 .num_pin_descs = 0, 1845 .pin_descs = NULL, 1846 .regs = &tegra20_pmc_regs, 1847 .init = tegra20_pmc_init, 1848 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1849 .reset_sources = tegra30_reset_sources, 1850 .num_reset_sources = 5, 1851 .reset_levels = NULL, 1852 .num_reset_levels = 0, 1853 }; 1854 1855 static const char * const tegra114_powergates[] = { 1856 [TEGRA_POWERGATE_CPU] = "crail", 1857 [TEGRA_POWERGATE_3D] = "3d", 1858 [TEGRA_POWERGATE_VENC] = "venc", 1859 [TEGRA_POWERGATE_VDEC] = "vdec", 1860 [TEGRA_POWERGATE_MPE] = "mpe", 1861 [TEGRA_POWERGATE_HEG] = "heg", 1862 [TEGRA_POWERGATE_CPU1] = "cpu1", 1863 [TEGRA_POWERGATE_CPU2] = "cpu2", 1864 [TEGRA_POWERGATE_CPU3] = "cpu3", 1865 [TEGRA_POWERGATE_CELP] = "celp", 1866 [TEGRA_POWERGATE_CPU0] = "cpu0", 1867 [TEGRA_POWERGATE_C0NC] = "c0nc", 1868 [TEGRA_POWERGATE_C1NC] = "c1nc", 1869 [TEGRA_POWERGATE_DIS] = "dis", 1870 [TEGRA_POWERGATE_DISB] = "disb", 1871 [TEGRA_POWERGATE_XUSBA] = "xusba", 1872 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1873 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1874 }; 1875 1876 static const u8 tegra114_cpu_powergates[] = { 1877 TEGRA_POWERGATE_CPU0, 1878 TEGRA_POWERGATE_CPU1, 1879 TEGRA_POWERGATE_CPU2, 1880 TEGRA_POWERGATE_CPU3, 1881 }; 1882 1883 static const struct tegra_pmc_soc tegra114_pmc_soc = { 1884 .num_powergates = ARRAY_SIZE(tegra114_powergates), 1885 .powergates = tegra114_powergates, 1886 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 1887 .cpu_powergates = tegra114_cpu_powergates, 1888 .has_tsense_reset = true, 1889 .has_gpu_clamps = false, 1890 .has_impl_33v_pwr = false, 1891 .num_io_pads = 0, 1892 .io_pads = NULL, 1893 .num_pin_descs = 0, 1894 .pin_descs = NULL, 1895 .regs = &tegra20_pmc_regs, 1896 .init = tegra20_pmc_init, 1897 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1898 .reset_sources = tegra30_reset_sources, 1899 .num_reset_sources = 5, 1900 .reset_levels = NULL, 1901 .num_reset_levels = 0, 1902 }; 1903 1904 static const char * const tegra124_powergates[] = { 1905 [TEGRA_POWERGATE_CPU] = "crail", 1906 [TEGRA_POWERGATE_3D] = "3d", 1907 [TEGRA_POWERGATE_VENC] = "venc", 1908 [TEGRA_POWERGATE_PCIE] = "pcie", 1909 [TEGRA_POWERGATE_VDEC] = "vdec", 1910 [TEGRA_POWERGATE_MPE] = "mpe", 1911 [TEGRA_POWERGATE_HEG] = "heg", 1912 [TEGRA_POWERGATE_SATA] = "sata", 1913 [TEGRA_POWERGATE_CPU1] = "cpu1", 1914 [TEGRA_POWERGATE_CPU2] = "cpu2", 1915 [TEGRA_POWERGATE_CPU3] = "cpu3", 1916 [TEGRA_POWERGATE_CELP] = "celp", 1917 [TEGRA_POWERGATE_CPU0] = "cpu0", 1918 [TEGRA_POWERGATE_C0NC] = "c0nc", 1919 [TEGRA_POWERGATE_C1NC] = "c1nc", 1920 [TEGRA_POWERGATE_SOR] = "sor", 1921 [TEGRA_POWERGATE_DIS] = "dis", 1922 [TEGRA_POWERGATE_DISB] = "disb", 1923 [TEGRA_POWERGATE_XUSBA] = "xusba", 1924 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1925 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1926 [TEGRA_POWERGATE_VIC] = "vic", 1927 [TEGRA_POWERGATE_IRAM] = "iram", 1928 }; 1929 1930 static const u8 tegra124_cpu_powergates[] = { 1931 TEGRA_POWERGATE_CPU0, 1932 TEGRA_POWERGATE_CPU1, 1933 TEGRA_POWERGATE_CPU2, 1934 TEGRA_POWERGATE_CPU3, 1935 }; 1936 1937 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ 1938 ((struct tegra_io_pad_soc) { \ 1939 .id = (_id), \ 1940 .dpd = (_dpd), \ 1941 .voltage = (_voltage), \ 1942 .name = (_name), \ 1943 }) 1944 1945 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ 1946 ((struct pinctrl_pin_desc) { \ 1947 .number = (_id), \ 1948 .name = (_name) \ 1949 }) 1950 1951 #define TEGRA124_IO_PAD_TABLE(_pad) \ 1952 /* .id .dpd .voltage .name */ \ 1953 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 1954 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ 1955 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ 1956 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ 1957 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 1958 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ 1959 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ 1960 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 1961 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 1962 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 1963 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 1964 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 1965 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 1966 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ 1967 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 1968 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 1969 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ 1970 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 1971 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 1972 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 1973 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 1974 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ 1975 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ 1976 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ 1977 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ 1978 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 1979 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 1980 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 1981 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 1982 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") 1983 1984 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 1985 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) 1986 }; 1987 1988 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 1989 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 1990 }; 1991 1992 static const struct tegra_pmc_soc tegra124_pmc_soc = { 1993 .num_powergates = ARRAY_SIZE(tegra124_powergates), 1994 .powergates = tegra124_powergates, 1995 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 1996 .cpu_powergates = tegra124_cpu_powergates, 1997 .has_tsense_reset = true, 1998 .has_gpu_clamps = true, 1999 .has_impl_33v_pwr = false, 2000 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 2001 .io_pads = tegra124_io_pads, 2002 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 2003 .pin_descs = tegra124_pin_descs, 2004 .regs = &tegra20_pmc_regs, 2005 .init = tegra20_pmc_init, 2006 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2007 .reset_sources = tegra30_reset_sources, 2008 .num_reset_sources = 5, 2009 .reset_levels = NULL, 2010 .num_reset_levels = 0, 2011 }; 2012 2013 static const char * const tegra210_powergates[] = { 2014 [TEGRA_POWERGATE_CPU] = "crail", 2015 [TEGRA_POWERGATE_3D] = "3d", 2016 [TEGRA_POWERGATE_VENC] = "venc", 2017 [TEGRA_POWERGATE_PCIE] = "pcie", 2018 [TEGRA_POWERGATE_MPE] = "mpe", 2019 [TEGRA_POWERGATE_SATA] = "sata", 2020 [TEGRA_POWERGATE_CPU1] = "cpu1", 2021 [TEGRA_POWERGATE_CPU2] = "cpu2", 2022 [TEGRA_POWERGATE_CPU3] = "cpu3", 2023 [TEGRA_POWERGATE_CPU0] = "cpu0", 2024 [TEGRA_POWERGATE_C0NC] = "c0nc", 2025 [TEGRA_POWERGATE_SOR] = "sor", 2026 [TEGRA_POWERGATE_DIS] = "dis", 2027 [TEGRA_POWERGATE_DISB] = "disb", 2028 [TEGRA_POWERGATE_XUSBA] = "xusba", 2029 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2030 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2031 [TEGRA_POWERGATE_VIC] = "vic", 2032 [TEGRA_POWERGATE_IRAM] = "iram", 2033 [TEGRA_POWERGATE_NVDEC] = "nvdec", 2034 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 2035 [TEGRA_POWERGATE_AUD] = "aud", 2036 [TEGRA_POWERGATE_DFD] = "dfd", 2037 [TEGRA_POWERGATE_VE2] = "ve2", 2038 }; 2039 2040 static const u8 tegra210_cpu_powergates[] = { 2041 TEGRA_POWERGATE_CPU0, 2042 TEGRA_POWERGATE_CPU1, 2043 TEGRA_POWERGATE_CPU2, 2044 TEGRA_POWERGATE_CPU3, 2045 }; 2046 2047 #define TEGRA210_IO_PAD_TABLE(_pad) \ 2048 /* .id .dpd .voltage .name */ \ 2049 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ 2050 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ 2051 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ 2052 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2053 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 2054 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ 2055 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ 2056 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ 2057 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ 2058 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ 2059 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ 2060 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ 2061 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ 2062 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2063 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 2064 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 2065 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 2066 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ 2067 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ 2068 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ 2069 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 2070 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2071 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 2072 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2073 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 2074 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 2075 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2076 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ 2077 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ 2078 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ 2079 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ 2080 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ 2081 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ 2082 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2083 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2084 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2085 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ 2086 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") 2087 2088 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 2089 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) 2090 }; 2091 2092 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 2093 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2094 }; 2095 2096 static const struct tegra_pmc_soc tegra210_pmc_soc = { 2097 .num_powergates = ARRAY_SIZE(tegra210_powergates), 2098 .powergates = tegra210_powergates, 2099 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 2100 .cpu_powergates = tegra210_cpu_powergates, 2101 .has_tsense_reset = true, 2102 .has_gpu_clamps = true, 2103 .has_impl_33v_pwr = false, 2104 .needs_mbist_war = true, 2105 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 2106 .io_pads = tegra210_io_pads, 2107 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 2108 .pin_descs = tegra210_pin_descs, 2109 .regs = &tegra20_pmc_regs, 2110 .init = tegra20_pmc_init, 2111 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2112 .reset_sources = tegra30_reset_sources, 2113 .num_reset_sources = 5, 2114 .reset_levels = NULL, 2115 .num_reset_levels = 0, 2116 }; 2117 2118 #define TEGRA186_IO_PAD_TABLE(_pad) \ 2119 /* .id .dpd .voltage .name */ \ 2120 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2121 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 2122 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2123 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2124 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 2125 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 2126 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2127 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 2128 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2129 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2130 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2131 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ 2132 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 2133 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 2134 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2135 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 2136 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 2137 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 2138 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 2139 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ 2140 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 2141 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 2142 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ 2143 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ 2144 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ 2145 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 2146 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 2147 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 2148 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 2149 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 2150 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 2151 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ 2152 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 2153 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 2154 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 2155 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 2156 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 2157 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 2158 2159 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 2160 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) 2161 }; 2162 2163 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 2164 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2165 }; 2166 2167 static const struct tegra_pmc_regs tegra186_pmc_regs = { 2168 .scratch0 = 0x2000, 2169 .dpd_req = 0x74, 2170 .dpd_status = 0x78, 2171 .dpd2_req = 0x7c, 2172 .dpd2_status = 0x80, 2173 .rst_status = 0x70, 2174 .rst_source_shift = 0x2, 2175 .rst_source_mask = 0x3C, 2176 .rst_level_shift = 0x0, 2177 .rst_level_mask = 0x3, 2178 }; 2179 2180 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 2181 struct device_node *np, 2182 bool invert) 2183 { 2184 struct resource regs; 2185 void __iomem *wake; 2186 u32 value; 2187 int index; 2188 2189 index = of_property_match_string(np, "reg-names", "wake"); 2190 if (index < 0) { 2191 pr_err("failed to find PMC wake registers\n"); 2192 return; 2193 } 2194 2195 of_address_to_resource(np, index, ®s); 2196 2197 wake = ioremap_nocache(regs.start, resource_size(®s)); 2198 if (!wake) { 2199 pr_err("failed to map PMC wake registers\n"); 2200 return; 2201 } 2202 2203 value = readl(wake + WAKE_AOWAKE_CTRL); 2204 2205 if (invert) 2206 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 2207 else 2208 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 2209 2210 writel(value, wake + WAKE_AOWAKE_CTRL); 2211 2212 iounmap(wake); 2213 } 2214 2215 static const struct tegra_pmc_soc tegra186_pmc_soc = { 2216 .num_powergates = 0, 2217 .powergates = NULL, 2218 .num_cpu_powergates = 0, 2219 .cpu_powergates = NULL, 2220 .has_tsense_reset = false, 2221 .has_gpu_clamps = false, 2222 .has_impl_33v_pwr = true, 2223 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 2224 .io_pads = tegra186_io_pads, 2225 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 2226 .pin_descs = tegra186_pin_descs, 2227 .regs = &tegra186_pmc_regs, 2228 .init = NULL, 2229 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 2230 .reset_sources = tegra186_reset_sources, 2231 .num_reset_sources = 14, 2232 .reset_levels = tegra186_reset_levels, 2233 .num_reset_levels = 3, 2234 }; 2235 2236 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 2237 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 2238 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 2239 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 2240 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, 2241 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, 2242 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 2243 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, 2244 { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX }, 2245 { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX }, 2246 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX }, 2247 { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX }, 2248 { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX }, 2249 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 2250 { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX }, 2251 { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX }, 2252 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 2253 { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX }, 2254 { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX }, 2255 { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX }, 2256 { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX }, 2257 { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX }, 2258 { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX }, 2259 { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX }, 2260 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, 2261 { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX }, 2262 { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX }, 2263 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, 2264 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, 2265 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 2266 { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX }, 2267 { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX }, 2268 { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX }, 2269 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, 2270 { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX }, 2271 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, 2272 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, 2273 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, 2274 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, 2275 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, 2276 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, 2277 { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX }, 2278 { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX }, 2279 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, 2280 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, 2281 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, 2282 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, 2283 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, 2284 }; 2285 2286 static const struct tegra_pmc_soc tegra194_pmc_soc = { 2287 .num_powergates = 0, 2288 .powergates = NULL, 2289 .num_cpu_powergates = 0, 2290 .cpu_powergates = NULL, 2291 .has_tsense_reset = false, 2292 .has_gpu_clamps = false, 2293 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 2294 .io_pads = tegra194_io_pads, 2295 .regs = &tegra186_pmc_regs, 2296 .init = NULL, 2297 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 2298 }; 2299 2300 static const struct of_device_id tegra_pmc_match[] = { 2301 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 2302 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 2303 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 2304 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 2305 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 2306 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 2307 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 2308 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 2309 { } 2310 }; 2311 2312 static struct platform_driver tegra_pmc_driver = { 2313 .driver = { 2314 .name = "tegra-pmc", 2315 .suppress_bind_attrs = true, 2316 .of_match_table = tegra_pmc_match, 2317 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 2318 .pm = &tegra_pmc_pm_ops, 2319 #endif 2320 }, 2321 .probe = tegra_pmc_probe, 2322 }; 2323 builtin_platform_driver(tegra_pmc_driver); 2324 2325 /* 2326 * Early initialization to allow access to registers in the very early boot 2327 * process. 2328 */ 2329 static int __init tegra_pmc_early_init(void) 2330 { 2331 const struct of_device_id *match; 2332 struct device_node *np; 2333 struct resource regs; 2334 bool invert; 2335 2336 mutex_init(&pmc->powergates_lock); 2337 2338 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 2339 if (!np) { 2340 /* 2341 * Fall back to legacy initialization for 32-bit ARM only. All 2342 * 64-bit ARM device tree files for Tegra are required to have 2343 * a PMC node. 2344 * 2345 * This is for backwards-compatibility with old device trees 2346 * that didn't contain a PMC node. Note that in this case the 2347 * SoC data can't be matched and therefore powergating is 2348 * disabled. 2349 */ 2350 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 2351 pr_warn("DT node not found, powergating disabled\n"); 2352 2353 regs.start = 0x7000e400; 2354 regs.end = 0x7000e7ff; 2355 regs.flags = IORESOURCE_MEM; 2356 2357 pr_warn("Using memory region %pR\n", ®s); 2358 } else { 2359 /* 2360 * At this point we're not running on Tegra, so play 2361 * nice with multi-platform kernels. 2362 */ 2363 return 0; 2364 } 2365 } else { 2366 /* 2367 * Extract information from the device tree if we've found a 2368 * matching node. 2369 */ 2370 if (of_address_to_resource(np, 0, ®s) < 0) { 2371 pr_err("failed to get PMC registers\n"); 2372 of_node_put(np); 2373 return -ENXIO; 2374 } 2375 } 2376 2377 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 2378 if (!pmc->base) { 2379 pr_err("failed to map PMC registers\n"); 2380 of_node_put(np); 2381 return -ENXIO; 2382 } 2383 2384 if (np) { 2385 pmc->soc = match->data; 2386 2387 tegra_powergate_init(pmc, np); 2388 2389 /* 2390 * Invert the interrupt polarity if a PMC device tree node 2391 * exists and contains the nvidia,invert-interrupt property. 2392 */ 2393 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 2394 2395 pmc->soc->setup_irq_polarity(pmc, np, invert); 2396 2397 of_node_put(np); 2398 } 2399 2400 return 0; 2401 } 2402 early_initcall(tegra_pmc_early_init); 2403