pinctrl-rockchip.c (c971af25cda94afe71617790826a86253e88eab0) pinctrl-rockchip.c (be786ac5a6c4bf4ef3e4c569a045d302c1e60fe6)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Pinctrl driver for Rockchip SoCs
4 *
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18#include <linux/init.h>
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Pinctrl driver for Rockchip SoCs
4 *
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/bitops.h>
22#include <linux/gpio/driver.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/bitops.h>
23#include <linux/gpio/driver.h>
24#include <linux/of_device.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/pinctrl/machine.h>
26#include <linux/pinctrl/pinconf.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/pinctrl/pinconf-generic.h>
30#include <linux/irqchip/chained_irq.h>

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3428 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3429
3430 /*
3431 * Linux assumes that all interrupts start out disabled/masked.
3432 * Our driver only uses the concept of masked and always keeps
3433 * things enabled, so for us that's all masked and all enabled.
3434 */
3435 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/pinctrl/machine.h>
28#include <linux/pinctrl/pinconf.h>
29#include <linux/pinctrl/pinctrl.h>
30#include <linux/pinctrl/pinmux.h>
31#include <linux/pinctrl/pinconf-generic.h>
32#include <linux/irqchip/chained_irq.h>

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3430 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
3431
3432 /*
3433 * Linux assumes that all interrupts start out disabled/masked.
3434 * Our driver only uses the concept of masked and always keeps
3435 * things enabled, so for us that's all masked and all enabled.
3436 */
3437 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
3438 writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI);
3436 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3437 gc->mask_cache = 0xffffffff;
3438
3439 irq_set_chained_handler_and_data(bank->irq,
3440 rockchip_irq_demux, bank);
3441 clk_disable(bank->clk);
3442 }
3443

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3722 }
3723
3724 return 0;
3725}
3726
3727static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3728{
3729 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3439 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
3440 gc->mask_cache = 0xffffffff;
3441
3442 irq_set_chained_handler_and_data(bank->irq,
3443 rockchip_irq_demux, bank);
3444 clk_disable(bank->clk);
3445 }
3446

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3725 }
3726
3727 return 0;
3728}
3729
3730static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3731{
3732 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3730 int ret;
3733 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3734 rk3288_grf_gpio6c_iomux |
3735 GPIO6C6_SEL_WRITE_ENABLE);
3731
3736
3732 if (info->ctrl->type == RK3288) {
3733 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3734 rk3288_grf_gpio6c_iomux |
3735 GPIO6C6_SEL_WRITE_ENABLE);
3736 if (ret)
3737 return ret;
3738 }
3737 if (ret)
3738 return ret;
3739
3740 return pinctrl_force_default(info->pctl_dev);
3741}
3742
3743static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3744 rockchip_pinctrl_resume);
3745
3746static int rockchip_pinctrl_probe(struct platform_device *pdev)

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4254 },
4255};
4256
4257static int __init rockchip_pinctrl_drv_register(void)
4258{
4259 return platform_driver_register(&rockchip_pinctrl_driver);
4260}
4261postcore_initcall(rockchip_pinctrl_drv_register);
3739
3740 return pinctrl_force_default(info->pctl_dev);
3741}
3742
3743static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3744 rockchip_pinctrl_resume);
3745
3746static int rockchip_pinctrl_probe(struct platform_device *pdev)

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4254 },
4255};
4256
4257static int __init rockchip_pinctrl_drv_register(void)
4258{
4259 return platform_driver_register(&rockchip_pinctrl_driver);
4260}
4261postcore_initcall(rockchip_pinctrl_drv_register);
4262
4263static void __exit rockchip_pinctrl_drv_unregister(void)
4264{
4265 platform_driver_unregister(&rockchip_pinctrl_driver);
4266}
4267module_exit(rockchip_pinctrl_drv_unregister);
4268
4269MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
4270MODULE_LICENSE("GPL");
4271MODULE_ALIAS("platform:pinctrl-rockchip");
4272MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);