1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pinctrl driver for Rockchip SoCs 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/io.h> 22 #include <linux/bitops.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/of_device.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/pinctrl/machine.h> 28 #include <linux/pinctrl/pinconf.h> 29 #include <linux/pinctrl/pinctrl.h> 30 #include <linux/pinctrl/pinmux.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/irqchip/chained_irq.h> 33 #include <linux/clk.h> 34 #include <linux/regmap.h> 35 #include <linux/mfd/syscon.h> 36 #include <dt-bindings/pinctrl/rockchip.h> 37 38 #include "core.h" 39 #include "pinconf.h" 40 41 /* GPIO control registers */ 42 #define GPIO_SWPORT_DR 0x00 43 #define GPIO_SWPORT_DDR 0x04 44 #define GPIO_INTEN 0x30 45 #define GPIO_INTMASK 0x34 46 #define GPIO_INTTYPE_LEVEL 0x38 47 #define GPIO_INT_POLARITY 0x3c 48 #define GPIO_INT_STATUS 0x40 49 #define GPIO_INT_RAWSTATUS 0x44 50 #define GPIO_DEBOUNCE 0x48 51 #define GPIO_PORTS_EOI 0x4c 52 #define GPIO_EXT_PORT 0x50 53 #define GPIO_LS_SYNC 0x60 54 55 enum rockchip_pinctrl_type { 56 PX30, 57 RV1108, 58 RK2928, 59 RK3066B, 60 RK3128, 61 RK3188, 62 RK3288, 63 RK3308, 64 RK3368, 65 RK3399, 66 }; 67 68 /* 69 * Encode variants of iomux registers into a type variable 70 */ 71 #define IOMUX_GPIO_ONLY BIT(0) 72 #define IOMUX_WIDTH_4BIT BIT(1) 73 #define IOMUX_SOURCE_PMU BIT(2) 74 #define IOMUX_UNROUTED BIT(3) 75 #define IOMUX_WIDTH_3BIT BIT(4) 76 #define IOMUX_WIDTH_2BIT BIT(5) 77 78 /** 79 * struct rockchip_iomux 80 * @type: iomux variant using IOMUX_* constants 81 * @offset: if initialized to -1 it will be autocalculated, by specifying 82 * an initial offset value the relevant source offset can be reset 83 * to a new value for autocalculating the following iomux registers. 84 */ 85 struct rockchip_iomux { 86 int type; 87 int offset; 88 }; 89 90 /* 91 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 92 */ 93 enum rockchip_pin_drv_type { 94 DRV_TYPE_IO_DEFAULT = 0, 95 DRV_TYPE_IO_1V8_OR_3V0, 96 DRV_TYPE_IO_1V8_ONLY, 97 DRV_TYPE_IO_1V8_3V0_AUTO, 98 DRV_TYPE_IO_3V3_ONLY, 99 DRV_TYPE_MAX 100 }; 101 102 /* 103 * enum type index corresponding to rockchip_pull_list arrays index. 104 */ 105 enum rockchip_pin_pull_type { 106 PULL_TYPE_IO_DEFAULT = 0, 107 PULL_TYPE_IO_1V8_ONLY, 108 PULL_TYPE_MAX 109 }; 110 111 /** 112 * struct rockchip_drv 113 * @drv_type: drive strength variant using rockchip_perpin_drv_type 114 * @offset: if initialized to -1 it will be autocalculated, by specifying 115 * an initial offset value the relevant source offset can be reset 116 * to a new value for autocalculating the following drive strength 117 * registers. if used chips own cal_drv func instead to calculate 118 * registers offset, the variant could be ignored. 119 */ 120 struct rockchip_drv { 121 enum rockchip_pin_drv_type drv_type; 122 int offset; 123 }; 124 125 /** 126 * struct rockchip_pin_bank 127 * @reg_base: register base of the gpio bank 128 * @regmap_pull: optional separate register for additional pull settings 129 * @clk: clock of the gpio bank 130 * @irq: interrupt of the gpio bank 131 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 132 * @pin_base: first pin number 133 * @nr_pins: number of pins in this bank 134 * @name: name of the bank 135 * @bank_num: number of the bank, to account for holes 136 * @iomux: array describing the 4 iomux sources of the bank 137 * @drv: array describing the 4 drive strength sources of the bank 138 * @pull_type: array describing the 4 pull type sources of the bank 139 * @valid: is all necessary information present 140 * @of_node: dt node of this bank 141 * @drvdata: common pinctrl basedata 142 * @domain: irqdomain of the gpio bank 143 * @gpio_chip: gpiolib chip 144 * @grange: gpio range 145 * @slock: spinlock for the gpio bank 146 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode 147 * @recalced_mask: bit mask to indicate a need to recalulate the mask 148 * @route_mask: bits describing the routing pins of per bank 149 */ 150 struct rockchip_pin_bank { 151 void __iomem *reg_base; 152 struct regmap *regmap_pull; 153 struct clk *clk; 154 int irq; 155 u32 saved_masks; 156 u32 pin_base; 157 u8 nr_pins; 158 char *name; 159 u8 bank_num; 160 struct rockchip_iomux iomux[4]; 161 struct rockchip_drv drv[4]; 162 enum rockchip_pin_pull_type pull_type[4]; 163 bool valid; 164 struct device_node *of_node; 165 struct rockchip_pinctrl *drvdata; 166 struct irq_domain *domain; 167 struct gpio_chip gpio_chip; 168 struct pinctrl_gpio_range grange; 169 raw_spinlock_t slock; 170 u32 toggle_edge_mode; 171 u32 recalced_mask; 172 u32 route_mask; 173 }; 174 175 #define PIN_BANK(id, pins, label) \ 176 { \ 177 .bank_num = id, \ 178 .nr_pins = pins, \ 179 .name = label, \ 180 .iomux = { \ 181 { .offset = -1 }, \ 182 { .offset = -1 }, \ 183 { .offset = -1 }, \ 184 { .offset = -1 }, \ 185 }, \ 186 } 187 188 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 189 { \ 190 .bank_num = id, \ 191 .nr_pins = pins, \ 192 .name = label, \ 193 .iomux = { \ 194 { .type = iom0, .offset = -1 }, \ 195 { .type = iom1, .offset = -1 }, \ 196 { .type = iom2, .offset = -1 }, \ 197 { .type = iom3, .offset = -1 }, \ 198 }, \ 199 } 200 201 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 202 { \ 203 .bank_num = id, \ 204 .nr_pins = pins, \ 205 .name = label, \ 206 .iomux = { \ 207 { .offset = -1 }, \ 208 { .offset = -1 }, \ 209 { .offset = -1 }, \ 210 { .offset = -1 }, \ 211 }, \ 212 .drv = { \ 213 { .drv_type = type0, .offset = -1 }, \ 214 { .drv_type = type1, .offset = -1 }, \ 215 { .drv_type = type2, .offset = -1 }, \ 216 { .drv_type = type3, .offset = -1 }, \ 217 }, \ 218 } 219 220 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 221 drv2, drv3, pull0, pull1, \ 222 pull2, pull3) \ 223 { \ 224 .bank_num = id, \ 225 .nr_pins = pins, \ 226 .name = label, \ 227 .iomux = { \ 228 { .offset = -1 }, \ 229 { .offset = -1 }, \ 230 { .offset = -1 }, \ 231 { .offset = -1 }, \ 232 }, \ 233 .drv = { \ 234 { .drv_type = drv0, .offset = -1 }, \ 235 { .drv_type = drv1, .offset = -1 }, \ 236 { .drv_type = drv2, .offset = -1 }, \ 237 { .drv_type = drv3, .offset = -1 }, \ 238 }, \ 239 .pull_type[0] = pull0, \ 240 .pull_type[1] = pull1, \ 241 .pull_type[2] = pull2, \ 242 .pull_type[3] = pull3, \ 243 } 244 245 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 246 iom2, iom3, drv0, drv1, drv2, \ 247 drv3, offset0, offset1, \ 248 offset2, offset3) \ 249 { \ 250 .bank_num = id, \ 251 .nr_pins = pins, \ 252 .name = label, \ 253 .iomux = { \ 254 { .type = iom0, .offset = -1 }, \ 255 { .type = iom1, .offset = -1 }, \ 256 { .type = iom2, .offset = -1 }, \ 257 { .type = iom3, .offset = -1 }, \ 258 }, \ 259 .drv = { \ 260 { .drv_type = drv0, .offset = offset0 }, \ 261 { .drv_type = drv1, .offset = offset1 }, \ 262 { .drv_type = drv2, .offset = offset2 }, \ 263 { .drv_type = drv3, .offset = offset3 }, \ 264 }, \ 265 } 266 267 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 268 label, iom0, iom1, iom2, \ 269 iom3, drv0, drv1, drv2, \ 270 drv3, offset0, offset1, \ 271 offset2, offset3, pull0, \ 272 pull1, pull2, pull3) \ 273 { \ 274 .bank_num = id, \ 275 .nr_pins = pins, \ 276 .name = label, \ 277 .iomux = { \ 278 { .type = iom0, .offset = -1 }, \ 279 { .type = iom1, .offset = -1 }, \ 280 { .type = iom2, .offset = -1 }, \ 281 { .type = iom3, .offset = -1 }, \ 282 }, \ 283 .drv = { \ 284 { .drv_type = drv0, .offset = offset0 }, \ 285 { .drv_type = drv1, .offset = offset1 }, \ 286 { .drv_type = drv2, .offset = offset2 }, \ 287 { .drv_type = drv3, .offset = offset3 }, \ 288 }, \ 289 .pull_type[0] = pull0, \ 290 .pull_type[1] = pull1, \ 291 .pull_type[2] = pull2, \ 292 .pull_type[3] = pull3, \ 293 } 294 295 /** 296 * struct rockchip_mux_recalced_data: represent a pin iomux data. 297 * @num: bank number. 298 * @pin: pin number. 299 * @bit: index at register. 300 * @reg: register offset. 301 * @mask: mask bit 302 */ 303 struct rockchip_mux_recalced_data { 304 u8 num; 305 u8 pin; 306 u32 reg; 307 u8 bit; 308 u8 mask; 309 }; 310 311 enum rockchip_mux_route_location { 312 ROCKCHIP_ROUTE_SAME = 0, 313 ROCKCHIP_ROUTE_PMU, 314 ROCKCHIP_ROUTE_GRF, 315 }; 316 317 /** 318 * struct rockchip_mux_recalced_data: represent a pin iomux data. 319 * @bank_num: bank number. 320 * @pin: index at register or used to calc index. 321 * @func: the min pin. 322 * @route_location: the mux route location (same, pmu, grf). 323 * @route_offset: the max pin. 324 * @route_val: the register offset. 325 */ 326 struct rockchip_mux_route_data { 327 u8 bank_num; 328 u8 pin; 329 u8 func; 330 enum rockchip_mux_route_location route_location; 331 u32 route_offset; 332 u32 route_val; 333 }; 334 335 struct rockchip_pin_ctrl { 336 struct rockchip_pin_bank *pin_banks; 337 u32 nr_banks; 338 u32 nr_pins; 339 char *label; 340 enum rockchip_pinctrl_type type; 341 int grf_mux_offset; 342 int pmu_mux_offset; 343 int grf_drv_offset; 344 int pmu_drv_offset; 345 struct rockchip_mux_recalced_data *iomux_recalced; 346 u32 niomux_recalced; 347 struct rockchip_mux_route_data *iomux_routes; 348 u32 niomux_routes; 349 350 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 351 int pin_num, struct regmap **regmap, 352 int *reg, u8 *bit); 353 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 354 int pin_num, struct regmap **regmap, 355 int *reg, u8 *bit); 356 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 357 int pin_num, struct regmap **regmap, 358 int *reg, u8 *bit); 359 }; 360 361 struct rockchip_pin_config { 362 unsigned int func; 363 unsigned long *configs; 364 unsigned int nconfigs; 365 }; 366 367 /** 368 * struct rockchip_pin_group: represent group of pins of a pinmux function. 369 * @name: name of the pin group, used to lookup the group. 370 * @pins: the pins included in this group. 371 * @npins: number of pins included in this group. 372 * @data: local pin configuration 373 */ 374 struct rockchip_pin_group { 375 const char *name; 376 unsigned int npins; 377 unsigned int *pins; 378 struct rockchip_pin_config *data; 379 }; 380 381 /** 382 * struct rockchip_pmx_func: represent a pin function. 383 * @name: name of the pin function, used to lookup the function. 384 * @groups: one or more names of pin groups that provide this function. 385 * @ngroups: number of groups included in @groups. 386 */ 387 struct rockchip_pmx_func { 388 const char *name; 389 const char **groups; 390 u8 ngroups; 391 }; 392 393 struct rockchip_pinctrl { 394 struct regmap *regmap_base; 395 int reg_size; 396 struct regmap *regmap_pull; 397 struct regmap *regmap_pmu; 398 struct device *dev; 399 struct rockchip_pin_ctrl *ctrl; 400 struct pinctrl_desc pctl; 401 struct pinctrl_dev *pctl_dev; 402 struct rockchip_pin_group *groups; 403 unsigned int ngroups; 404 struct rockchip_pmx_func *functions; 405 unsigned int nfunctions; 406 }; 407 408 static struct regmap_config rockchip_regmap_config = { 409 .reg_bits = 32, 410 .val_bits = 32, 411 .reg_stride = 4, 412 }; 413 414 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 415 const struct rockchip_pinctrl *info, 416 const char *name) 417 { 418 int i; 419 420 for (i = 0; i < info->ngroups; i++) { 421 if (!strcmp(info->groups[i].name, name)) 422 return &info->groups[i]; 423 } 424 425 return NULL; 426 } 427 428 /* 429 * given a pin number that is local to a pin controller, find out the pin bank 430 * and the register base of the pin bank. 431 */ 432 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 433 unsigned pin) 434 { 435 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 436 437 while (pin >= (b->pin_base + b->nr_pins)) 438 b++; 439 440 return b; 441 } 442 443 static struct rockchip_pin_bank *bank_num_to_bank( 444 struct rockchip_pinctrl *info, 445 unsigned num) 446 { 447 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 448 int i; 449 450 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 451 if (b->bank_num == num) 452 return b; 453 } 454 455 return ERR_PTR(-EINVAL); 456 } 457 458 /* 459 * Pinctrl_ops handling 460 */ 461 462 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 463 { 464 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 465 466 return info->ngroups; 467 } 468 469 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 470 unsigned selector) 471 { 472 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 473 474 return info->groups[selector].name; 475 } 476 477 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 478 unsigned selector, const unsigned **pins, 479 unsigned *npins) 480 { 481 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 482 483 if (selector >= info->ngroups) 484 return -EINVAL; 485 486 *pins = info->groups[selector].pins; 487 *npins = info->groups[selector].npins; 488 489 return 0; 490 } 491 492 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 493 struct device_node *np, 494 struct pinctrl_map **map, unsigned *num_maps) 495 { 496 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 497 const struct rockchip_pin_group *grp; 498 struct pinctrl_map *new_map; 499 struct device_node *parent; 500 int map_num = 1; 501 int i; 502 503 /* 504 * first find the group of this node and check if we need to create 505 * config maps for pins 506 */ 507 grp = pinctrl_name_to_group(info, np->name); 508 if (!grp) { 509 dev_err(info->dev, "unable to find group for node %pOFn\n", 510 np); 511 return -EINVAL; 512 } 513 514 map_num += grp->npins; 515 516 new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); 517 if (!new_map) 518 return -ENOMEM; 519 520 *map = new_map; 521 *num_maps = map_num; 522 523 /* create mux map */ 524 parent = of_get_parent(np); 525 if (!parent) { 526 kfree(new_map); 527 return -EINVAL; 528 } 529 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 530 new_map[0].data.mux.function = parent->name; 531 new_map[0].data.mux.group = np->name; 532 of_node_put(parent); 533 534 /* create config map */ 535 new_map++; 536 for (i = 0; i < grp->npins; i++) { 537 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 538 new_map[i].data.configs.group_or_pin = 539 pin_get_name(pctldev, grp->pins[i]); 540 new_map[i].data.configs.configs = grp->data[i].configs; 541 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 542 } 543 544 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 545 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 546 547 return 0; 548 } 549 550 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 551 struct pinctrl_map *map, unsigned num_maps) 552 { 553 kfree(map); 554 } 555 556 static const struct pinctrl_ops rockchip_pctrl_ops = { 557 .get_groups_count = rockchip_get_groups_count, 558 .get_group_name = rockchip_get_group_name, 559 .get_group_pins = rockchip_get_group_pins, 560 .dt_node_to_map = rockchip_dt_node_to_map, 561 .dt_free_map = rockchip_dt_free_map, 562 }; 563 564 /* 565 * Hardware access 566 */ 567 568 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 569 { 570 .num = 1, 571 .pin = 0, 572 .reg = 0x418, 573 .bit = 0, 574 .mask = 0x3 575 }, { 576 .num = 1, 577 .pin = 1, 578 .reg = 0x418, 579 .bit = 2, 580 .mask = 0x3 581 }, { 582 .num = 1, 583 .pin = 2, 584 .reg = 0x418, 585 .bit = 4, 586 .mask = 0x3 587 }, { 588 .num = 1, 589 .pin = 3, 590 .reg = 0x418, 591 .bit = 6, 592 .mask = 0x3 593 }, { 594 .num = 1, 595 .pin = 4, 596 .reg = 0x418, 597 .bit = 8, 598 .mask = 0x3 599 }, { 600 .num = 1, 601 .pin = 5, 602 .reg = 0x418, 603 .bit = 10, 604 .mask = 0x3 605 }, { 606 .num = 1, 607 .pin = 6, 608 .reg = 0x418, 609 .bit = 12, 610 .mask = 0x3 611 }, { 612 .num = 1, 613 .pin = 7, 614 .reg = 0x418, 615 .bit = 14, 616 .mask = 0x3 617 }, { 618 .num = 1, 619 .pin = 8, 620 .reg = 0x41c, 621 .bit = 0, 622 .mask = 0x3 623 }, { 624 .num = 1, 625 .pin = 9, 626 .reg = 0x41c, 627 .bit = 2, 628 .mask = 0x3 629 }, 630 }; 631 632 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 633 { 634 .num = 2, 635 .pin = 20, 636 .reg = 0xe8, 637 .bit = 0, 638 .mask = 0x7 639 }, { 640 .num = 2, 641 .pin = 21, 642 .reg = 0xe8, 643 .bit = 4, 644 .mask = 0x7 645 }, { 646 .num = 2, 647 .pin = 22, 648 .reg = 0xe8, 649 .bit = 8, 650 .mask = 0x7 651 }, { 652 .num = 2, 653 .pin = 23, 654 .reg = 0xe8, 655 .bit = 12, 656 .mask = 0x7 657 }, { 658 .num = 2, 659 .pin = 24, 660 .reg = 0xd4, 661 .bit = 12, 662 .mask = 0x7 663 }, 664 }; 665 666 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 667 { 668 .num = 1, 669 .pin = 14, 670 .reg = 0x28, 671 .bit = 12, 672 .mask = 0xf 673 }, { 674 .num = 1, 675 .pin = 15, 676 .reg = 0x2c, 677 .bit = 0, 678 .mask = 0x3 679 }, { 680 .num = 1, 681 .pin = 18, 682 .reg = 0x30, 683 .bit = 4, 684 .mask = 0xf 685 }, { 686 .num = 1, 687 .pin = 19, 688 .reg = 0x30, 689 .bit = 8, 690 .mask = 0xf 691 }, { 692 .num = 1, 693 .pin = 20, 694 .reg = 0x30, 695 .bit = 12, 696 .mask = 0xf 697 }, { 698 .num = 1, 699 .pin = 21, 700 .reg = 0x34, 701 .bit = 0, 702 .mask = 0xf 703 }, { 704 .num = 1, 705 .pin = 22, 706 .reg = 0x34, 707 .bit = 4, 708 .mask = 0xf 709 }, { 710 .num = 1, 711 .pin = 23, 712 .reg = 0x34, 713 .bit = 8, 714 .mask = 0xf 715 }, { 716 .num = 3, 717 .pin = 12, 718 .reg = 0x68, 719 .bit = 8, 720 .mask = 0xf 721 }, { 722 .num = 3, 723 .pin = 13, 724 .reg = 0x68, 725 .bit = 12, 726 .mask = 0xf 727 }, { 728 .num = 2, 729 .pin = 2, 730 .reg = 0x608, 731 .bit = 0, 732 .mask = 0x7 733 }, { 734 .num = 2, 735 .pin = 3, 736 .reg = 0x608, 737 .bit = 4, 738 .mask = 0x7 739 }, { 740 .num = 2, 741 .pin = 16, 742 .reg = 0x610, 743 .bit = 8, 744 .mask = 0x7 745 }, { 746 .num = 3, 747 .pin = 10, 748 .reg = 0x610, 749 .bit = 0, 750 .mask = 0x7 751 }, { 752 .num = 3, 753 .pin = 11, 754 .reg = 0x610, 755 .bit = 4, 756 .mask = 0x7 757 }, 758 }; 759 760 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 761 { 762 .num = 2, 763 .pin = 12, 764 .reg = 0x24, 765 .bit = 8, 766 .mask = 0x3 767 }, { 768 .num = 2, 769 .pin = 15, 770 .reg = 0x28, 771 .bit = 0, 772 .mask = 0x7 773 }, { 774 .num = 2, 775 .pin = 23, 776 .reg = 0x30, 777 .bit = 14, 778 .mask = 0x3 779 }, 780 }; 781 782 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 783 int *reg, u8 *bit, int *mask) 784 { 785 struct rockchip_pinctrl *info = bank->drvdata; 786 struct rockchip_pin_ctrl *ctrl = info->ctrl; 787 struct rockchip_mux_recalced_data *data; 788 int i; 789 790 for (i = 0; i < ctrl->niomux_recalced; i++) { 791 data = &ctrl->iomux_recalced[i]; 792 if (data->num == bank->bank_num && 793 data->pin == pin) 794 break; 795 } 796 797 if (i >= ctrl->niomux_recalced) 798 return; 799 800 *reg = data->reg; 801 *mask = data->mask; 802 *bit = data->bit; 803 } 804 805 static struct rockchip_mux_route_data px30_mux_route_data[] = { 806 { 807 /* cif-d2m0 */ 808 .bank_num = 2, 809 .pin = 0, 810 .func = 1, 811 .route_offset = 0x184, 812 .route_val = BIT(16 + 7), 813 }, { 814 /* cif-d2m1 */ 815 .bank_num = 3, 816 .pin = 3, 817 .func = 3, 818 .route_offset = 0x184, 819 .route_val = BIT(16 + 7) | BIT(7), 820 }, { 821 /* pdm-m0 */ 822 .bank_num = 3, 823 .pin = 22, 824 .func = 2, 825 .route_offset = 0x184, 826 .route_val = BIT(16 + 8), 827 }, { 828 /* pdm-m1 */ 829 .bank_num = 2, 830 .pin = 22, 831 .func = 1, 832 .route_offset = 0x184, 833 .route_val = BIT(16 + 8) | BIT(8), 834 }, { 835 /* uart2-rxm0 */ 836 .bank_num = 1, 837 .pin = 27, 838 .func = 2, 839 .route_offset = 0x184, 840 .route_val = BIT(16 + 10), 841 }, { 842 /* uart2-rxm1 */ 843 .bank_num = 2, 844 .pin = 14, 845 .func = 2, 846 .route_offset = 0x184, 847 .route_val = BIT(16 + 10) | BIT(10), 848 }, { 849 /* uart3-rxm0 */ 850 .bank_num = 0, 851 .pin = 17, 852 .func = 2, 853 .route_offset = 0x184, 854 .route_val = BIT(16 + 9), 855 }, { 856 /* uart3-rxm1 */ 857 .bank_num = 1, 858 .pin = 15, 859 .func = 2, 860 .route_offset = 0x184, 861 .route_val = BIT(16 + 9) | BIT(9), 862 }, 863 }; 864 865 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 866 { 867 /* spi-0 */ 868 .bank_num = 1, 869 .pin = 10, 870 .func = 1, 871 .route_offset = 0x144, 872 .route_val = BIT(16 + 3) | BIT(16 + 4), 873 }, { 874 /* spi-1 */ 875 .bank_num = 1, 876 .pin = 27, 877 .func = 3, 878 .route_offset = 0x144, 879 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 880 }, { 881 /* spi-2 */ 882 .bank_num = 0, 883 .pin = 13, 884 .func = 2, 885 .route_offset = 0x144, 886 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 887 }, { 888 /* i2s-0 */ 889 .bank_num = 1, 890 .pin = 5, 891 .func = 1, 892 .route_offset = 0x144, 893 .route_val = BIT(16 + 5), 894 }, { 895 /* i2s-1 */ 896 .bank_num = 0, 897 .pin = 14, 898 .func = 1, 899 .route_offset = 0x144, 900 .route_val = BIT(16 + 5) | BIT(5), 901 }, { 902 /* emmc-0 */ 903 .bank_num = 1, 904 .pin = 22, 905 .func = 2, 906 .route_offset = 0x144, 907 .route_val = BIT(16 + 6), 908 }, { 909 /* emmc-1 */ 910 .bank_num = 2, 911 .pin = 4, 912 .func = 2, 913 .route_offset = 0x144, 914 .route_val = BIT(16 + 6) | BIT(6), 915 }, 916 }; 917 918 static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 919 { 920 /* non-iomuxed emmc/flash pins on flash-dqs */ 921 .bank_num = 0, 922 .pin = 24, 923 .func = 1, 924 .route_location = ROCKCHIP_ROUTE_GRF, 925 .route_offset = 0xa0, 926 .route_val = BIT(16 + 11), 927 }, { 928 /* non-iomuxed emmc/flash pins on emmc-clk */ 929 .bank_num = 0, 930 .pin = 24, 931 .func = 2, 932 .route_location = ROCKCHIP_ROUTE_GRF, 933 .route_offset = 0xa0, 934 .route_val = BIT(16 + 11) | BIT(11), 935 }, 936 }; 937 938 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 939 { 940 /* pwm0-0 */ 941 .bank_num = 0, 942 .pin = 26, 943 .func = 1, 944 .route_offset = 0x50, 945 .route_val = BIT(16), 946 }, { 947 /* pwm0-1 */ 948 .bank_num = 3, 949 .pin = 21, 950 .func = 1, 951 .route_offset = 0x50, 952 .route_val = BIT(16) | BIT(0), 953 }, { 954 /* pwm1-0 */ 955 .bank_num = 0, 956 .pin = 27, 957 .func = 1, 958 .route_offset = 0x50, 959 .route_val = BIT(16 + 1), 960 }, { 961 /* pwm1-1 */ 962 .bank_num = 0, 963 .pin = 30, 964 .func = 2, 965 .route_offset = 0x50, 966 .route_val = BIT(16 + 1) | BIT(1), 967 }, { 968 /* pwm2-0 */ 969 .bank_num = 0, 970 .pin = 28, 971 .func = 1, 972 .route_offset = 0x50, 973 .route_val = BIT(16 + 2), 974 }, { 975 /* pwm2-1 */ 976 .bank_num = 1, 977 .pin = 12, 978 .func = 2, 979 .route_offset = 0x50, 980 .route_val = BIT(16 + 2) | BIT(2), 981 }, { 982 /* pwm3-0 */ 983 .bank_num = 3, 984 .pin = 26, 985 .func = 1, 986 .route_offset = 0x50, 987 .route_val = BIT(16 + 3), 988 }, { 989 /* pwm3-1 */ 990 .bank_num = 1, 991 .pin = 11, 992 .func = 2, 993 .route_offset = 0x50, 994 .route_val = BIT(16 + 3) | BIT(3), 995 }, { 996 /* sdio-0_d0 */ 997 .bank_num = 1, 998 .pin = 1, 999 .func = 1, 1000 .route_offset = 0x50, 1001 .route_val = BIT(16 + 4), 1002 }, { 1003 /* sdio-1_d0 */ 1004 .bank_num = 3, 1005 .pin = 2, 1006 .func = 1, 1007 .route_offset = 0x50, 1008 .route_val = BIT(16 + 4) | BIT(4), 1009 }, { 1010 /* spi-0_rx */ 1011 .bank_num = 0, 1012 .pin = 13, 1013 .func = 2, 1014 .route_offset = 0x50, 1015 .route_val = BIT(16 + 5), 1016 }, { 1017 /* spi-1_rx */ 1018 .bank_num = 2, 1019 .pin = 0, 1020 .func = 2, 1021 .route_offset = 0x50, 1022 .route_val = BIT(16 + 5) | BIT(5), 1023 }, { 1024 /* emmc-0_cmd */ 1025 .bank_num = 1, 1026 .pin = 22, 1027 .func = 2, 1028 .route_offset = 0x50, 1029 .route_val = BIT(16 + 7), 1030 }, { 1031 /* emmc-1_cmd */ 1032 .bank_num = 2, 1033 .pin = 4, 1034 .func = 2, 1035 .route_offset = 0x50, 1036 .route_val = BIT(16 + 7) | BIT(7), 1037 }, { 1038 /* uart2-0_rx */ 1039 .bank_num = 1, 1040 .pin = 19, 1041 .func = 2, 1042 .route_offset = 0x50, 1043 .route_val = BIT(16 + 8), 1044 }, { 1045 /* uart2-1_rx */ 1046 .bank_num = 1, 1047 .pin = 10, 1048 .func = 2, 1049 .route_offset = 0x50, 1050 .route_val = BIT(16 + 8) | BIT(8), 1051 }, { 1052 /* uart1-0_rx */ 1053 .bank_num = 1, 1054 .pin = 10, 1055 .func = 1, 1056 .route_offset = 0x50, 1057 .route_val = BIT(16 + 11), 1058 }, { 1059 /* uart1-1_rx */ 1060 .bank_num = 3, 1061 .pin = 13, 1062 .func = 1, 1063 .route_offset = 0x50, 1064 .route_val = BIT(16 + 11) | BIT(11), 1065 }, 1066 }; 1067 1068 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 1069 { 1070 /* edphdmi_cecinoutt1 */ 1071 .bank_num = 7, 1072 .pin = 16, 1073 .func = 2, 1074 .route_offset = 0x264, 1075 .route_val = BIT(16 + 12) | BIT(12), 1076 }, { 1077 /* edphdmi_cecinout */ 1078 .bank_num = 7, 1079 .pin = 23, 1080 .func = 4, 1081 .route_offset = 0x264, 1082 .route_val = BIT(16 + 12), 1083 }, 1084 }; 1085 1086 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 1087 { 1088 /* rtc_clk */ 1089 .bank_num = 0, 1090 .pin = 19, 1091 .func = 1, 1092 .route_offset = 0x314, 1093 .route_val = BIT(16 + 0) | BIT(0), 1094 }, { 1095 /* uart2_rxm0 */ 1096 .bank_num = 1, 1097 .pin = 22, 1098 .func = 2, 1099 .route_offset = 0x314, 1100 .route_val = BIT(16 + 2) | BIT(16 + 3), 1101 }, { 1102 /* uart2_rxm1 */ 1103 .bank_num = 4, 1104 .pin = 26, 1105 .func = 2, 1106 .route_offset = 0x314, 1107 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1108 }, { 1109 /* i2c3_sdam0 */ 1110 .bank_num = 0, 1111 .pin = 15, 1112 .func = 2, 1113 .route_offset = 0x608, 1114 .route_val = BIT(16 + 8) | BIT(16 + 9), 1115 }, { 1116 /* i2c3_sdam1 */ 1117 .bank_num = 3, 1118 .pin = 12, 1119 .func = 2, 1120 .route_offset = 0x608, 1121 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1122 }, { 1123 /* i2c3_sdam2 */ 1124 .bank_num = 2, 1125 .pin = 0, 1126 .func = 3, 1127 .route_offset = 0x608, 1128 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1129 }, { 1130 /* i2s-8ch-1-sclktxm0 */ 1131 .bank_num = 1, 1132 .pin = 3, 1133 .func = 2, 1134 .route_offset = 0x308, 1135 .route_val = BIT(16 + 3), 1136 }, { 1137 /* i2s-8ch-1-sclkrxm0 */ 1138 .bank_num = 1, 1139 .pin = 4, 1140 .func = 2, 1141 .route_offset = 0x308, 1142 .route_val = BIT(16 + 3), 1143 }, { 1144 /* i2s-8ch-1-sclktxm1 */ 1145 .bank_num = 1, 1146 .pin = 13, 1147 .func = 2, 1148 .route_offset = 0x308, 1149 .route_val = BIT(16 + 3) | BIT(3), 1150 }, { 1151 /* i2s-8ch-1-sclkrxm1 */ 1152 .bank_num = 1, 1153 .pin = 14, 1154 .func = 2, 1155 .route_offset = 0x308, 1156 .route_val = BIT(16 + 3) | BIT(3), 1157 }, { 1158 /* pdm-clkm0 */ 1159 .bank_num = 1, 1160 .pin = 4, 1161 .func = 3, 1162 .route_offset = 0x308, 1163 .route_val = BIT(16 + 12) | BIT(16 + 13), 1164 }, { 1165 /* pdm-clkm1 */ 1166 .bank_num = 1, 1167 .pin = 14, 1168 .func = 4, 1169 .route_offset = 0x308, 1170 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1171 }, { 1172 /* pdm-clkm2 */ 1173 .bank_num = 2, 1174 .pin = 6, 1175 .func = 2, 1176 .route_offset = 0x308, 1177 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1178 }, { 1179 /* pdm-clkm-m2 */ 1180 .bank_num = 2, 1181 .pin = 4, 1182 .func = 3, 1183 .route_offset = 0x600, 1184 .route_val = BIT(16 + 2) | BIT(2), 1185 }, { 1186 /* spi1_miso */ 1187 .bank_num = 3, 1188 .pin = 10, 1189 .func = 3, 1190 .route_offset = 0x314, 1191 .route_val = BIT(16 + 9), 1192 }, { 1193 /* spi1_miso_m1 */ 1194 .bank_num = 2, 1195 .pin = 4, 1196 .func = 2, 1197 .route_offset = 0x314, 1198 .route_val = BIT(16 + 9) | BIT(9), 1199 }, { 1200 /* owire_m0 */ 1201 .bank_num = 0, 1202 .pin = 11, 1203 .func = 3, 1204 .route_offset = 0x314, 1205 .route_val = BIT(16 + 10) | BIT(16 + 11), 1206 }, { 1207 /* owire_m1 */ 1208 .bank_num = 1, 1209 .pin = 22, 1210 .func = 7, 1211 .route_offset = 0x314, 1212 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1213 }, { 1214 /* owire_m2 */ 1215 .bank_num = 2, 1216 .pin = 2, 1217 .func = 5, 1218 .route_offset = 0x314, 1219 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1220 }, { 1221 /* can_rxd_m0 */ 1222 .bank_num = 0, 1223 .pin = 11, 1224 .func = 2, 1225 .route_offset = 0x314, 1226 .route_val = BIT(16 + 12) | BIT(16 + 13), 1227 }, { 1228 /* can_rxd_m1 */ 1229 .bank_num = 1, 1230 .pin = 22, 1231 .func = 5, 1232 .route_offset = 0x314, 1233 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1234 }, { 1235 /* can_rxd_m2 */ 1236 .bank_num = 2, 1237 .pin = 2, 1238 .func = 4, 1239 .route_offset = 0x314, 1240 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1241 }, { 1242 /* mac_rxd0_m0 */ 1243 .bank_num = 1, 1244 .pin = 20, 1245 .func = 3, 1246 .route_offset = 0x314, 1247 .route_val = BIT(16 + 14), 1248 }, { 1249 /* mac_rxd0_m1 */ 1250 .bank_num = 4, 1251 .pin = 2, 1252 .func = 2, 1253 .route_offset = 0x314, 1254 .route_val = BIT(16 + 14) | BIT(14), 1255 }, { 1256 /* uart3_rx */ 1257 .bank_num = 3, 1258 .pin = 12, 1259 .func = 4, 1260 .route_offset = 0x314, 1261 .route_val = BIT(16 + 15), 1262 }, { 1263 /* uart3_rx_m1 */ 1264 .bank_num = 0, 1265 .pin = 17, 1266 .func = 3, 1267 .route_offset = 0x314, 1268 .route_val = BIT(16 + 15) | BIT(15), 1269 }, 1270 }; 1271 1272 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1273 { 1274 /* uart2dbg_rxm0 */ 1275 .bank_num = 1, 1276 .pin = 1, 1277 .func = 2, 1278 .route_offset = 0x50, 1279 .route_val = BIT(16) | BIT(16 + 1), 1280 }, { 1281 /* uart2dbg_rxm1 */ 1282 .bank_num = 2, 1283 .pin = 1, 1284 .func = 1, 1285 .route_offset = 0x50, 1286 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1287 }, { 1288 /* gmac-m1_rxd0 */ 1289 .bank_num = 1, 1290 .pin = 11, 1291 .func = 2, 1292 .route_offset = 0x50, 1293 .route_val = BIT(16 + 2) | BIT(2), 1294 }, { 1295 /* gmac-m1-optimized_rxd3 */ 1296 .bank_num = 1, 1297 .pin = 14, 1298 .func = 2, 1299 .route_offset = 0x50, 1300 .route_val = BIT(16 + 10) | BIT(10), 1301 }, { 1302 /* pdm_sdi0m0 */ 1303 .bank_num = 2, 1304 .pin = 19, 1305 .func = 2, 1306 .route_offset = 0x50, 1307 .route_val = BIT(16 + 3), 1308 }, { 1309 /* pdm_sdi0m1 */ 1310 .bank_num = 1, 1311 .pin = 23, 1312 .func = 3, 1313 .route_offset = 0x50, 1314 .route_val = BIT(16 + 3) | BIT(3), 1315 }, { 1316 /* spi_rxdm2 */ 1317 .bank_num = 3, 1318 .pin = 2, 1319 .func = 4, 1320 .route_offset = 0x50, 1321 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1322 }, { 1323 /* i2s2_sdim0 */ 1324 .bank_num = 1, 1325 .pin = 24, 1326 .func = 1, 1327 .route_offset = 0x50, 1328 .route_val = BIT(16 + 6), 1329 }, { 1330 /* i2s2_sdim1 */ 1331 .bank_num = 3, 1332 .pin = 2, 1333 .func = 6, 1334 .route_offset = 0x50, 1335 .route_val = BIT(16 + 6) | BIT(6), 1336 }, { 1337 /* card_iom1 */ 1338 .bank_num = 2, 1339 .pin = 22, 1340 .func = 3, 1341 .route_offset = 0x50, 1342 .route_val = BIT(16 + 7) | BIT(7), 1343 }, { 1344 /* tsp_d5m1 */ 1345 .bank_num = 2, 1346 .pin = 16, 1347 .func = 3, 1348 .route_offset = 0x50, 1349 .route_val = BIT(16 + 8) | BIT(8), 1350 }, { 1351 /* cif_data5m1 */ 1352 .bank_num = 2, 1353 .pin = 16, 1354 .func = 4, 1355 .route_offset = 0x50, 1356 .route_val = BIT(16 + 9) | BIT(9), 1357 }, 1358 }; 1359 1360 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1361 { 1362 /* uart2dbga_rx */ 1363 .bank_num = 4, 1364 .pin = 8, 1365 .func = 2, 1366 .route_offset = 0xe21c, 1367 .route_val = BIT(16 + 10) | BIT(16 + 11), 1368 }, { 1369 /* uart2dbgb_rx */ 1370 .bank_num = 4, 1371 .pin = 16, 1372 .func = 2, 1373 .route_offset = 0xe21c, 1374 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1375 }, { 1376 /* uart2dbgc_rx */ 1377 .bank_num = 4, 1378 .pin = 19, 1379 .func = 1, 1380 .route_offset = 0xe21c, 1381 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1382 }, { 1383 /* pcie_clkreqn */ 1384 .bank_num = 2, 1385 .pin = 26, 1386 .func = 2, 1387 .route_offset = 0xe21c, 1388 .route_val = BIT(16 + 14), 1389 }, { 1390 /* pcie_clkreqnb */ 1391 .bank_num = 4, 1392 .pin = 24, 1393 .func = 1, 1394 .route_offset = 0xe21c, 1395 .route_val = BIT(16 + 14) | BIT(14), 1396 }, 1397 }; 1398 1399 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1400 int mux, u32 *loc, u32 *reg, u32 *value) 1401 { 1402 struct rockchip_pinctrl *info = bank->drvdata; 1403 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1404 struct rockchip_mux_route_data *data; 1405 int i; 1406 1407 for (i = 0; i < ctrl->niomux_routes; i++) { 1408 data = &ctrl->iomux_routes[i]; 1409 if ((data->bank_num == bank->bank_num) && 1410 (data->pin == pin) && (data->func == mux)) 1411 break; 1412 } 1413 1414 if (i >= ctrl->niomux_routes) 1415 return false; 1416 1417 *loc = data->route_location; 1418 *reg = data->route_offset; 1419 *value = data->route_val; 1420 1421 return true; 1422 } 1423 1424 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1425 { 1426 struct rockchip_pinctrl *info = bank->drvdata; 1427 int iomux_num = (pin / 8); 1428 struct regmap *regmap; 1429 unsigned int val; 1430 int reg, ret, mask, mux_type; 1431 u8 bit; 1432 1433 if (iomux_num > 3) 1434 return -EINVAL; 1435 1436 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1437 dev_err(info->dev, "pin %d is unrouted\n", pin); 1438 return -EINVAL; 1439 } 1440 1441 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1442 return RK_FUNC_GPIO; 1443 1444 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1445 ? info->regmap_pmu : info->regmap_base; 1446 1447 /* get basic quadrupel of mux registers and the correct reg inside */ 1448 mux_type = bank->iomux[iomux_num].type; 1449 reg = bank->iomux[iomux_num].offset; 1450 if (mux_type & IOMUX_WIDTH_4BIT) { 1451 if ((pin % 8) >= 4) 1452 reg += 0x4; 1453 bit = (pin % 4) * 4; 1454 mask = 0xf; 1455 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1456 if ((pin % 8) >= 5) 1457 reg += 0x4; 1458 bit = (pin % 8 % 5) * 3; 1459 mask = 0x7; 1460 } else { 1461 bit = (pin % 8) * 2; 1462 mask = 0x3; 1463 } 1464 1465 if (bank->recalced_mask & BIT(pin)) 1466 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1467 1468 ret = regmap_read(regmap, reg, &val); 1469 if (ret) 1470 return ret; 1471 1472 return ((val >> bit) & mask); 1473 } 1474 1475 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1476 int pin, int mux) 1477 { 1478 struct rockchip_pinctrl *info = bank->drvdata; 1479 int iomux_num = (pin / 8); 1480 1481 if (iomux_num > 3) 1482 return -EINVAL; 1483 1484 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1485 dev_err(info->dev, "pin %d is unrouted\n", pin); 1486 return -EINVAL; 1487 } 1488 1489 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1490 if (mux != RK_FUNC_GPIO) { 1491 dev_err(info->dev, 1492 "pin %d only supports a gpio mux\n", pin); 1493 return -ENOTSUPP; 1494 } 1495 } 1496 1497 return 0; 1498 } 1499 1500 /* 1501 * Set a new mux function for a pin. 1502 * 1503 * The register is divided into the upper and lower 16 bit. When changing 1504 * a value, the previous register value is not read and changed. Instead 1505 * it seems the changed bits are marked in the upper 16 bit, while the 1506 * changed value gets set in the same offset in the lower 16 bit. 1507 * All pin settings seem to be 2 bit wide in both the upper and lower 1508 * parts. 1509 * @bank: pin bank to change 1510 * @pin: pin to change 1511 * @mux: new mux function to set 1512 */ 1513 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1514 { 1515 struct rockchip_pinctrl *info = bank->drvdata; 1516 int iomux_num = (pin / 8); 1517 struct regmap *regmap; 1518 int reg, ret, mask, mux_type; 1519 u8 bit; 1520 u32 data, rmask, route_location, route_reg, route_val; 1521 1522 ret = rockchip_verify_mux(bank, pin, mux); 1523 if (ret < 0) 1524 return ret; 1525 1526 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1527 return 0; 1528 1529 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 1530 bank->bank_num, pin, mux); 1531 1532 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1533 ? info->regmap_pmu : info->regmap_base; 1534 1535 /* get basic quadrupel of mux registers and the correct reg inside */ 1536 mux_type = bank->iomux[iomux_num].type; 1537 reg = bank->iomux[iomux_num].offset; 1538 if (mux_type & IOMUX_WIDTH_4BIT) { 1539 if ((pin % 8) >= 4) 1540 reg += 0x4; 1541 bit = (pin % 4) * 4; 1542 mask = 0xf; 1543 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1544 if ((pin % 8) >= 5) 1545 reg += 0x4; 1546 bit = (pin % 8 % 5) * 3; 1547 mask = 0x7; 1548 } else { 1549 bit = (pin % 8) * 2; 1550 mask = 0x3; 1551 } 1552 1553 if (bank->recalced_mask & BIT(pin)) 1554 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1555 1556 if (bank->route_mask & BIT(pin)) { 1557 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1558 &route_reg, &route_val)) { 1559 struct regmap *route_regmap = regmap; 1560 1561 /* handle special locations */ 1562 switch (route_location) { 1563 case ROCKCHIP_ROUTE_PMU: 1564 route_regmap = info->regmap_pmu; 1565 break; 1566 case ROCKCHIP_ROUTE_GRF: 1567 route_regmap = info->regmap_base; 1568 break; 1569 } 1570 1571 ret = regmap_write(route_regmap, route_reg, route_val); 1572 if (ret) 1573 return ret; 1574 } 1575 } 1576 1577 data = (mask << (bit + 16)); 1578 rmask = data | (data >> 16); 1579 data |= (mux & mask) << bit; 1580 ret = regmap_update_bits(regmap, reg, rmask, data); 1581 1582 return ret; 1583 } 1584 1585 #define PX30_PULL_PMU_OFFSET 0x10 1586 #define PX30_PULL_GRF_OFFSET 0x60 1587 #define PX30_PULL_BITS_PER_PIN 2 1588 #define PX30_PULL_PINS_PER_REG 8 1589 #define PX30_PULL_BANK_STRIDE 16 1590 1591 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1592 int pin_num, struct regmap **regmap, 1593 int *reg, u8 *bit) 1594 { 1595 struct rockchip_pinctrl *info = bank->drvdata; 1596 1597 /* The first 32 pins of the first bank are located in PMU */ 1598 if (bank->bank_num == 0) { 1599 *regmap = info->regmap_pmu; 1600 *reg = PX30_PULL_PMU_OFFSET; 1601 } else { 1602 *regmap = info->regmap_base; 1603 *reg = PX30_PULL_GRF_OFFSET; 1604 1605 /* correct the offset, as we're starting with the 2nd bank */ 1606 *reg -= 0x10; 1607 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1608 } 1609 1610 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1611 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1612 *bit *= PX30_PULL_BITS_PER_PIN; 1613 } 1614 1615 #define PX30_DRV_PMU_OFFSET 0x20 1616 #define PX30_DRV_GRF_OFFSET 0xf0 1617 #define PX30_DRV_BITS_PER_PIN 2 1618 #define PX30_DRV_PINS_PER_REG 8 1619 #define PX30_DRV_BANK_STRIDE 16 1620 1621 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1622 int pin_num, struct regmap **regmap, 1623 int *reg, u8 *bit) 1624 { 1625 struct rockchip_pinctrl *info = bank->drvdata; 1626 1627 /* The first 32 pins of the first bank are located in PMU */ 1628 if (bank->bank_num == 0) { 1629 *regmap = info->regmap_pmu; 1630 *reg = PX30_DRV_PMU_OFFSET; 1631 } else { 1632 *regmap = info->regmap_base; 1633 *reg = PX30_DRV_GRF_OFFSET; 1634 1635 /* correct the offset, as we're starting with the 2nd bank */ 1636 *reg -= 0x10; 1637 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1638 } 1639 1640 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1641 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1642 *bit *= PX30_DRV_BITS_PER_PIN; 1643 } 1644 1645 #define PX30_SCHMITT_PMU_OFFSET 0x38 1646 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1647 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1648 #define PX30_SCHMITT_BANK_STRIDE 16 1649 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1650 1651 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1652 int pin_num, 1653 struct regmap **regmap, 1654 int *reg, u8 *bit) 1655 { 1656 struct rockchip_pinctrl *info = bank->drvdata; 1657 int pins_per_reg; 1658 1659 if (bank->bank_num == 0) { 1660 *regmap = info->regmap_pmu; 1661 *reg = PX30_SCHMITT_PMU_OFFSET; 1662 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1663 } else { 1664 *regmap = info->regmap_base; 1665 *reg = PX30_SCHMITT_GRF_OFFSET; 1666 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1667 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1668 } 1669 1670 *reg += ((pin_num / pins_per_reg) * 4); 1671 *bit = pin_num % pins_per_reg; 1672 1673 return 0; 1674 } 1675 1676 #define RV1108_PULL_PMU_OFFSET 0x10 1677 #define RV1108_PULL_OFFSET 0x110 1678 #define RV1108_PULL_PINS_PER_REG 8 1679 #define RV1108_PULL_BITS_PER_PIN 2 1680 #define RV1108_PULL_BANK_STRIDE 16 1681 1682 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1683 int pin_num, struct regmap **regmap, 1684 int *reg, u8 *bit) 1685 { 1686 struct rockchip_pinctrl *info = bank->drvdata; 1687 1688 /* The first 24 pins of the first bank are located in PMU */ 1689 if (bank->bank_num == 0) { 1690 *regmap = info->regmap_pmu; 1691 *reg = RV1108_PULL_PMU_OFFSET; 1692 } else { 1693 *reg = RV1108_PULL_OFFSET; 1694 *regmap = info->regmap_base; 1695 /* correct the offset, as we're starting with the 2nd bank */ 1696 *reg -= 0x10; 1697 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1698 } 1699 1700 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1701 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1702 *bit *= RV1108_PULL_BITS_PER_PIN; 1703 } 1704 1705 #define RV1108_DRV_PMU_OFFSET 0x20 1706 #define RV1108_DRV_GRF_OFFSET 0x210 1707 #define RV1108_DRV_BITS_PER_PIN 2 1708 #define RV1108_DRV_PINS_PER_REG 8 1709 #define RV1108_DRV_BANK_STRIDE 16 1710 1711 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1712 int pin_num, struct regmap **regmap, 1713 int *reg, u8 *bit) 1714 { 1715 struct rockchip_pinctrl *info = bank->drvdata; 1716 1717 /* The first 24 pins of the first bank are located in PMU */ 1718 if (bank->bank_num == 0) { 1719 *regmap = info->regmap_pmu; 1720 *reg = RV1108_DRV_PMU_OFFSET; 1721 } else { 1722 *regmap = info->regmap_base; 1723 *reg = RV1108_DRV_GRF_OFFSET; 1724 1725 /* correct the offset, as we're starting with the 2nd bank */ 1726 *reg -= 0x10; 1727 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1728 } 1729 1730 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1731 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1732 *bit *= RV1108_DRV_BITS_PER_PIN; 1733 } 1734 1735 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1736 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1737 #define RV1108_SCHMITT_BANK_STRIDE 8 1738 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1739 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1740 1741 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1742 int pin_num, 1743 struct regmap **regmap, 1744 int *reg, u8 *bit) 1745 { 1746 struct rockchip_pinctrl *info = bank->drvdata; 1747 int pins_per_reg; 1748 1749 if (bank->bank_num == 0) { 1750 *regmap = info->regmap_pmu; 1751 *reg = RV1108_SCHMITT_PMU_OFFSET; 1752 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1753 } else { 1754 *regmap = info->regmap_base; 1755 *reg = RV1108_SCHMITT_GRF_OFFSET; 1756 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1757 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1758 } 1759 *reg += ((pin_num / pins_per_reg) * 4); 1760 *bit = pin_num % pins_per_reg; 1761 1762 return 0; 1763 } 1764 1765 #define RK3308_SCHMITT_PINS_PER_REG 8 1766 #define RK3308_SCHMITT_BANK_STRIDE 16 1767 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1768 1769 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1770 int pin_num, struct regmap **regmap, 1771 int *reg, u8 *bit) 1772 { 1773 struct rockchip_pinctrl *info = bank->drvdata; 1774 1775 *regmap = info->regmap_base; 1776 *reg = RK3308_SCHMITT_GRF_OFFSET; 1777 1778 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1779 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1780 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1781 1782 return 0; 1783 } 1784 1785 #define RK2928_PULL_OFFSET 0x118 1786 #define RK2928_PULL_PINS_PER_REG 16 1787 #define RK2928_PULL_BANK_STRIDE 8 1788 1789 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1790 int pin_num, struct regmap **regmap, 1791 int *reg, u8 *bit) 1792 { 1793 struct rockchip_pinctrl *info = bank->drvdata; 1794 1795 *regmap = info->regmap_base; 1796 *reg = RK2928_PULL_OFFSET; 1797 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1798 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1799 1800 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1801 }; 1802 1803 #define RK3128_PULL_OFFSET 0x118 1804 1805 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1806 int pin_num, struct regmap **regmap, 1807 int *reg, u8 *bit) 1808 { 1809 struct rockchip_pinctrl *info = bank->drvdata; 1810 1811 *regmap = info->regmap_base; 1812 *reg = RK3128_PULL_OFFSET; 1813 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1814 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1815 1816 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1817 } 1818 1819 #define RK3188_PULL_OFFSET 0x164 1820 #define RK3188_PULL_BITS_PER_PIN 2 1821 #define RK3188_PULL_PINS_PER_REG 8 1822 #define RK3188_PULL_BANK_STRIDE 16 1823 #define RK3188_PULL_PMU_OFFSET 0x64 1824 1825 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1826 int pin_num, struct regmap **regmap, 1827 int *reg, u8 *bit) 1828 { 1829 struct rockchip_pinctrl *info = bank->drvdata; 1830 1831 /* The first 12 pins of the first bank are located elsewhere */ 1832 if (bank->bank_num == 0 && pin_num < 12) { 1833 *regmap = info->regmap_pmu ? info->regmap_pmu 1834 : bank->regmap_pull; 1835 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1836 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1837 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1838 *bit *= RK3188_PULL_BITS_PER_PIN; 1839 } else { 1840 *regmap = info->regmap_pull ? info->regmap_pull 1841 : info->regmap_base; 1842 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1843 1844 /* correct the offset, as it is the 2nd pull register */ 1845 *reg -= 4; 1846 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1847 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1848 1849 /* 1850 * The bits in these registers have an inverse ordering 1851 * with the lowest pin being in bits 15:14 and the highest 1852 * pin in bits 1:0 1853 */ 1854 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1855 *bit *= RK3188_PULL_BITS_PER_PIN; 1856 } 1857 } 1858 1859 #define RK3288_PULL_OFFSET 0x140 1860 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1861 int pin_num, struct regmap **regmap, 1862 int *reg, u8 *bit) 1863 { 1864 struct rockchip_pinctrl *info = bank->drvdata; 1865 1866 /* The first 24 pins of the first bank are located in PMU */ 1867 if (bank->bank_num == 0) { 1868 *regmap = info->regmap_pmu; 1869 *reg = RK3188_PULL_PMU_OFFSET; 1870 1871 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1872 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1873 *bit *= RK3188_PULL_BITS_PER_PIN; 1874 } else { 1875 *regmap = info->regmap_base; 1876 *reg = RK3288_PULL_OFFSET; 1877 1878 /* correct the offset, as we're starting with the 2nd bank */ 1879 *reg -= 0x10; 1880 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1881 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1882 1883 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1884 *bit *= RK3188_PULL_BITS_PER_PIN; 1885 } 1886 } 1887 1888 #define RK3288_DRV_PMU_OFFSET 0x70 1889 #define RK3288_DRV_GRF_OFFSET 0x1c0 1890 #define RK3288_DRV_BITS_PER_PIN 2 1891 #define RK3288_DRV_PINS_PER_REG 8 1892 #define RK3288_DRV_BANK_STRIDE 16 1893 1894 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1895 int pin_num, struct regmap **regmap, 1896 int *reg, u8 *bit) 1897 { 1898 struct rockchip_pinctrl *info = bank->drvdata; 1899 1900 /* The first 24 pins of the first bank are located in PMU */ 1901 if (bank->bank_num == 0) { 1902 *regmap = info->regmap_pmu; 1903 *reg = RK3288_DRV_PMU_OFFSET; 1904 1905 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1906 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1907 *bit *= RK3288_DRV_BITS_PER_PIN; 1908 } else { 1909 *regmap = info->regmap_base; 1910 *reg = RK3288_DRV_GRF_OFFSET; 1911 1912 /* correct the offset, as we're starting with the 2nd bank */ 1913 *reg -= 0x10; 1914 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1915 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1916 1917 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1918 *bit *= RK3288_DRV_BITS_PER_PIN; 1919 } 1920 } 1921 1922 #define RK3228_PULL_OFFSET 0x100 1923 1924 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1925 int pin_num, struct regmap **regmap, 1926 int *reg, u8 *bit) 1927 { 1928 struct rockchip_pinctrl *info = bank->drvdata; 1929 1930 *regmap = info->regmap_base; 1931 *reg = RK3228_PULL_OFFSET; 1932 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1933 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1934 1935 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1936 *bit *= RK3188_PULL_BITS_PER_PIN; 1937 } 1938 1939 #define RK3228_DRV_GRF_OFFSET 0x200 1940 1941 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1942 int pin_num, struct regmap **regmap, 1943 int *reg, u8 *bit) 1944 { 1945 struct rockchip_pinctrl *info = bank->drvdata; 1946 1947 *regmap = info->regmap_base; 1948 *reg = RK3228_DRV_GRF_OFFSET; 1949 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1950 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1951 1952 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1953 *bit *= RK3288_DRV_BITS_PER_PIN; 1954 } 1955 1956 #define RK3308_PULL_OFFSET 0xa0 1957 1958 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1959 int pin_num, struct regmap **regmap, 1960 int *reg, u8 *bit) 1961 { 1962 struct rockchip_pinctrl *info = bank->drvdata; 1963 1964 *regmap = info->regmap_base; 1965 *reg = RK3308_PULL_OFFSET; 1966 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1967 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1968 1969 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1970 *bit *= RK3188_PULL_BITS_PER_PIN; 1971 } 1972 1973 #define RK3308_DRV_GRF_OFFSET 0x100 1974 1975 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1976 int pin_num, struct regmap **regmap, 1977 int *reg, u8 *bit) 1978 { 1979 struct rockchip_pinctrl *info = bank->drvdata; 1980 1981 *regmap = info->regmap_base; 1982 *reg = RK3308_DRV_GRF_OFFSET; 1983 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1984 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1985 1986 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1987 *bit *= RK3288_DRV_BITS_PER_PIN; 1988 } 1989 1990 #define RK3368_PULL_GRF_OFFSET 0x100 1991 #define RK3368_PULL_PMU_OFFSET 0x10 1992 1993 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1994 int pin_num, struct regmap **regmap, 1995 int *reg, u8 *bit) 1996 { 1997 struct rockchip_pinctrl *info = bank->drvdata; 1998 1999 /* The first 32 pins of the first bank are located in PMU */ 2000 if (bank->bank_num == 0) { 2001 *regmap = info->regmap_pmu; 2002 *reg = RK3368_PULL_PMU_OFFSET; 2003 2004 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2005 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2006 *bit *= RK3188_PULL_BITS_PER_PIN; 2007 } else { 2008 *regmap = info->regmap_base; 2009 *reg = RK3368_PULL_GRF_OFFSET; 2010 2011 /* correct the offset, as we're starting with the 2nd bank */ 2012 *reg -= 0x10; 2013 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2014 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2015 2016 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2017 *bit *= RK3188_PULL_BITS_PER_PIN; 2018 } 2019 } 2020 2021 #define RK3368_DRV_PMU_OFFSET 0x20 2022 #define RK3368_DRV_GRF_OFFSET 0x200 2023 2024 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2025 int pin_num, struct regmap **regmap, 2026 int *reg, u8 *bit) 2027 { 2028 struct rockchip_pinctrl *info = bank->drvdata; 2029 2030 /* The first 32 pins of the first bank are located in PMU */ 2031 if (bank->bank_num == 0) { 2032 *regmap = info->regmap_pmu; 2033 *reg = RK3368_DRV_PMU_OFFSET; 2034 2035 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2036 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2037 *bit *= RK3288_DRV_BITS_PER_PIN; 2038 } else { 2039 *regmap = info->regmap_base; 2040 *reg = RK3368_DRV_GRF_OFFSET; 2041 2042 /* correct the offset, as we're starting with the 2nd bank */ 2043 *reg -= 0x10; 2044 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2045 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2046 2047 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2048 *bit *= RK3288_DRV_BITS_PER_PIN; 2049 } 2050 } 2051 2052 #define RK3399_PULL_GRF_OFFSET 0xe040 2053 #define RK3399_PULL_PMU_OFFSET 0x40 2054 #define RK3399_DRV_3BITS_PER_PIN 3 2055 2056 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2057 int pin_num, struct regmap **regmap, 2058 int *reg, u8 *bit) 2059 { 2060 struct rockchip_pinctrl *info = bank->drvdata; 2061 2062 /* The bank0:16 and bank1:32 pins are located in PMU */ 2063 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2064 *regmap = info->regmap_pmu; 2065 *reg = RK3399_PULL_PMU_OFFSET; 2066 2067 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2068 2069 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2070 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2071 *bit *= RK3188_PULL_BITS_PER_PIN; 2072 } else { 2073 *regmap = info->regmap_base; 2074 *reg = RK3399_PULL_GRF_OFFSET; 2075 2076 /* correct the offset, as we're starting with the 3rd bank */ 2077 *reg -= 0x20; 2078 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2079 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2080 2081 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2082 *bit *= RK3188_PULL_BITS_PER_PIN; 2083 } 2084 } 2085 2086 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2087 int pin_num, struct regmap **regmap, 2088 int *reg, u8 *bit) 2089 { 2090 struct rockchip_pinctrl *info = bank->drvdata; 2091 int drv_num = (pin_num / 8); 2092 2093 /* The bank0:16 and bank1:32 pins are located in PMU */ 2094 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2095 *regmap = info->regmap_pmu; 2096 else 2097 *regmap = info->regmap_base; 2098 2099 *reg = bank->drv[drv_num].offset; 2100 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2101 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2102 *bit = (pin_num % 8) * 3; 2103 else 2104 *bit = (pin_num % 8) * 2; 2105 } 2106 2107 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2108 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2109 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2110 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2111 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2112 { 4, 7, 10, 13, 16, 19, 22, 26 } 2113 }; 2114 2115 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 2116 int pin_num) 2117 { 2118 struct rockchip_pinctrl *info = bank->drvdata; 2119 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2120 struct regmap *regmap; 2121 int reg, ret; 2122 u32 data, temp, rmask_bits; 2123 u8 bit; 2124 int drv_type = bank->drv[pin_num / 8].drv_type; 2125 2126 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2127 2128 switch (drv_type) { 2129 case DRV_TYPE_IO_1V8_3V0_AUTO: 2130 case DRV_TYPE_IO_3V3_ONLY: 2131 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2132 switch (bit) { 2133 case 0 ... 12: 2134 /* regular case, nothing to do */ 2135 break; 2136 case 15: 2137 /* 2138 * drive-strength offset is special, as it is 2139 * spread over 2 registers 2140 */ 2141 ret = regmap_read(regmap, reg, &data); 2142 if (ret) 2143 return ret; 2144 2145 ret = regmap_read(regmap, reg + 0x4, &temp); 2146 if (ret) 2147 return ret; 2148 2149 /* 2150 * the bit data[15] contains bit 0 of the value 2151 * while temp[1:0] contains bits 2 and 1 2152 */ 2153 data >>= 15; 2154 temp &= 0x3; 2155 temp <<= 1; 2156 data |= temp; 2157 2158 return rockchip_perpin_drv_list[drv_type][data]; 2159 case 18 ... 21: 2160 /* setting fully enclosed in the second register */ 2161 reg += 4; 2162 bit -= 16; 2163 break; 2164 default: 2165 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2166 bit, drv_type); 2167 return -EINVAL; 2168 } 2169 2170 break; 2171 case DRV_TYPE_IO_DEFAULT: 2172 case DRV_TYPE_IO_1V8_OR_3V0: 2173 case DRV_TYPE_IO_1V8_ONLY: 2174 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2175 break; 2176 default: 2177 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 2178 drv_type); 2179 return -EINVAL; 2180 } 2181 2182 ret = regmap_read(regmap, reg, &data); 2183 if (ret) 2184 return ret; 2185 2186 data >>= bit; 2187 data &= (1 << rmask_bits) - 1; 2188 2189 return rockchip_perpin_drv_list[drv_type][data]; 2190 } 2191 2192 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2193 int pin_num, int strength) 2194 { 2195 struct rockchip_pinctrl *info = bank->drvdata; 2196 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2197 struct regmap *regmap; 2198 int reg, ret, i; 2199 u32 data, rmask, rmask_bits, temp; 2200 u8 bit; 2201 int drv_type = bank->drv[pin_num / 8].drv_type; 2202 2203 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", 2204 bank->bank_num, pin_num, strength); 2205 2206 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2207 2208 ret = -EINVAL; 2209 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2210 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2211 ret = i; 2212 break; 2213 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2214 ret = rockchip_perpin_drv_list[drv_type][i]; 2215 break; 2216 } 2217 } 2218 2219 if (ret < 0) { 2220 dev_err(info->dev, "unsupported driver strength %d\n", 2221 strength); 2222 return ret; 2223 } 2224 2225 switch (drv_type) { 2226 case DRV_TYPE_IO_1V8_3V0_AUTO: 2227 case DRV_TYPE_IO_3V3_ONLY: 2228 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2229 switch (bit) { 2230 case 0 ... 12: 2231 /* regular case, nothing to do */ 2232 break; 2233 case 15: 2234 /* 2235 * drive-strength offset is special, as it is spread 2236 * over 2 registers, the bit data[15] contains bit 0 2237 * of the value while temp[1:0] contains bits 2 and 1 2238 */ 2239 data = (ret & 0x1) << 15; 2240 temp = (ret >> 0x1) & 0x3; 2241 2242 rmask = BIT(15) | BIT(31); 2243 data |= BIT(31); 2244 ret = regmap_update_bits(regmap, reg, rmask, data); 2245 if (ret) 2246 return ret; 2247 2248 rmask = 0x3 | (0x3 << 16); 2249 temp |= (0x3 << 16); 2250 reg += 0x4; 2251 ret = regmap_update_bits(regmap, reg, rmask, temp); 2252 2253 return ret; 2254 case 18 ... 21: 2255 /* setting fully enclosed in the second register */ 2256 reg += 4; 2257 bit -= 16; 2258 break; 2259 default: 2260 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2261 bit, drv_type); 2262 return -EINVAL; 2263 } 2264 break; 2265 case DRV_TYPE_IO_DEFAULT: 2266 case DRV_TYPE_IO_1V8_OR_3V0: 2267 case DRV_TYPE_IO_1V8_ONLY: 2268 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2269 break; 2270 default: 2271 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 2272 drv_type); 2273 return -EINVAL; 2274 } 2275 2276 /* enable the write to the equivalent lower bits */ 2277 data = ((1 << rmask_bits) - 1) << (bit + 16); 2278 rmask = data | (data >> 16); 2279 data |= (ret << bit); 2280 2281 ret = regmap_update_bits(regmap, reg, rmask, data); 2282 2283 return ret; 2284 } 2285 2286 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2287 { 2288 PIN_CONFIG_BIAS_DISABLE, 2289 PIN_CONFIG_BIAS_PULL_UP, 2290 PIN_CONFIG_BIAS_PULL_DOWN, 2291 PIN_CONFIG_BIAS_BUS_HOLD 2292 }, 2293 { 2294 PIN_CONFIG_BIAS_DISABLE, 2295 PIN_CONFIG_BIAS_PULL_DOWN, 2296 PIN_CONFIG_BIAS_DISABLE, 2297 PIN_CONFIG_BIAS_PULL_UP 2298 }, 2299 }; 2300 2301 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 2302 { 2303 struct rockchip_pinctrl *info = bank->drvdata; 2304 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2305 struct regmap *regmap; 2306 int reg, ret, pull_type; 2307 u8 bit; 2308 u32 data; 2309 2310 /* rk3066b does support any pulls */ 2311 if (ctrl->type == RK3066B) 2312 return PIN_CONFIG_BIAS_DISABLE; 2313 2314 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2315 2316 ret = regmap_read(regmap, reg, &data); 2317 if (ret) 2318 return ret; 2319 2320 switch (ctrl->type) { 2321 case RK2928: 2322 case RK3128: 2323 return !(data & BIT(bit)) 2324 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 2325 : PIN_CONFIG_BIAS_DISABLE; 2326 case PX30: 2327 case RV1108: 2328 case RK3188: 2329 case RK3288: 2330 case RK3308: 2331 case RK3368: 2332 case RK3399: 2333 pull_type = bank->pull_type[pin_num / 8]; 2334 data >>= bit; 2335 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 2336 2337 return rockchip_pull_list[pull_type][data]; 2338 default: 2339 dev_err(info->dev, "unsupported pinctrl type\n"); 2340 return -EINVAL; 2341 }; 2342 } 2343 2344 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2345 int pin_num, int pull) 2346 { 2347 struct rockchip_pinctrl *info = bank->drvdata; 2348 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2349 struct regmap *regmap; 2350 int reg, ret, i, pull_type; 2351 u8 bit; 2352 u32 data, rmask; 2353 2354 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 2355 bank->bank_num, pin_num, pull); 2356 2357 /* rk3066b does support any pulls */ 2358 if (ctrl->type == RK3066B) 2359 return pull ? -EINVAL : 0; 2360 2361 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2362 2363 switch (ctrl->type) { 2364 case RK2928: 2365 case RK3128: 2366 data = BIT(bit + 16); 2367 if (pull == PIN_CONFIG_BIAS_DISABLE) 2368 data |= BIT(bit); 2369 ret = regmap_write(regmap, reg, data); 2370 break; 2371 case PX30: 2372 case RV1108: 2373 case RK3188: 2374 case RK3288: 2375 case RK3308: 2376 case RK3368: 2377 case RK3399: 2378 pull_type = bank->pull_type[pin_num / 8]; 2379 ret = -EINVAL; 2380 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2381 i++) { 2382 if (rockchip_pull_list[pull_type][i] == pull) { 2383 ret = i; 2384 break; 2385 } 2386 } 2387 2388 if (ret < 0) { 2389 dev_err(info->dev, "unsupported pull setting %d\n", 2390 pull); 2391 return ret; 2392 } 2393 2394 /* enable the write to the equivalent lower bits */ 2395 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2396 rmask = data | (data >> 16); 2397 data |= (ret << bit); 2398 2399 ret = regmap_update_bits(regmap, reg, rmask, data); 2400 break; 2401 default: 2402 dev_err(info->dev, "unsupported pinctrl type\n"); 2403 return -EINVAL; 2404 } 2405 2406 return ret; 2407 } 2408 2409 #define RK3328_SCHMITT_BITS_PER_PIN 1 2410 #define RK3328_SCHMITT_PINS_PER_REG 16 2411 #define RK3328_SCHMITT_BANK_STRIDE 8 2412 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2413 2414 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2415 int pin_num, 2416 struct regmap **regmap, 2417 int *reg, u8 *bit) 2418 { 2419 struct rockchip_pinctrl *info = bank->drvdata; 2420 2421 *regmap = info->regmap_base; 2422 *reg = RK3328_SCHMITT_GRF_OFFSET; 2423 2424 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2425 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2426 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2427 2428 return 0; 2429 } 2430 2431 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2432 { 2433 struct rockchip_pinctrl *info = bank->drvdata; 2434 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2435 struct regmap *regmap; 2436 int reg, ret; 2437 u8 bit; 2438 u32 data; 2439 2440 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2441 if (ret) 2442 return ret; 2443 2444 ret = regmap_read(regmap, reg, &data); 2445 if (ret) 2446 return ret; 2447 2448 data >>= bit; 2449 return data & 0x1; 2450 } 2451 2452 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2453 int pin_num, int enable) 2454 { 2455 struct rockchip_pinctrl *info = bank->drvdata; 2456 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2457 struct regmap *regmap; 2458 int reg, ret; 2459 u8 bit; 2460 u32 data, rmask; 2461 2462 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", 2463 bank->bank_num, pin_num, enable); 2464 2465 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2466 if (ret) 2467 return ret; 2468 2469 /* enable the write to the equivalent lower bits */ 2470 data = BIT(bit + 16) | (enable << bit); 2471 rmask = BIT(bit + 16) | BIT(bit); 2472 2473 return regmap_update_bits(regmap, reg, rmask, data); 2474 } 2475 2476 /* 2477 * Pinmux_ops handling 2478 */ 2479 2480 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2481 { 2482 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2483 2484 return info->nfunctions; 2485 } 2486 2487 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2488 unsigned selector) 2489 { 2490 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2491 2492 return info->functions[selector].name; 2493 } 2494 2495 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2496 unsigned selector, const char * const **groups, 2497 unsigned * const num_groups) 2498 { 2499 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2500 2501 *groups = info->functions[selector].groups; 2502 *num_groups = info->functions[selector].ngroups; 2503 2504 return 0; 2505 } 2506 2507 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2508 unsigned group) 2509 { 2510 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2511 const unsigned int *pins = info->groups[group].pins; 2512 const struct rockchip_pin_config *data = info->groups[group].data; 2513 struct rockchip_pin_bank *bank; 2514 int cnt, ret = 0; 2515 2516 dev_dbg(info->dev, "enable function %s group %s\n", 2517 info->functions[selector].name, info->groups[group].name); 2518 2519 /* 2520 * for each pin in the pin group selected, program the corresponding 2521 * pin function number in the config register. 2522 */ 2523 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2524 bank = pin_to_bank(info, pins[cnt]); 2525 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2526 data[cnt].func); 2527 if (ret) 2528 break; 2529 } 2530 2531 if (ret) { 2532 /* revert the already done pin settings */ 2533 for (cnt--; cnt >= 0; cnt--) 2534 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2535 2536 return ret; 2537 } 2538 2539 return 0; 2540 } 2541 2542 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 2543 { 2544 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 2545 u32 data; 2546 int ret; 2547 2548 ret = clk_enable(bank->clk); 2549 if (ret < 0) { 2550 dev_err(bank->drvdata->dev, 2551 "failed to enable clock for bank %s\n", bank->name); 2552 return ret; 2553 } 2554 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2555 clk_disable(bank->clk); 2556 2557 if (data & BIT(offset)) 2558 return GPIO_LINE_DIRECTION_OUT; 2559 2560 return GPIO_LINE_DIRECTION_IN; 2561 } 2562 2563 /* 2564 * The calls to gpio_direction_output() and gpio_direction_input() 2565 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 2566 * function called from the gpiolib interface). 2567 */ 2568 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 2569 int pin, bool input) 2570 { 2571 struct rockchip_pin_bank *bank; 2572 int ret; 2573 unsigned long flags; 2574 u32 data; 2575 2576 bank = gpiochip_get_data(chip); 2577 2578 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 2579 if (ret < 0) 2580 return ret; 2581 2582 clk_enable(bank->clk); 2583 raw_spin_lock_irqsave(&bank->slock, flags); 2584 2585 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2586 /* set bit to 1 for output, 0 for input */ 2587 if (!input) 2588 data |= BIT(pin); 2589 else 2590 data &= ~BIT(pin); 2591 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2592 2593 raw_spin_unlock_irqrestore(&bank->slock, flags); 2594 clk_disable(bank->clk); 2595 2596 return 0; 2597 } 2598 2599 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 2600 struct pinctrl_gpio_range *range, 2601 unsigned offset, bool input) 2602 { 2603 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2604 struct gpio_chip *chip; 2605 int pin; 2606 2607 chip = range->gc; 2608 pin = offset - chip->base; 2609 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 2610 offset, range->name, pin, input ? "input" : "output"); 2611 2612 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 2613 input); 2614 } 2615 2616 static const struct pinmux_ops rockchip_pmx_ops = { 2617 .get_functions_count = rockchip_pmx_get_funcs_count, 2618 .get_function_name = rockchip_pmx_get_func_name, 2619 .get_function_groups = rockchip_pmx_get_groups, 2620 .set_mux = rockchip_pmx_set, 2621 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 2622 }; 2623 2624 /* 2625 * Pinconf_ops handling 2626 */ 2627 2628 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2629 enum pin_config_param pull) 2630 { 2631 switch (ctrl->type) { 2632 case RK2928: 2633 case RK3128: 2634 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2635 pull == PIN_CONFIG_BIAS_DISABLE); 2636 case RK3066B: 2637 return pull ? false : true; 2638 case PX30: 2639 case RV1108: 2640 case RK3188: 2641 case RK3288: 2642 case RK3308: 2643 case RK3368: 2644 case RK3399: 2645 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2646 } 2647 2648 return false; 2649 } 2650 2651 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 2652 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 2653 2654 /* set the pin config settings for a specified pin */ 2655 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2656 unsigned long *configs, unsigned num_configs) 2657 { 2658 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2659 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2660 enum pin_config_param param; 2661 u32 arg; 2662 int i; 2663 int rc; 2664 2665 for (i = 0; i < num_configs; i++) { 2666 param = pinconf_to_config_param(configs[i]); 2667 arg = pinconf_to_config_argument(configs[i]); 2668 2669 switch (param) { 2670 case PIN_CONFIG_BIAS_DISABLE: 2671 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2672 param); 2673 if (rc) 2674 return rc; 2675 break; 2676 case PIN_CONFIG_BIAS_PULL_UP: 2677 case PIN_CONFIG_BIAS_PULL_DOWN: 2678 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2679 case PIN_CONFIG_BIAS_BUS_HOLD: 2680 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2681 return -ENOTSUPP; 2682 2683 if (!arg) 2684 return -EINVAL; 2685 2686 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2687 param); 2688 if (rc) 2689 return rc; 2690 break; 2691 case PIN_CONFIG_OUTPUT: 2692 rockchip_gpio_set(&bank->gpio_chip, 2693 pin - bank->pin_base, arg); 2694 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 2695 pin - bank->pin_base, false); 2696 if (rc) 2697 return rc; 2698 break; 2699 case PIN_CONFIG_DRIVE_STRENGTH: 2700 /* rk3288 is the first with per-pin drive-strength */ 2701 if (!info->ctrl->drv_calc_reg) 2702 return -ENOTSUPP; 2703 2704 rc = rockchip_set_drive_perpin(bank, 2705 pin - bank->pin_base, arg); 2706 if (rc < 0) 2707 return rc; 2708 break; 2709 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2710 if (!info->ctrl->schmitt_calc_reg) 2711 return -ENOTSUPP; 2712 2713 rc = rockchip_set_schmitt(bank, 2714 pin - bank->pin_base, arg); 2715 if (rc < 0) 2716 return rc; 2717 break; 2718 default: 2719 return -ENOTSUPP; 2720 break; 2721 } 2722 } /* for each config */ 2723 2724 return 0; 2725 } 2726 2727 /* get the pin config settings for a specified pin */ 2728 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2729 unsigned long *config) 2730 { 2731 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2732 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2733 enum pin_config_param param = pinconf_to_config_param(*config); 2734 u16 arg; 2735 int rc; 2736 2737 switch (param) { 2738 case PIN_CONFIG_BIAS_DISABLE: 2739 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2740 return -EINVAL; 2741 2742 arg = 0; 2743 break; 2744 case PIN_CONFIG_BIAS_PULL_UP: 2745 case PIN_CONFIG_BIAS_PULL_DOWN: 2746 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2747 case PIN_CONFIG_BIAS_BUS_HOLD: 2748 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2749 return -ENOTSUPP; 2750 2751 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2752 return -EINVAL; 2753 2754 arg = 1; 2755 break; 2756 case PIN_CONFIG_OUTPUT: 2757 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2758 if (rc != RK_FUNC_GPIO) 2759 return -EINVAL; 2760 2761 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 2762 if (rc < 0) 2763 return rc; 2764 2765 arg = rc ? 1 : 0; 2766 break; 2767 case PIN_CONFIG_DRIVE_STRENGTH: 2768 /* rk3288 is the first with per-pin drive-strength */ 2769 if (!info->ctrl->drv_calc_reg) 2770 return -ENOTSUPP; 2771 2772 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2773 if (rc < 0) 2774 return rc; 2775 2776 arg = rc; 2777 break; 2778 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2779 if (!info->ctrl->schmitt_calc_reg) 2780 return -ENOTSUPP; 2781 2782 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2783 if (rc < 0) 2784 return rc; 2785 2786 arg = rc; 2787 break; 2788 default: 2789 return -ENOTSUPP; 2790 break; 2791 } 2792 2793 *config = pinconf_to_config_packed(param, arg); 2794 2795 return 0; 2796 } 2797 2798 static const struct pinconf_ops rockchip_pinconf_ops = { 2799 .pin_config_get = rockchip_pinconf_get, 2800 .pin_config_set = rockchip_pinconf_set, 2801 .is_generic = true, 2802 }; 2803 2804 static const struct of_device_id rockchip_bank_match[] = { 2805 { .compatible = "rockchip,gpio-bank" }, 2806 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2807 {}, 2808 }; 2809 2810 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2811 struct device_node *np) 2812 { 2813 struct device_node *child; 2814 2815 for_each_child_of_node(np, child) { 2816 if (of_match_node(rockchip_bank_match, child)) 2817 continue; 2818 2819 info->nfunctions++; 2820 info->ngroups += of_get_child_count(child); 2821 } 2822 } 2823 2824 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2825 struct rockchip_pin_group *grp, 2826 struct rockchip_pinctrl *info, 2827 u32 index) 2828 { 2829 struct rockchip_pin_bank *bank; 2830 int size; 2831 const __be32 *list; 2832 int num; 2833 int i, j; 2834 int ret; 2835 2836 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); 2837 2838 /* Initialise group */ 2839 grp->name = np->name; 2840 2841 /* 2842 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2843 * do sanity check and calculate pins number 2844 */ 2845 list = of_get_property(np, "rockchip,pins", &size); 2846 /* we do not check return since it's safe node passed down */ 2847 size /= sizeof(*list); 2848 if (!size || size % 4) { 2849 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 2850 return -EINVAL; 2851 } 2852 2853 grp->npins = size / 4; 2854 2855 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), 2856 GFP_KERNEL); 2857 grp->data = devm_kcalloc(info->dev, 2858 grp->npins, 2859 sizeof(struct rockchip_pin_config), 2860 GFP_KERNEL); 2861 if (!grp->pins || !grp->data) 2862 return -ENOMEM; 2863 2864 for (i = 0, j = 0; i < size; i += 4, j++) { 2865 const __be32 *phandle; 2866 struct device_node *np_config; 2867 2868 num = be32_to_cpu(*list++); 2869 bank = bank_num_to_bank(info, num); 2870 if (IS_ERR(bank)) 2871 return PTR_ERR(bank); 2872 2873 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2874 grp->data[j].func = be32_to_cpu(*list++); 2875 2876 phandle = list++; 2877 if (!phandle) 2878 return -EINVAL; 2879 2880 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2881 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2882 &grp->data[j].configs, &grp->data[j].nconfigs); 2883 if (ret) 2884 return ret; 2885 } 2886 2887 return 0; 2888 } 2889 2890 static int rockchip_pinctrl_parse_functions(struct device_node *np, 2891 struct rockchip_pinctrl *info, 2892 u32 index) 2893 { 2894 struct device_node *child; 2895 struct rockchip_pmx_func *func; 2896 struct rockchip_pin_group *grp; 2897 int ret; 2898 static u32 grp_index; 2899 u32 i = 0; 2900 2901 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); 2902 2903 func = &info->functions[index]; 2904 2905 /* Initialise function */ 2906 func->name = np->name; 2907 func->ngroups = of_get_child_count(np); 2908 if (func->ngroups <= 0) 2909 return 0; 2910 2911 func->groups = devm_kcalloc(info->dev, 2912 func->ngroups, sizeof(char *), GFP_KERNEL); 2913 if (!func->groups) 2914 return -ENOMEM; 2915 2916 for_each_child_of_node(np, child) { 2917 func->groups[i] = child->name; 2918 grp = &info->groups[grp_index++]; 2919 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 2920 if (ret) { 2921 of_node_put(child); 2922 return ret; 2923 } 2924 } 2925 2926 return 0; 2927 } 2928 2929 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 2930 struct rockchip_pinctrl *info) 2931 { 2932 struct device *dev = &pdev->dev; 2933 struct device_node *np = dev->of_node; 2934 struct device_node *child; 2935 int ret; 2936 int i; 2937 2938 rockchip_pinctrl_child_count(info, np); 2939 2940 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 2941 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 2942 2943 info->functions = devm_kcalloc(dev, 2944 info->nfunctions, 2945 sizeof(struct rockchip_pmx_func), 2946 GFP_KERNEL); 2947 if (!info->functions) 2948 return -ENOMEM; 2949 2950 info->groups = devm_kcalloc(dev, 2951 info->ngroups, 2952 sizeof(struct rockchip_pin_group), 2953 GFP_KERNEL); 2954 if (!info->groups) 2955 return -ENOMEM; 2956 2957 i = 0; 2958 2959 for_each_child_of_node(np, child) { 2960 if (of_match_node(rockchip_bank_match, child)) 2961 continue; 2962 2963 ret = rockchip_pinctrl_parse_functions(child, info, i++); 2964 if (ret) { 2965 dev_err(&pdev->dev, "failed to parse function\n"); 2966 of_node_put(child); 2967 return ret; 2968 } 2969 } 2970 2971 return 0; 2972 } 2973 2974 static int rockchip_pinctrl_register(struct platform_device *pdev, 2975 struct rockchip_pinctrl *info) 2976 { 2977 struct pinctrl_desc *ctrldesc = &info->pctl; 2978 struct pinctrl_pin_desc *pindesc, *pdesc; 2979 struct rockchip_pin_bank *pin_bank; 2980 int pin, bank, ret; 2981 int k; 2982 2983 ctrldesc->name = "rockchip-pinctrl"; 2984 ctrldesc->owner = THIS_MODULE; 2985 ctrldesc->pctlops = &rockchip_pctrl_ops; 2986 ctrldesc->pmxops = &rockchip_pmx_ops; 2987 ctrldesc->confops = &rockchip_pinconf_ops; 2988 2989 pindesc = devm_kcalloc(&pdev->dev, 2990 info->ctrl->nr_pins, sizeof(*pindesc), 2991 GFP_KERNEL); 2992 if (!pindesc) 2993 return -ENOMEM; 2994 2995 ctrldesc->pins = pindesc; 2996 ctrldesc->npins = info->ctrl->nr_pins; 2997 2998 pdesc = pindesc; 2999 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 3000 pin_bank = &info->ctrl->pin_banks[bank]; 3001 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 3002 pdesc->number = k; 3003 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 3004 pin_bank->name, pin); 3005 pdesc++; 3006 } 3007 } 3008 3009 ret = rockchip_pinctrl_parse_dt(pdev, info); 3010 if (ret) 3011 return ret; 3012 3013 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 3014 if (IS_ERR(info->pctl_dev)) { 3015 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 3016 return PTR_ERR(info->pctl_dev); 3017 } 3018 3019 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 3020 pin_bank = &info->ctrl->pin_banks[bank]; 3021 pin_bank->grange.name = pin_bank->name; 3022 pin_bank->grange.id = bank; 3023 pin_bank->grange.pin_base = pin_bank->pin_base; 3024 pin_bank->grange.base = pin_bank->gpio_chip.base; 3025 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 3026 pin_bank->grange.gc = &pin_bank->gpio_chip; 3027 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 3028 } 3029 3030 return 0; 3031 } 3032 3033 /* 3034 * GPIO handling 3035 */ 3036 3037 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 3038 { 3039 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 3040 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 3041 unsigned long flags; 3042 u32 data; 3043 3044 clk_enable(bank->clk); 3045 raw_spin_lock_irqsave(&bank->slock, flags); 3046 3047 data = readl(reg); 3048 data &= ~BIT(offset); 3049 if (value) 3050 data |= BIT(offset); 3051 writel(data, reg); 3052 3053 raw_spin_unlock_irqrestore(&bank->slock, flags); 3054 clk_disable(bank->clk); 3055 } 3056 3057 /* 3058 * Returns the level of the pin for input direction and setting of the DR 3059 * register for output gpios. 3060 */ 3061 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 3062 { 3063 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 3064 u32 data; 3065 3066 clk_enable(bank->clk); 3067 data = readl(bank->reg_base + GPIO_EXT_PORT); 3068 clk_disable(bank->clk); 3069 data >>= offset; 3070 data &= 1; 3071 return data; 3072 } 3073 3074 /* 3075 * gpiolib gpio_direction_input callback function. The setting of the pin 3076 * mux function as 'gpio input' will be handled by the pinctrl subsystem 3077 * interface. 3078 */ 3079 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 3080 { 3081 return pinctrl_gpio_direction_input(gc->base + offset); 3082 } 3083 3084 /* 3085 * gpiolib gpio_direction_output callback function. The setting of the pin 3086 * mux function as 'gpio output' will be handled by the pinctrl subsystem 3087 * interface. 3088 */ 3089 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 3090 unsigned offset, int value) 3091 { 3092 rockchip_gpio_set(gc, offset, value); 3093 return pinctrl_gpio_direction_output(gc->base + offset); 3094 } 3095 3096 static void rockchip_gpio_set_debounce(struct gpio_chip *gc, 3097 unsigned int offset, bool enable) 3098 { 3099 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 3100 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; 3101 unsigned long flags; 3102 u32 data; 3103 3104 clk_enable(bank->clk); 3105 raw_spin_lock_irqsave(&bank->slock, flags); 3106 3107 data = readl(reg); 3108 if (enable) 3109 data |= BIT(offset); 3110 else 3111 data &= ~BIT(offset); 3112 writel(data, reg); 3113 3114 raw_spin_unlock_irqrestore(&bank->slock, flags); 3115 clk_disable(bank->clk); 3116 } 3117 3118 /* 3119 * gpiolib set_config callback function. The setting of the pin 3120 * mux function as 'gpio output' will be handled by the pinctrl subsystem 3121 * interface. 3122 */ 3123 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 3124 unsigned long config) 3125 { 3126 enum pin_config_param param = pinconf_to_config_param(config); 3127 3128 switch (param) { 3129 case PIN_CONFIG_INPUT_DEBOUNCE: 3130 rockchip_gpio_set_debounce(gc, offset, true); 3131 /* 3132 * Rockchip's gpio could only support up to one period 3133 * of the debounce clock(pclk), which is far away from 3134 * satisftying the requirement, as pclk is usually near 3135 * 100MHz shared by all peripherals. So the fact is it 3136 * has crippled debounce capability could only be useful 3137 * to prevent any spurious glitches from waking up the system 3138 * if the gpio is conguired as wakeup interrupt source. Let's 3139 * still return -ENOTSUPP as before, to make sure the caller 3140 * of gpiod_set_debounce won't change its behaviour. 3141 */ 3142 return -ENOTSUPP; 3143 default: 3144 return -ENOTSUPP; 3145 } 3146 } 3147 3148 /* 3149 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 3150 * and a virtual IRQ, if not already present. 3151 */ 3152 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 3153 { 3154 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 3155 unsigned int virq; 3156 3157 if (!bank->domain) 3158 return -ENXIO; 3159 3160 clk_enable(bank->clk); 3161 virq = irq_create_mapping(bank->domain, offset); 3162 clk_disable(bank->clk); 3163 3164 return (virq) ? : -ENXIO; 3165 } 3166 3167 static const struct gpio_chip rockchip_gpiolib_chip = { 3168 .request = gpiochip_generic_request, 3169 .free = gpiochip_generic_free, 3170 .set = rockchip_gpio_set, 3171 .get = rockchip_gpio_get, 3172 .get_direction = rockchip_gpio_get_direction, 3173 .direction_input = rockchip_gpio_direction_input, 3174 .direction_output = rockchip_gpio_direction_output, 3175 .set_config = rockchip_gpio_set_config, 3176 .to_irq = rockchip_gpio_to_irq, 3177 .owner = THIS_MODULE, 3178 }; 3179 3180 /* 3181 * Interrupt handling 3182 */ 3183 3184 static void rockchip_irq_demux(struct irq_desc *desc) 3185 { 3186 struct irq_chip *chip = irq_desc_get_chip(desc); 3187 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 3188 u32 pend; 3189 3190 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 3191 3192 chained_irq_enter(chip, desc); 3193 3194 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 3195 3196 while (pend) { 3197 unsigned int irq, virq; 3198 3199 irq = __ffs(pend); 3200 pend &= ~BIT(irq); 3201 virq = irq_find_mapping(bank->domain, irq); 3202 3203 if (!virq) { 3204 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 3205 continue; 3206 } 3207 3208 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 3209 3210 /* 3211 * Triggering IRQ on both rising and falling edge 3212 * needs manual intervention. 3213 */ 3214 if (bank->toggle_edge_mode & BIT(irq)) { 3215 u32 data, data_old, polarity; 3216 unsigned long flags; 3217 3218 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 3219 do { 3220 raw_spin_lock_irqsave(&bank->slock, flags); 3221 3222 polarity = readl_relaxed(bank->reg_base + 3223 GPIO_INT_POLARITY); 3224 if (data & BIT(irq)) 3225 polarity &= ~BIT(irq); 3226 else 3227 polarity |= BIT(irq); 3228 writel(polarity, 3229 bank->reg_base + GPIO_INT_POLARITY); 3230 3231 raw_spin_unlock_irqrestore(&bank->slock, flags); 3232 3233 data_old = data; 3234 data = readl_relaxed(bank->reg_base + 3235 GPIO_EXT_PORT); 3236 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 3237 } 3238 3239 generic_handle_irq(virq); 3240 } 3241 3242 chained_irq_exit(chip, desc); 3243 } 3244 3245 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 3246 { 3247 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3248 struct rockchip_pin_bank *bank = gc->private; 3249 u32 mask = BIT(d->hwirq); 3250 u32 polarity; 3251 u32 level; 3252 u32 data; 3253 unsigned long flags; 3254 int ret; 3255 3256 /* make sure the pin is configured as gpio input */ 3257 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 3258 if (ret < 0) 3259 return ret; 3260 3261 clk_enable(bank->clk); 3262 raw_spin_lock_irqsave(&bank->slock, flags); 3263 3264 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 3265 data &= ~mask; 3266 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 3267 3268 raw_spin_unlock_irqrestore(&bank->slock, flags); 3269 3270 if (type & IRQ_TYPE_EDGE_BOTH) 3271 irq_set_handler_locked(d, handle_edge_irq); 3272 else 3273 irq_set_handler_locked(d, handle_level_irq); 3274 3275 raw_spin_lock_irqsave(&bank->slock, flags); 3276 irq_gc_lock(gc); 3277 3278 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 3279 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 3280 3281 switch (type) { 3282 case IRQ_TYPE_EDGE_BOTH: 3283 bank->toggle_edge_mode |= mask; 3284 level |= mask; 3285 3286 /* 3287 * Determine gpio state. If 1 next interrupt should be falling 3288 * otherwise rising. 3289 */ 3290 data = readl(bank->reg_base + GPIO_EXT_PORT); 3291 if (data & mask) 3292 polarity &= ~mask; 3293 else 3294 polarity |= mask; 3295 break; 3296 case IRQ_TYPE_EDGE_RISING: 3297 bank->toggle_edge_mode &= ~mask; 3298 level |= mask; 3299 polarity |= mask; 3300 break; 3301 case IRQ_TYPE_EDGE_FALLING: 3302 bank->toggle_edge_mode &= ~mask; 3303 level |= mask; 3304 polarity &= ~mask; 3305 break; 3306 case IRQ_TYPE_LEVEL_HIGH: 3307 bank->toggle_edge_mode &= ~mask; 3308 level &= ~mask; 3309 polarity |= mask; 3310 break; 3311 case IRQ_TYPE_LEVEL_LOW: 3312 bank->toggle_edge_mode &= ~mask; 3313 level &= ~mask; 3314 polarity &= ~mask; 3315 break; 3316 default: 3317 irq_gc_unlock(gc); 3318 raw_spin_unlock_irqrestore(&bank->slock, flags); 3319 clk_disable(bank->clk); 3320 return -EINVAL; 3321 } 3322 3323 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 3324 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 3325 3326 irq_gc_unlock(gc); 3327 raw_spin_unlock_irqrestore(&bank->slock, flags); 3328 clk_disable(bank->clk); 3329 3330 return 0; 3331 } 3332 3333 static void rockchip_irq_suspend(struct irq_data *d) 3334 { 3335 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3336 struct rockchip_pin_bank *bank = gc->private; 3337 3338 clk_enable(bank->clk); 3339 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 3340 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 3341 clk_disable(bank->clk); 3342 } 3343 3344 static void rockchip_irq_resume(struct irq_data *d) 3345 { 3346 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3347 struct rockchip_pin_bank *bank = gc->private; 3348 3349 clk_enable(bank->clk); 3350 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 3351 clk_disable(bank->clk); 3352 } 3353 3354 static void rockchip_irq_enable(struct irq_data *d) 3355 { 3356 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3357 struct rockchip_pin_bank *bank = gc->private; 3358 3359 clk_enable(bank->clk); 3360 irq_gc_mask_clr_bit(d); 3361 } 3362 3363 static void rockchip_irq_disable(struct irq_data *d) 3364 { 3365 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3366 struct rockchip_pin_bank *bank = gc->private; 3367 3368 irq_gc_mask_set_bit(d); 3369 clk_disable(bank->clk); 3370 } 3371 3372 static int rockchip_interrupts_register(struct platform_device *pdev, 3373 struct rockchip_pinctrl *info) 3374 { 3375 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3376 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3377 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 3378 struct irq_chip_generic *gc; 3379 int ret; 3380 int i; 3381 3382 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3383 if (!bank->valid) { 3384 dev_warn(&pdev->dev, "bank %s is not valid\n", 3385 bank->name); 3386 continue; 3387 } 3388 3389 ret = clk_enable(bank->clk); 3390 if (ret) { 3391 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 3392 bank->name); 3393 continue; 3394 } 3395 3396 bank->domain = irq_domain_add_linear(bank->of_node, 32, 3397 &irq_generic_chip_ops, NULL); 3398 if (!bank->domain) { 3399 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 3400 bank->name); 3401 clk_disable(bank->clk); 3402 continue; 3403 } 3404 3405 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 3406 "rockchip_gpio_irq", handle_level_irq, 3407 clr, 0, 0); 3408 if (ret) { 3409 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 3410 bank->name); 3411 irq_domain_remove(bank->domain); 3412 clk_disable(bank->clk); 3413 continue; 3414 } 3415 3416 gc = irq_get_domain_generic_chip(bank->domain, 0); 3417 gc->reg_base = bank->reg_base; 3418 gc->private = bank; 3419 gc->chip_types[0].regs.mask = GPIO_INTMASK; 3420 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 3421 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 3422 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 3423 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 3424 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 3425 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 3426 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 3427 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 3428 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 3429 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 3430 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 3431 3432 /* 3433 * Linux assumes that all interrupts start out disabled/masked. 3434 * Our driver only uses the concept of masked and always keeps 3435 * things enabled, so for us that's all masked and all enabled. 3436 */ 3437 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 3438 writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI); 3439 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 3440 gc->mask_cache = 0xffffffff; 3441 3442 irq_set_chained_handler_and_data(bank->irq, 3443 rockchip_irq_demux, bank); 3444 clk_disable(bank->clk); 3445 } 3446 3447 return 0; 3448 } 3449 3450 static int rockchip_gpiolib_register(struct platform_device *pdev, 3451 struct rockchip_pinctrl *info) 3452 { 3453 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3454 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3455 struct gpio_chip *gc; 3456 int ret; 3457 int i; 3458 3459 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3460 if (!bank->valid) { 3461 dev_warn(&pdev->dev, "bank %s is not valid\n", 3462 bank->name); 3463 continue; 3464 } 3465 3466 bank->gpio_chip = rockchip_gpiolib_chip; 3467 3468 gc = &bank->gpio_chip; 3469 gc->base = bank->pin_base; 3470 gc->ngpio = bank->nr_pins; 3471 gc->parent = &pdev->dev; 3472 gc->of_node = bank->of_node; 3473 gc->label = bank->name; 3474 3475 ret = gpiochip_add_data(gc, bank); 3476 if (ret) { 3477 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 3478 gc->label, ret); 3479 goto fail; 3480 } 3481 } 3482 3483 rockchip_interrupts_register(pdev, info); 3484 3485 return 0; 3486 3487 fail: 3488 for (--i, --bank; i >= 0; --i, --bank) { 3489 if (!bank->valid) 3490 continue; 3491 gpiochip_remove(&bank->gpio_chip); 3492 } 3493 return ret; 3494 } 3495 3496 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 3497 struct rockchip_pinctrl *info) 3498 { 3499 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3500 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3501 int i; 3502 3503 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3504 if (!bank->valid) 3505 continue; 3506 gpiochip_remove(&bank->gpio_chip); 3507 } 3508 3509 return 0; 3510 } 3511 3512 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 3513 struct rockchip_pinctrl *info) 3514 { 3515 struct resource res; 3516 void __iomem *base; 3517 3518 if (of_address_to_resource(bank->of_node, 0, &res)) { 3519 dev_err(info->dev, "cannot find IO resource for bank\n"); 3520 return -ENOENT; 3521 } 3522 3523 bank->reg_base = devm_ioremap_resource(info->dev, &res); 3524 if (IS_ERR(bank->reg_base)) 3525 return PTR_ERR(bank->reg_base); 3526 3527 /* 3528 * special case, where parts of the pull setting-registers are 3529 * part of the PMU register space 3530 */ 3531 if (of_device_is_compatible(bank->of_node, 3532 "rockchip,rk3188-gpio-bank0")) { 3533 struct device_node *node; 3534 3535 node = of_parse_phandle(bank->of_node->parent, 3536 "rockchip,pmu", 0); 3537 if (!node) { 3538 if (of_address_to_resource(bank->of_node, 1, &res)) { 3539 dev_err(info->dev, "cannot find IO resource for bank\n"); 3540 return -ENOENT; 3541 } 3542 3543 base = devm_ioremap_resource(info->dev, &res); 3544 if (IS_ERR(base)) 3545 return PTR_ERR(base); 3546 rockchip_regmap_config.max_register = 3547 resource_size(&res) - 4; 3548 rockchip_regmap_config.name = 3549 "rockchip,rk3188-gpio-bank0-pull"; 3550 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 3551 base, 3552 &rockchip_regmap_config); 3553 } 3554 of_node_put(node); 3555 } 3556 3557 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 3558 3559 bank->clk = of_clk_get(bank->of_node, 0); 3560 if (IS_ERR(bank->clk)) 3561 return PTR_ERR(bank->clk); 3562 3563 return clk_prepare(bank->clk); 3564 } 3565 3566 static const struct of_device_id rockchip_pinctrl_dt_match[]; 3567 3568 /* retrieve the soc specific data */ 3569 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 3570 struct rockchip_pinctrl *d, 3571 struct platform_device *pdev) 3572 { 3573 const struct of_device_id *match; 3574 struct device_node *node = pdev->dev.of_node; 3575 struct device_node *np; 3576 struct rockchip_pin_ctrl *ctrl; 3577 struct rockchip_pin_bank *bank; 3578 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3579 3580 match = of_match_node(rockchip_pinctrl_dt_match, node); 3581 ctrl = (struct rockchip_pin_ctrl *)match->data; 3582 3583 for_each_child_of_node(node, np) { 3584 if (!of_find_property(np, "gpio-controller", NULL)) 3585 continue; 3586 3587 bank = ctrl->pin_banks; 3588 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3589 if (!strcmp(bank->name, np->name)) { 3590 bank->of_node = np; 3591 3592 if (!rockchip_get_bank_data(bank, d)) 3593 bank->valid = true; 3594 3595 break; 3596 } 3597 } 3598 } 3599 3600 grf_offs = ctrl->grf_mux_offset; 3601 pmu_offs = ctrl->pmu_mux_offset; 3602 drv_pmu_offs = ctrl->pmu_drv_offset; 3603 drv_grf_offs = ctrl->grf_drv_offset; 3604 bank = ctrl->pin_banks; 3605 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3606 int bank_pins = 0; 3607 3608 raw_spin_lock_init(&bank->slock); 3609 bank->drvdata = d; 3610 bank->pin_base = ctrl->nr_pins; 3611 ctrl->nr_pins += bank->nr_pins; 3612 3613 /* calculate iomux and drv offsets */ 3614 for (j = 0; j < 4; j++) { 3615 struct rockchip_iomux *iom = &bank->iomux[j]; 3616 struct rockchip_drv *drv = &bank->drv[j]; 3617 int inc; 3618 3619 if (bank_pins >= bank->nr_pins) 3620 break; 3621 3622 /* preset iomux offset value, set new start value */ 3623 if (iom->offset >= 0) { 3624 if (iom->type & IOMUX_SOURCE_PMU) 3625 pmu_offs = iom->offset; 3626 else 3627 grf_offs = iom->offset; 3628 } else { /* set current iomux offset */ 3629 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3630 pmu_offs : grf_offs; 3631 } 3632 3633 /* preset drv offset value, set new start value */ 3634 if (drv->offset >= 0) { 3635 if (iom->type & IOMUX_SOURCE_PMU) 3636 drv_pmu_offs = drv->offset; 3637 else 3638 drv_grf_offs = drv->offset; 3639 } else { /* set current drv offset */ 3640 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3641 drv_pmu_offs : drv_grf_offs; 3642 } 3643 3644 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3645 i, j, iom->offset, drv->offset); 3646 3647 /* 3648 * Increase offset according to iomux width. 3649 * 4bit iomux'es are spread over two registers. 3650 */ 3651 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3652 IOMUX_WIDTH_3BIT | 3653 IOMUX_WIDTH_2BIT)) ? 8 : 4; 3654 if (iom->type & IOMUX_SOURCE_PMU) 3655 pmu_offs += inc; 3656 else 3657 grf_offs += inc; 3658 3659 /* 3660 * Increase offset according to drv width. 3661 * 3bit drive-strenth'es are spread over two registers. 3662 */ 3663 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3664 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3665 inc = 8; 3666 else 3667 inc = 4; 3668 3669 if (iom->type & IOMUX_SOURCE_PMU) 3670 drv_pmu_offs += inc; 3671 else 3672 drv_grf_offs += inc; 3673 3674 bank_pins += 8; 3675 } 3676 3677 /* calculate the per-bank recalced_mask */ 3678 for (j = 0; j < ctrl->niomux_recalced; j++) { 3679 int pin = 0; 3680 3681 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3682 pin = ctrl->iomux_recalced[j].pin; 3683 bank->recalced_mask |= BIT(pin); 3684 } 3685 } 3686 3687 /* calculate the per-bank route_mask */ 3688 for (j = 0; j < ctrl->niomux_routes; j++) { 3689 int pin = 0; 3690 3691 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3692 pin = ctrl->iomux_routes[j].pin; 3693 bank->route_mask |= BIT(pin); 3694 } 3695 } 3696 } 3697 3698 return ctrl; 3699 } 3700 3701 #define RK3288_GRF_GPIO6C_IOMUX 0x64 3702 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3703 3704 static u32 rk3288_grf_gpio6c_iomux; 3705 3706 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3707 { 3708 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3709 int ret = pinctrl_force_sleep(info->pctl_dev); 3710 3711 if (ret) 3712 return ret; 3713 3714 /* 3715 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3716 * the setting here, and restore it at resume. 3717 */ 3718 if (info->ctrl->type == RK3288) { 3719 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3720 &rk3288_grf_gpio6c_iomux); 3721 if (ret) { 3722 pinctrl_force_default(info->pctl_dev); 3723 return ret; 3724 } 3725 } 3726 3727 return 0; 3728 } 3729 3730 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3731 { 3732 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3733 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3734 rk3288_grf_gpio6c_iomux | 3735 GPIO6C6_SEL_WRITE_ENABLE); 3736 3737 if (ret) 3738 return ret; 3739 3740 return pinctrl_force_default(info->pctl_dev); 3741 } 3742 3743 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3744 rockchip_pinctrl_resume); 3745 3746 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3747 { 3748 struct rockchip_pinctrl *info; 3749 struct device *dev = &pdev->dev; 3750 struct rockchip_pin_ctrl *ctrl; 3751 struct device_node *np = pdev->dev.of_node, *node; 3752 struct resource *res; 3753 void __iomem *base; 3754 int ret; 3755 3756 if (!dev->of_node) { 3757 dev_err(dev, "device tree node not found\n"); 3758 return -ENODEV; 3759 } 3760 3761 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3762 if (!info) 3763 return -ENOMEM; 3764 3765 info->dev = dev; 3766 3767 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3768 if (!ctrl) { 3769 dev_err(dev, "driver data not available\n"); 3770 return -EINVAL; 3771 } 3772 info->ctrl = ctrl; 3773 3774 node = of_parse_phandle(np, "rockchip,grf", 0); 3775 if (node) { 3776 info->regmap_base = syscon_node_to_regmap(node); 3777 if (IS_ERR(info->regmap_base)) 3778 return PTR_ERR(info->regmap_base); 3779 } else { 3780 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3781 base = devm_ioremap_resource(&pdev->dev, res); 3782 if (IS_ERR(base)) 3783 return PTR_ERR(base); 3784 3785 rockchip_regmap_config.max_register = resource_size(res) - 4; 3786 rockchip_regmap_config.name = "rockchip,pinctrl"; 3787 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 3788 &rockchip_regmap_config); 3789 3790 /* to check for the old dt-bindings */ 3791 info->reg_size = resource_size(res); 3792 3793 /* Honor the old binding, with pull registers as 2nd resource */ 3794 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3795 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3796 base = devm_ioremap_resource(&pdev->dev, res); 3797 if (IS_ERR(base)) 3798 return PTR_ERR(base); 3799 3800 rockchip_regmap_config.max_register = 3801 resource_size(res) - 4; 3802 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3803 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 3804 base, 3805 &rockchip_regmap_config); 3806 } 3807 } 3808 3809 /* try to find the optional reference to the pmu syscon */ 3810 node = of_parse_phandle(np, "rockchip,pmu", 0); 3811 if (node) { 3812 info->regmap_pmu = syscon_node_to_regmap(node); 3813 if (IS_ERR(info->regmap_pmu)) 3814 return PTR_ERR(info->regmap_pmu); 3815 } 3816 3817 ret = rockchip_gpiolib_register(pdev, info); 3818 if (ret) 3819 return ret; 3820 3821 ret = rockchip_pinctrl_register(pdev, info); 3822 if (ret) { 3823 rockchip_gpiolib_unregister(pdev, info); 3824 return ret; 3825 } 3826 3827 platform_set_drvdata(pdev, info); 3828 3829 return 0; 3830 } 3831 3832 static struct rockchip_pin_bank px30_pin_banks[] = { 3833 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3834 IOMUX_SOURCE_PMU, 3835 IOMUX_SOURCE_PMU, 3836 IOMUX_SOURCE_PMU 3837 ), 3838 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3839 IOMUX_WIDTH_4BIT, 3840 IOMUX_WIDTH_4BIT, 3841 IOMUX_WIDTH_4BIT 3842 ), 3843 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3844 IOMUX_WIDTH_4BIT, 3845 IOMUX_WIDTH_4BIT, 3846 IOMUX_WIDTH_4BIT 3847 ), 3848 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3849 IOMUX_WIDTH_4BIT, 3850 IOMUX_WIDTH_4BIT, 3851 IOMUX_WIDTH_4BIT 3852 ), 3853 }; 3854 3855 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3856 .pin_banks = px30_pin_banks, 3857 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3858 .label = "PX30-GPIO", 3859 .type = PX30, 3860 .grf_mux_offset = 0x0, 3861 .pmu_mux_offset = 0x0, 3862 .iomux_routes = px30_mux_route_data, 3863 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3864 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3865 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3866 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3867 }; 3868 3869 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3870 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3871 IOMUX_SOURCE_PMU, 3872 IOMUX_SOURCE_PMU, 3873 IOMUX_SOURCE_PMU), 3874 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3875 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3876 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3877 }; 3878 3879 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3880 .pin_banks = rv1108_pin_banks, 3881 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3882 .label = "RV1108-GPIO", 3883 .type = RV1108, 3884 .grf_mux_offset = 0x10, 3885 .pmu_mux_offset = 0x0, 3886 .iomux_recalced = rv1108_mux_recalced_data, 3887 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3888 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3889 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3890 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3891 }; 3892 3893 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3894 PIN_BANK(0, 32, "gpio0"), 3895 PIN_BANK(1, 32, "gpio1"), 3896 PIN_BANK(2, 32, "gpio2"), 3897 PIN_BANK(3, 32, "gpio3"), 3898 }; 3899 3900 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3901 .pin_banks = rk2928_pin_banks, 3902 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3903 .label = "RK2928-GPIO", 3904 .type = RK2928, 3905 .grf_mux_offset = 0xa8, 3906 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3907 }; 3908 3909 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3910 PIN_BANK(0, 32, "gpio0"), 3911 PIN_BANK(1, 32, "gpio1"), 3912 PIN_BANK(2, 32, "gpio2"), 3913 }; 3914 3915 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3916 .pin_banks = rk3036_pin_banks, 3917 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3918 .label = "RK3036-GPIO", 3919 .type = RK2928, 3920 .grf_mux_offset = 0xa8, 3921 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3922 }; 3923 3924 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3925 PIN_BANK(0, 32, "gpio0"), 3926 PIN_BANK(1, 32, "gpio1"), 3927 PIN_BANK(2, 32, "gpio2"), 3928 PIN_BANK(3, 32, "gpio3"), 3929 PIN_BANK(4, 32, "gpio4"), 3930 PIN_BANK(6, 16, "gpio6"), 3931 }; 3932 3933 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3934 .pin_banks = rk3066a_pin_banks, 3935 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3936 .label = "RK3066a-GPIO", 3937 .type = RK2928, 3938 .grf_mux_offset = 0xa8, 3939 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3940 }; 3941 3942 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3943 PIN_BANK(0, 32, "gpio0"), 3944 PIN_BANK(1, 32, "gpio1"), 3945 PIN_BANK(2, 32, "gpio2"), 3946 PIN_BANK(3, 32, "gpio3"), 3947 }; 3948 3949 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3950 .pin_banks = rk3066b_pin_banks, 3951 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3952 .label = "RK3066b-GPIO", 3953 .type = RK3066B, 3954 .grf_mux_offset = 0x60, 3955 }; 3956 3957 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3958 PIN_BANK(0, 32, "gpio0"), 3959 PIN_BANK(1, 32, "gpio1"), 3960 PIN_BANK(2, 32, "gpio2"), 3961 PIN_BANK(3, 32, "gpio3"), 3962 }; 3963 3964 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3965 .pin_banks = rk3128_pin_banks, 3966 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3967 .label = "RK3128-GPIO", 3968 .type = RK3128, 3969 .grf_mux_offset = 0xa8, 3970 .iomux_recalced = rk3128_mux_recalced_data, 3971 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3972 .iomux_routes = rk3128_mux_route_data, 3973 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3974 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3975 }; 3976 3977 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3978 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3979 PIN_BANK(1, 32, "gpio1"), 3980 PIN_BANK(2, 32, "gpio2"), 3981 PIN_BANK(3, 32, "gpio3"), 3982 }; 3983 3984 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3985 .pin_banks = rk3188_pin_banks, 3986 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3987 .label = "RK3188-GPIO", 3988 .type = RK3188, 3989 .grf_mux_offset = 0x60, 3990 .iomux_routes = rk3188_mux_route_data, 3991 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 3992 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3993 }; 3994 3995 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3996 PIN_BANK(0, 32, "gpio0"), 3997 PIN_BANK(1, 32, "gpio1"), 3998 PIN_BANK(2, 32, "gpio2"), 3999 PIN_BANK(3, 32, "gpio3"), 4000 }; 4001 4002 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 4003 .pin_banks = rk3228_pin_banks, 4004 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 4005 .label = "RK3228-GPIO", 4006 .type = RK3288, 4007 .grf_mux_offset = 0x0, 4008 .iomux_routes = rk3228_mux_route_data, 4009 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 4010 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 4011 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 4012 }; 4013 4014 static struct rockchip_pin_bank rk3288_pin_banks[] = { 4015 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 4016 IOMUX_SOURCE_PMU, 4017 IOMUX_SOURCE_PMU, 4018 IOMUX_UNROUTED 4019 ), 4020 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 4021 IOMUX_UNROUTED, 4022 IOMUX_UNROUTED, 4023 0 4024 ), 4025 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 4026 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 4027 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 4028 IOMUX_WIDTH_4BIT, 4029 0, 4030 0 4031 ), 4032 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 4033 0, 4034 0, 4035 IOMUX_UNROUTED 4036 ), 4037 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 4038 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 4039 0, 4040 IOMUX_WIDTH_4BIT, 4041 IOMUX_UNROUTED 4042 ), 4043 PIN_BANK(8, 16, "gpio8"), 4044 }; 4045 4046 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 4047 .pin_banks = rk3288_pin_banks, 4048 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 4049 .label = "RK3288-GPIO", 4050 .type = RK3288, 4051 .grf_mux_offset = 0x0, 4052 .pmu_mux_offset = 0x84, 4053 .iomux_routes = rk3288_mux_route_data, 4054 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 4055 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 4056 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 4057 }; 4058 4059 static struct rockchip_pin_bank rk3308_pin_banks[] = { 4060 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 4061 IOMUX_WIDTH_2BIT, 4062 IOMUX_WIDTH_2BIT, 4063 IOMUX_WIDTH_2BIT), 4064 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 4065 IOMUX_WIDTH_2BIT, 4066 IOMUX_WIDTH_2BIT, 4067 IOMUX_WIDTH_2BIT), 4068 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 4069 IOMUX_WIDTH_2BIT, 4070 IOMUX_WIDTH_2BIT, 4071 IOMUX_WIDTH_2BIT), 4072 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 4073 IOMUX_WIDTH_2BIT, 4074 IOMUX_WIDTH_2BIT, 4075 IOMUX_WIDTH_2BIT), 4076 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 4077 IOMUX_WIDTH_2BIT, 4078 IOMUX_WIDTH_2BIT, 4079 IOMUX_WIDTH_2BIT), 4080 }; 4081 4082 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 4083 .pin_banks = rk3308_pin_banks, 4084 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 4085 .label = "RK3308-GPIO", 4086 .type = RK3308, 4087 .grf_mux_offset = 0x0, 4088 .iomux_recalced = rk3308_mux_recalced_data, 4089 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 4090 .iomux_routes = rk3308_mux_route_data, 4091 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 4092 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 4093 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 4094 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 4095 }; 4096 4097 static struct rockchip_pin_bank rk3328_pin_banks[] = { 4098 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 4099 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 4100 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 4101 IOMUX_WIDTH_3BIT, 4102 IOMUX_WIDTH_3BIT, 4103 0), 4104 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 4105 IOMUX_WIDTH_3BIT, 4106 IOMUX_WIDTH_3BIT, 4107 0, 4108 0), 4109 }; 4110 4111 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 4112 .pin_banks = rk3328_pin_banks, 4113 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 4114 .label = "RK3328-GPIO", 4115 .type = RK3288, 4116 .grf_mux_offset = 0x0, 4117 .iomux_recalced = rk3328_mux_recalced_data, 4118 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 4119 .iomux_routes = rk3328_mux_route_data, 4120 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 4121 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 4122 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 4123 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 4124 }; 4125 4126 static struct rockchip_pin_bank rk3368_pin_banks[] = { 4127 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 4128 IOMUX_SOURCE_PMU, 4129 IOMUX_SOURCE_PMU, 4130 IOMUX_SOURCE_PMU 4131 ), 4132 PIN_BANK(1, 32, "gpio1"), 4133 PIN_BANK(2, 32, "gpio2"), 4134 PIN_BANK(3, 32, "gpio3"), 4135 }; 4136 4137 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 4138 .pin_banks = rk3368_pin_banks, 4139 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 4140 .label = "RK3368-GPIO", 4141 .type = RK3368, 4142 .grf_mux_offset = 0x0, 4143 .pmu_mux_offset = 0x0, 4144 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 4145 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 4146 }; 4147 4148 static struct rockchip_pin_bank rk3399_pin_banks[] = { 4149 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 4150 IOMUX_SOURCE_PMU, 4151 IOMUX_SOURCE_PMU, 4152 IOMUX_SOURCE_PMU, 4153 IOMUX_SOURCE_PMU, 4154 DRV_TYPE_IO_1V8_ONLY, 4155 DRV_TYPE_IO_1V8_ONLY, 4156 DRV_TYPE_IO_DEFAULT, 4157 DRV_TYPE_IO_DEFAULT, 4158 0x80, 4159 0x88, 4160 -1, 4161 -1, 4162 PULL_TYPE_IO_1V8_ONLY, 4163 PULL_TYPE_IO_1V8_ONLY, 4164 PULL_TYPE_IO_DEFAULT, 4165 PULL_TYPE_IO_DEFAULT 4166 ), 4167 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 4168 IOMUX_SOURCE_PMU, 4169 IOMUX_SOURCE_PMU, 4170 IOMUX_SOURCE_PMU, 4171 DRV_TYPE_IO_1V8_OR_3V0, 4172 DRV_TYPE_IO_1V8_OR_3V0, 4173 DRV_TYPE_IO_1V8_OR_3V0, 4174 DRV_TYPE_IO_1V8_OR_3V0, 4175 0xa0, 4176 0xa8, 4177 0xb0, 4178 0xb8 4179 ), 4180 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 4181 DRV_TYPE_IO_1V8_OR_3V0, 4182 DRV_TYPE_IO_1V8_ONLY, 4183 DRV_TYPE_IO_1V8_ONLY, 4184 PULL_TYPE_IO_DEFAULT, 4185 PULL_TYPE_IO_DEFAULT, 4186 PULL_TYPE_IO_1V8_ONLY, 4187 PULL_TYPE_IO_1V8_ONLY 4188 ), 4189 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 4190 DRV_TYPE_IO_3V3_ONLY, 4191 DRV_TYPE_IO_3V3_ONLY, 4192 DRV_TYPE_IO_1V8_OR_3V0 4193 ), 4194 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 4195 DRV_TYPE_IO_1V8_3V0_AUTO, 4196 DRV_TYPE_IO_1V8_OR_3V0, 4197 DRV_TYPE_IO_1V8_OR_3V0 4198 ), 4199 }; 4200 4201 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 4202 .pin_banks = rk3399_pin_banks, 4203 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 4204 .label = "RK3399-GPIO", 4205 .type = RK3399, 4206 .grf_mux_offset = 0xe000, 4207 .pmu_mux_offset = 0x0, 4208 .grf_drv_offset = 0xe100, 4209 .pmu_drv_offset = 0x80, 4210 .iomux_routes = rk3399_mux_route_data, 4211 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 4212 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 4213 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 4214 }; 4215 4216 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 4217 { .compatible = "rockchip,px30-pinctrl", 4218 .data = &px30_pin_ctrl }, 4219 { .compatible = "rockchip,rv1108-pinctrl", 4220 .data = &rv1108_pin_ctrl }, 4221 { .compatible = "rockchip,rk2928-pinctrl", 4222 .data = &rk2928_pin_ctrl }, 4223 { .compatible = "rockchip,rk3036-pinctrl", 4224 .data = &rk3036_pin_ctrl }, 4225 { .compatible = "rockchip,rk3066a-pinctrl", 4226 .data = &rk3066a_pin_ctrl }, 4227 { .compatible = "rockchip,rk3066b-pinctrl", 4228 .data = &rk3066b_pin_ctrl }, 4229 { .compatible = "rockchip,rk3128-pinctrl", 4230 .data = (void *)&rk3128_pin_ctrl }, 4231 { .compatible = "rockchip,rk3188-pinctrl", 4232 .data = &rk3188_pin_ctrl }, 4233 { .compatible = "rockchip,rk3228-pinctrl", 4234 .data = &rk3228_pin_ctrl }, 4235 { .compatible = "rockchip,rk3288-pinctrl", 4236 .data = &rk3288_pin_ctrl }, 4237 { .compatible = "rockchip,rk3308-pinctrl", 4238 .data = &rk3308_pin_ctrl }, 4239 { .compatible = "rockchip,rk3328-pinctrl", 4240 .data = &rk3328_pin_ctrl }, 4241 { .compatible = "rockchip,rk3368-pinctrl", 4242 .data = &rk3368_pin_ctrl }, 4243 { .compatible = "rockchip,rk3399-pinctrl", 4244 .data = &rk3399_pin_ctrl }, 4245 {}, 4246 }; 4247 4248 static struct platform_driver rockchip_pinctrl_driver = { 4249 .probe = rockchip_pinctrl_probe, 4250 .driver = { 4251 .name = "rockchip-pinctrl", 4252 .pm = &rockchip_pinctrl_dev_pm_ops, 4253 .of_match_table = rockchip_pinctrl_dt_match, 4254 }, 4255 }; 4256 4257 static int __init rockchip_pinctrl_drv_register(void) 4258 { 4259 return platform_driver_register(&rockchip_pinctrl_driver); 4260 } 4261 postcore_initcall(rockchip_pinctrl_drv_register); 4262 4263 static void __exit rockchip_pinctrl_drv_unregister(void) 4264 { 4265 platform_driver_unregister(&rockchip_pinctrl_driver); 4266 } 4267 module_exit(rockchip_pinctrl_drv_unregister); 4268 4269 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver"); 4270 MODULE_LICENSE("GPL"); 4271 MODULE_ALIAS("platform:pinctrl-rockchip"); 4272 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 4273