pinctrl-rockchip.c (bfc7a42a0e74f0b589a017679620d2a3edda9198) pinctrl-rockchip.c (751a99aba47e9bd30b4fd5bf36f4e0143d3e81bb)
1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.

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32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
39#include <linux/clk.h>
1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.

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32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
39#include <linux/clk.h>
40#include <linux/regmap.h>
40#include <dt-bindings/pinctrl/rockchip.h>
41
42#include "core.h"
43#include "pinconf.h"
44
45/* GPIO control registers */
46#define GPIO_SWPORT_DR 0x00
47#define GPIO_SWPORT_DDR 0x04

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81 * @drvdata: common pinctrl basedata
82 * @domain: irqdomain of the gpio bank
83 * @gpio_chip: gpiolib chip
84 * @grange: gpio range
85 * @slock: spinlock for the gpio bank
86 */
87struct rockchip_pin_bank {
88 void __iomem *reg_base;
41#include <dt-bindings/pinctrl/rockchip.h>
42
43#include "core.h"
44#include "pinconf.h"
45
46/* GPIO control registers */
47#define GPIO_SWPORT_DR 0x00
48#define GPIO_SWPORT_DDR 0x04

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82 * @drvdata: common pinctrl basedata
83 * @domain: irqdomain of the gpio bank
84 * @gpio_chip: gpiolib chip
85 * @grange: gpio range
86 * @slock: spinlock for the gpio bank
87 */
88struct rockchip_pin_bank {
89 void __iomem *reg_base;
89 void __iomem *reg_pull;
90 struct regmap *regmap_pull;
90 struct clk *clk;
91 int irq;
92 u32 pin_base;
93 u8 nr_pins;
94 char *name;
95 u8 bank_num;
96 enum rockchip_pin_bank_type bank_type;
97 bool valid;

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115 */
116struct rockchip_pin_ctrl {
117 struct rockchip_pin_bank *pin_banks;
118 u32 nr_banks;
119 u32 nr_pins;
120 char *label;
121 enum rockchip_pinctrl_type type;
122 int mux_offset;
91 struct clk *clk;
92 int irq;
93 u32 pin_base;
94 u8 nr_pins;
95 char *name;
96 u8 bank_num;
97 enum rockchip_pin_bank_type bank_type;
98 bool valid;

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116 */
117struct rockchip_pin_ctrl {
118 struct rockchip_pin_bank *pin_banks;
119 u32 nr_banks;
120 u32 nr_pins;
121 char *label;
122 enum rockchip_pinctrl_type type;
123 int mux_offset;
123 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
124 void __iomem **reg, u8 *bit);
124 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
125 int pin_num, struct regmap **regmap,
126 int *reg, u8 *bit);
125};
126
127struct rockchip_pin_config {
128 unsigned int func;
129 unsigned long *configs;
130 unsigned int nconfigs;
131};
132

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154 */
155struct rockchip_pmx_func {
156 const char *name;
157 const char **groups;
158 u8 ngroups;
159};
160
161struct rockchip_pinctrl {
127};
128
129struct rockchip_pin_config {
130 unsigned int func;
131 unsigned long *configs;
132 unsigned int nconfigs;
133};
134

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156 */
157struct rockchip_pmx_func {
158 const char *name;
159 const char **groups;
160 u8 ngroups;
161};
162
163struct rockchip_pinctrl {
162 void __iomem *reg_base;
164 struct regmap *regmap_base;
163 int reg_size;
165 int reg_size;
164 void __iomem *reg_pull;
166 struct regmap *regmap_pull;
165 struct device *dev;
166 struct rockchip_pin_ctrl *ctrl;
167 struct pinctrl_desc pctl;
168 struct pinctrl_dev *pctl_dev;
169 struct rockchip_pin_group *groups;
170 unsigned int ngroups;
171 struct rockchip_pmx_func *functions;
172 unsigned int nfunctions;
173};
174
167 struct device *dev;
168 struct rockchip_pin_ctrl *ctrl;
169 struct pinctrl_desc pctl;
170 struct pinctrl_dev *pctl_dev;
171 struct rockchip_pin_group *groups;
172 unsigned int ngroups;
173 struct rockchip_pmx_func *functions;
174 unsigned int nfunctions;
175};
176
177static struct regmap_config rockchip_regmap_config = {
178 .reg_bits = 32,
179 .val_bits = 32,
180 .reg_stride = 4,
181};
182
175static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
176{
177 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
178}
179
180static const inline struct rockchip_pin_group *pinctrl_name_to_group(
181 const struct rockchip_pinctrl *info,
182 const char *name)

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328
329/*
330 * Hardware access
331 */
332
333static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
334{
335 struct rockchip_pinctrl *info = bank->drvdata;
183static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
184{
185 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
186}
187
188static const inline struct rockchip_pin_group *pinctrl_name_to_group(
189 const struct rockchip_pinctrl *info,
190 const char *name)

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336
337/*
338 * Hardware access
339 */
340
341static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
342{
343 struct rockchip_pinctrl *info = bank->drvdata;
336 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
344 unsigned int val;
345 int reg, ret;
337 u8 bit;
338
339 if (bank->bank_type == RK3188_BANK0 && pin < 16)
340 return RK_FUNC_GPIO;
341
342 /* get basic quadrupel of mux registers and the correct reg inside */
346 u8 bit;
347
348 if (bank->bank_type == RK3188_BANK0 && pin < 16)
349 return RK_FUNC_GPIO;
350
351 /* get basic quadrupel of mux registers and the correct reg inside */
352 reg = info->ctrl->mux_offset;
343 reg += bank->bank_num * 0x10;
344 reg += (pin / 8) * 4;
345 bit = (pin % 8) * 2;
346
353 reg += bank->bank_num * 0x10;
354 reg += (pin / 8) * 4;
355 bit = (pin % 8) * 2;
356
347 return ((readl(reg) >> bit) & 3);
357 ret = regmap_read(info->regmap_base, reg, &val);
358 if (ret)
359 return ret;
360
361 return ((val >> bit) & 3);
348}
349
350/*
351 * Set a new mux function for a pin.
352 *
353 * The register is divided into the upper and lower 16 bit. When changing
354 * a value, the previous register value is not read and changed. Instead
355 * it seems the changed bits are marked in the upper 16 bit, while the
356 * changed value gets set in the same offset in the lower 16 bit.
357 * All pin settings seem to be 2 bit wide in both the upper and lower
358 * parts.
359 * @bank: pin bank to change
360 * @pin: pin to change
361 * @mux: new mux function to set
362 */
363static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
364{
365 struct rockchip_pinctrl *info = bank->drvdata;
362}
363
364/*
365 * Set a new mux function for a pin.
366 *
367 * The register is divided into the upper and lower 16 bit. When changing
368 * a value, the previous register value is not read and changed. Instead
369 * it seems the changed bits are marked in the upper 16 bit, while the
370 * changed value gets set in the same offset in the lower 16 bit.
371 * All pin settings seem to be 2 bit wide in both the upper and lower
372 * parts.
373 * @bank: pin bank to change
374 * @pin: pin to change
375 * @mux: new mux function to set
376 */
377static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
378{
379 struct rockchip_pinctrl *info = bank->drvdata;
366 void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
380 int reg, ret;
367 unsigned long flags;
368 u8 bit;
369 u32 data;
370
371 /*
372 * The first 16 pins of rk3188_bank0 are always gpios and do not have
373 * a mux register at all.
374 */

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381 return 0;
382 }
383 }
384
385 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
386 bank->bank_num, pin, mux);
387
388 /* get basic quadrupel of mux registers and the correct reg inside */
381 unsigned long flags;
382 u8 bit;
383 u32 data;
384
385 /*
386 * The first 16 pins of rk3188_bank0 are always gpios and do not have
387 * a mux register at all.
388 */

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395 return 0;
396 }
397 }
398
399 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
400 bank->bank_num, pin, mux);
401
402 /* get basic quadrupel of mux registers and the correct reg inside */
403 reg = info->ctrl->mux_offset;
389 reg += bank->bank_num * 0x10;
390 reg += (pin / 8) * 4;
391 bit = (pin % 8) * 2;
392
393 spin_lock_irqsave(&bank->slock, flags);
394
395 data = (3 << (bit + 16));
396 data |= (mux & 3) << bit;
404 reg += bank->bank_num * 0x10;
405 reg += (pin / 8) * 4;
406 bit = (pin % 8) * 2;
407
408 spin_lock_irqsave(&bank->slock, flags);
409
410 data = (3 << (bit + 16));
411 data |= (mux & 3) << bit;
397 writel(data, reg);
412 ret = regmap_write(info->regmap_base, reg, data);
398
399 spin_unlock_irqrestore(&bank->slock, flags);
400
413
414 spin_unlock_irqrestore(&bank->slock, flags);
415
401 return 0;
416 return ret;
402}
403
404#define RK2928_PULL_OFFSET 0x118
405#define RK2928_PULL_PINS_PER_REG 16
406#define RK2928_PULL_BANK_STRIDE 8
407
408static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
417}
418
419#define RK2928_PULL_OFFSET 0x118
420#define RK2928_PULL_PINS_PER_REG 16
421#define RK2928_PULL_BANK_STRIDE 8
422
423static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
409 int pin_num, void __iomem **reg, u8 *bit)
424 int pin_num, struct regmap **regmap,
425 int *reg, u8 *bit)
410{
411 struct rockchip_pinctrl *info = bank->drvdata;
412
426{
427 struct rockchip_pinctrl *info = bank->drvdata;
428
413 *reg = info->reg_base + RK2928_PULL_OFFSET;
429 *regmap = info->regmap_base;
430 *reg = RK2928_PULL_OFFSET;
414 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
415 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
416
417 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
418};
419
420#define RK3188_PULL_OFFSET 0x164
421#define RK3188_PULL_BITS_PER_PIN 2
422#define RK3188_PULL_PINS_PER_REG 8
423#define RK3188_PULL_BANK_STRIDE 16
424
425static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
431 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
432 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
433
434 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
435};
436
437#define RK3188_PULL_OFFSET 0x164
438#define RK3188_PULL_BITS_PER_PIN 2
439#define RK3188_PULL_PINS_PER_REG 8
440#define RK3188_PULL_BANK_STRIDE 16
441
442static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
426 int pin_num, void __iomem **reg, u8 *bit)
443 int pin_num, struct regmap **regmap,
444 int *reg, u8 *bit)
427{
428 struct rockchip_pinctrl *info = bank->drvdata;
429
430 /* The first 12 pins of the first bank are located elsewhere */
431 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
445{
446 struct rockchip_pinctrl *info = bank->drvdata;
447
448 /* The first 12 pins of the first bank are located elsewhere */
449 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
432 *reg = bank->reg_pull +
433 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
450 *regmap = bank->regmap_pull;
451 *reg = 0;
452 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
434 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
435 *bit *= RK3188_PULL_BITS_PER_PIN;
436 } else {
453 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
454 *bit *= RK3188_PULL_BITS_PER_PIN;
455 } else {
437 *reg = info->reg_pull ? info->reg_pull
438 : info->reg_base + RK3188_PULL_OFFSET;
456 *regmap = info->regmap_pull ? info->regmap_pull
457 : info->regmap_base;
458 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
459
439 /* correct the offset, as it is the 2nd pull register */
440 *reg -= 4;
441 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
442 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
443
444 /*
445 * The bits in these registers have an inverse ordering
446 * with the lowest pin being in bits 15:14 and the highest
447 * pin in bits 1:0
448 */
449 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
450 *bit *= RK3188_PULL_BITS_PER_PIN;
451 }
452}
453
454static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
455{
456 struct rockchip_pinctrl *info = bank->drvdata;
457 struct rockchip_pin_ctrl *ctrl = info->ctrl;
460 /* correct the offset, as it is the 2nd pull register */
461 *reg -= 4;
462 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
463 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
464
465 /*
466 * The bits in these registers have an inverse ordering
467 * with the lowest pin being in bits 15:14 and the highest
468 * pin in bits 1:0
469 */
470 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
471 *bit *= RK3188_PULL_BITS_PER_PIN;
472 }
473}
474
475static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
476{
477 struct rockchip_pinctrl *info = bank->drvdata;
478 struct rockchip_pin_ctrl *ctrl = info->ctrl;
458 void __iomem *reg;
479 struct regmap *regmap;
480 int reg, ret;
459 u8 bit;
460 u32 data;
461
462 /* rk3066b does support any pulls */
463 if (ctrl->type == RK3066B)
464 return PIN_CONFIG_BIAS_DISABLE;
465
481 u8 bit;
482 u32 data;
483
484 /* rk3066b does support any pulls */
485 if (ctrl->type == RK3066B)
486 return PIN_CONFIG_BIAS_DISABLE;
487
466 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
488 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
467
489
490 ret = regmap_read(regmap, reg, &data);
491 if (ret)
492 return ret;
493
468 switch (ctrl->type) {
469 case RK2928:
494 switch (ctrl->type) {
495 case RK2928:
470 return !(readl_relaxed(reg) & BIT(bit))
496 return !(data & BIT(bit))
471 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
472 : PIN_CONFIG_BIAS_DISABLE;
473 case RK3188:
497 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
498 : PIN_CONFIG_BIAS_DISABLE;
499 case RK3188:
474 data = readl_relaxed(reg) >> bit;
500 data >>= bit;
475 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
476
477 switch (data) {
478 case 0:
479 return PIN_CONFIG_BIAS_DISABLE;
480 case 1:
481 return PIN_CONFIG_BIAS_PULL_UP;
482 case 2:

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493 };
494}
495
496static int rockchip_set_pull(struct rockchip_pin_bank *bank,
497 int pin_num, int pull)
498{
499 struct rockchip_pinctrl *info = bank->drvdata;
500 struct rockchip_pin_ctrl *ctrl = info->ctrl;
501 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
502
503 switch (data) {
504 case 0:
505 return PIN_CONFIG_BIAS_DISABLE;
506 case 1:
507 return PIN_CONFIG_BIAS_PULL_UP;
508 case 2:

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519 };
520}
521
522static int rockchip_set_pull(struct rockchip_pin_bank *bank,
523 int pin_num, int pull)
524{
525 struct rockchip_pinctrl *info = bank->drvdata;
526 struct rockchip_pin_ctrl *ctrl = info->ctrl;
501 void __iomem *reg;
527 struct regmap *regmap;
528 int reg, ret;
502 unsigned long flags;
503 u8 bit;
504 u32 data;
505
506 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
507 bank->bank_num, pin_num, pull);
508
509 /* rk3066b does support any pulls */
510 if (ctrl->type == RK3066B)
511 return pull ? -EINVAL : 0;
512
529 unsigned long flags;
530 u8 bit;
531 u32 data;
532
533 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
534 bank->bank_num, pin_num, pull);
535
536 /* rk3066b does support any pulls */
537 if (ctrl->type == RK3066B)
538 return pull ? -EINVAL : 0;
539
513 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
540 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
514
515 switch (ctrl->type) {
516 case RK2928:
517 spin_lock_irqsave(&bank->slock, flags);
518
519 data = BIT(bit + 16);
520 if (pull == PIN_CONFIG_BIAS_DISABLE)
521 data |= BIT(bit);
541
542 switch (ctrl->type) {
543 case RK2928:
544 spin_lock_irqsave(&bank->slock, flags);
545
546 data = BIT(bit + 16);
547 if (pull == PIN_CONFIG_BIAS_DISABLE)
548 data |= BIT(bit);
522 writel(data, reg);
549 ret = regmap_write(regmap, reg, data);
523
524 spin_unlock_irqrestore(&bank->slock, flags);
525 break;
526 case RK3188:
527 spin_lock_irqsave(&bank->slock, flags);
528
529 /* enable the write to the equivalent lower bits */
530 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);

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543 break;
544 default:
545 spin_unlock_irqrestore(&bank->slock, flags);
546 dev_err(info->dev, "unsupported pull setting %d\n",
547 pull);
548 return -EINVAL;
549 }
550
550
551 spin_unlock_irqrestore(&bank->slock, flags);
552 break;
553 case RK3188:
554 spin_lock_irqsave(&bank->slock, flags);
555
556 /* enable the write to the equivalent lower bits */
557 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);

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570 break;
571 default:
572 spin_unlock_irqrestore(&bank->slock, flags);
573 dev_err(info->dev, "unsupported pull setting %d\n",
574 pull);
575 return -EINVAL;
576 }
577
551 writel(data, reg);
578 ret = regmap_write(regmap, reg, data);
552
553 spin_unlock_irqrestore(&bank->slock, flags);
554 break;
555 default:
556 dev_err(info->dev, "unsupported pinctrl type\n");
557 return -EINVAL;
558 }
559
579
580 spin_unlock_irqrestore(&bank->slock, flags);
581 break;
582 default:
583 dev_err(info->dev, "unsupported pinctrl type\n");
584 return -EINVAL;
585 }
586
560 return 0;
587 return ret;
561}
562
563/*
564 * Pinmux_ops handling
565 */
566
567static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
568{

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1411
1412 return ret;
1413}
1414
1415static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1416 struct device *dev)
1417{
1418 struct resource res;
588}
589
590/*
591 * Pinmux_ops handling
592 */
593
594static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
595{

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1438
1439 return ret;
1440}
1441
1442static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1443 struct device *dev)
1444{
1445 struct resource res;
1446 void __iomem *base;
1419
1420 if (of_address_to_resource(bank->of_node, 0, &res)) {
1421 dev_err(dev, "cannot find IO resource for bank\n");
1422 return -ENOENT;
1423 }
1424
1425 bank->reg_base = devm_ioremap_resource(dev, &res);
1426 if (IS_ERR(bank->reg_base))

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1435
1436 bank->bank_type = RK3188_BANK0;
1437
1438 if (of_address_to_resource(bank->of_node, 1, &res)) {
1439 dev_err(dev, "cannot find IO resource for bank\n");
1440 return -ENOENT;
1441 }
1442
1447
1448 if (of_address_to_resource(bank->of_node, 0, &res)) {
1449 dev_err(dev, "cannot find IO resource for bank\n");
1450 return -ENOENT;
1451 }
1452
1453 bank->reg_base = devm_ioremap_resource(dev, &res);
1454 if (IS_ERR(bank->reg_base))

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1463
1464 bank->bank_type = RK3188_BANK0;
1465
1466 if (of_address_to_resource(bank->of_node, 1, &res)) {
1467 dev_err(dev, "cannot find IO resource for bank\n");
1468 return -ENOENT;
1469 }
1470
1443 bank->reg_pull = devm_ioremap_resource(dev, &res);
1444 if (IS_ERR(bank->reg_pull))
1445 return PTR_ERR(bank->reg_pull);
1471 base = devm_ioremap_resource(dev, &res);
1472 if (IS_ERR(base))
1473 return PTR_ERR(base);
1474 rockchip_regmap_config.max_register = resource_size(&res) - 4;
1475 rockchip_regmap_config.name = "rockchip,rk3188-gpio-bank0-pull";
1476 bank->regmap_pull = devm_regmap_init_mmio(dev, base,
1477 &rockchip_regmap_config);
1478
1446 } else {
1447 bank->bank_type = COMMON_BANK;
1448 }
1449
1450 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1451
1452 bank->clk = of_clk_get(bank->of_node, 0);
1453 if (IS_ERR(bank->clk))

--- 48 unchanged lines hidden (view full) ---

1502}
1503
1504static int rockchip_pinctrl_probe(struct platform_device *pdev)
1505{
1506 struct rockchip_pinctrl *info;
1507 struct device *dev = &pdev->dev;
1508 struct rockchip_pin_ctrl *ctrl;
1509 struct resource *res;
1479 } else {
1480 bank->bank_type = COMMON_BANK;
1481 }
1482
1483 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1484
1485 bank->clk = of_clk_get(bank->of_node, 0);
1486 if (IS_ERR(bank->clk))

--- 48 unchanged lines hidden (view full) ---

1535}
1536
1537static int rockchip_pinctrl_probe(struct platform_device *pdev)
1538{
1539 struct rockchip_pinctrl *info;
1540 struct device *dev = &pdev->dev;
1541 struct rockchip_pin_ctrl *ctrl;
1542 struct resource *res;
1543 void __iomem *base;
1510 int ret;
1511
1512 if (!dev->of_node) {
1513 dev_err(dev, "device tree node not found\n");
1514 return -ENODEV;
1515 }
1516
1517 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);

--- 4 unchanged lines hidden (view full) ---

1522 if (!ctrl) {
1523 dev_err(dev, "driver data not available\n");
1524 return -EINVAL;
1525 }
1526 info->ctrl = ctrl;
1527 info->dev = dev;
1528
1529 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1544 int ret;
1545
1546 if (!dev->of_node) {
1547 dev_err(dev, "device tree node not found\n");
1548 return -ENODEV;
1549 }
1550
1551 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);

--- 4 unchanged lines hidden (view full) ---

1556 if (!ctrl) {
1557 dev_err(dev, "driver data not available\n");
1558 return -EINVAL;
1559 }
1560 info->ctrl = ctrl;
1561 info->dev = dev;
1562
1563 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1530 info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1531 if (IS_ERR(info->reg_base))
1532 return PTR_ERR(info->reg_base);
1564 base = devm_ioremap_resource(&pdev->dev, res);
1565 if (IS_ERR(base))
1566 return PTR_ERR(base);
1533
1567
1568 rockchip_regmap_config.max_register = resource_size(res) - 4;
1569 rockchip_regmap_config.name = "rockchip,pinctrl";
1570 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1571 &rockchip_regmap_config);
1572
1534 /* to check for the old dt-bindings */
1535 info->reg_size = resource_size(res);
1536
1537 /* Honor the old binding, with pull registers as 2nd resource */
1573 /* to check for the old dt-bindings */
1574 info->reg_size = resource_size(res);
1575
1576 /* Honor the old binding, with pull registers as 2nd resource */
1538 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1577 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1539 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1578 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1540 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
1541 if (IS_ERR(info->reg_pull))
1542 return PTR_ERR(info->reg_pull);
1579 base = devm_ioremap_resource(&pdev->dev, res);
1580 if (IS_ERR(base))
1581 return PTR_ERR(base);
1582
1583 rockchip_regmap_config.max_register = resource_size(res) - 4;
1584 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1585 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, base,
1586 &rockchip_regmap_config);
1543 }
1544
1545 ret = rockchip_gpiolib_register(pdev, info);
1546 if (ret)
1547 return ret;
1548
1549 ret = rockchip_pinctrl_register(pdev, info);
1550 if (ret) {

--- 105 unchanged lines hidden --- 		1587 }
1588
1589 ret = rockchip_gpiolib_register(pdev, info);
1590 if (ret)
1591 return ret;
1592
1593 ret = rockchip_pinctrl_register(pdev, info);
1594 if (ret) {

--- 105 unchanged lines hidden ---