1 /* 2 * Pinctrl driver for Rockchip SoCs 3 * 4 * Copyright (c) 2013 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * With some ideas taken from pinctrl-samsung: 8 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 9 * http://www.samsung.com 10 * Copyright (c) 2012 Linaro Ltd 11 * http://www.linaro.org 12 * 13 * and pinctrl-at91: 14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as published 18 * by the Free Software Foundation. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/platform_device.h> 28 #include <linux/io.h> 29 #include <linux/bitops.h> 30 #include <linux/gpio.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/pinctrl/machine.h> 34 #include <linux/pinctrl/pinconf.h> 35 #include <linux/pinctrl/pinctrl.h> 36 #include <linux/pinctrl/pinmux.h> 37 #include <linux/pinctrl/pinconf-generic.h> 38 #include <linux/irqchip/chained_irq.h> 39 #include <linux/clk.h> 40 #include <dt-bindings/pinctrl/rockchip.h> 41 42 #include "core.h" 43 #include "pinconf.h" 44 45 /* GPIO control registers */ 46 #define GPIO_SWPORT_DR 0x00 47 #define GPIO_SWPORT_DDR 0x04 48 #define GPIO_INTEN 0x30 49 #define GPIO_INTMASK 0x34 50 #define GPIO_INTTYPE_LEVEL 0x38 51 #define GPIO_INT_POLARITY 0x3c 52 #define GPIO_INT_STATUS 0x40 53 #define GPIO_INT_RAWSTATUS 0x44 54 #define GPIO_DEBOUNCE 0x48 55 #define GPIO_PORTS_EOI 0x4c 56 #define GPIO_EXT_PORT 0x50 57 #define GPIO_LS_SYNC 0x60 58 59 enum rockchip_pinctrl_type { 60 RK2928, 61 RK3066B, 62 RK3188, 63 }; 64 65 enum rockchip_pin_bank_type { 66 COMMON_BANK, 67 RK3188_BANK0, 68 }; 69 70 /** 71 * @reg_base: register base of the gpio bank 72 * @reg_pull: optional separate register for additional pull settings 73 * @clk: clock of the gpio bank 74 * @irq: interrupt of the gpio bank 75 * @pin_base: first pin number 76 * @nr_pins: number of pins in this bank 77 * @name: name of the bank 78 * @bank_num: number of the bank, to account for holes 79 * @valid: are all necessary informations present 80 * @of_node: dt node of this bank 81 * @drvdata: common pinctrl basedata 82 * @domain: irqdomain of the gpio bank 83 * @gpio_chip: gpiolib chip 84 * @grange: gpio range 85 * @slock: spinlock for the gpio bank 86 */ 87 struct rockchip_pin_bank { 88 void __iomem *reg_base; 89 void __iomem *reg_pull; 90 struct clk *clk; 91 int irq; 92 u32 pin_base; 93 u8 nr_pins; 94 char *name; 95 u8 bank_num; 96 enum rockchip_pin_bank_type bank_type; 97 bool valid; 98 struct device_node *of_node; 99 struct rockchip_pinctrl *drvdata; 100 struct irq_domain *domain; 101 struct gpio_chip gpio_chip; 102 struct pinctrl_gpio_range grange; 103 spinlock_t slock; 104 u32 toggle_edge_mode; 105 }; 106 107 #define PIN_BANK(id, pins, label) \ 108 { \ 109 .bank_num = id, \ 110 .nr_pins = pins, \ 111 .name = label, \ 112 } 113 114 /** 115 */ 116 struct rockchip_pin_ctrl { 117 struct rockchip_pin_bank *pin_banks; 118 u32 nr_banks; 119 u32 nr_pins; 120 char *label; 121 enum rockchip_pinctrl_type type; 122 int mux_offset; 123 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, 124 void __iomem **reg, u8 *bit); 125 }; 126 127 struct rockchip_pin_config { 128 unsigned int func; 129 unsigned long *configs; 130 unsigned int nconfigs; 131 }; 132 133 /** 134 * struct rockchip_pin_group: represent group of pins of a pinmux function. 135 * @name: name of the pin group, used to lookup the group. 136 * @pins: the pins included in this group. 137 * @npins: number of pins included in this group. 138 * @func: the mux function number to be programmed when selected. 139 * @configs: the config values to be set for each pin 140 * @nconfigs: number of configs for each pin 141 */ 142 struct rockchip_pin_group { 143 const char *name; 144 unsigned int npins; 145 unsigned int *pins; 146 struct rockchip_pin_config *data; 147 }; 148 149 /** 150 * struct rockchip_pmx_func: represent a pin function. 151 * @name: name of the pin function, used to lookup the function. 152 * @groups: one or more names of pin groups that provide this function. 153 * @num_groups: number of groups included in @groups. 154 */ 155 struct rockchip_pmx_func { 156 const char *name; 157 const char **groups; 158 u8 ngroups; 159 }; 160 161 struct rockchip_pinctrl { 162 void __iomem *reg_base; 163 int reg_size; 164 void __iomem *reg_pull; 165 struct device *dev; 166 struct rockchip_pin_ctrl *ctrl; 167 struct pinctrl_desc pctl; 168 struct pinctrl_dev *pctl_dev; 169 struct rockchip_pin_group *groups; 170 unsigned int ngroups; 171 struct rockchip_pmx_func *functions; 172 unsigned int nfunctions; 173 }; 174 175 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) 176 { 177 return container_of(gc, struct rockchip_pin_bank, gpio_chip); 178 } 179 180 static const inline struct rockchip_pin_group *pinctrl_name_to_group( 181 const struct rockchip_pinctrl *info, 182 const char *name) 183 { 184 int i; 185 186 for (i = 0; i < info->ngroups; i++) { 187 if (!strcmp(info->groups[i].name, name)) 188 return &info->groups[i]; 189 } 190 191 return NULL; 192 } 193 194 /* 195 * given a pin number that is local to a pin controller, find out the pin bank 196 * and the register base of the pin bank. 197 */ 198 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 199 unsigned pin) 200 { 201 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 202 203 while (pin >= (b->pin_base + b->nr_pins)) 204 b++; 205 206 return b; 207 } 208 209 static struct rockchip_pin_bank *bank_num_to_bank( 210 struct rockchip_pinctrl *info, 211 unsigned num) 212 { 213 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 214 int i; 215 216 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 217 if (b->bank_num == num) 218 return b; 219 } 220 221 return ERR_PTR(-EINVAL); 222 } 223 224 /* 225 * Pinctrl_ops handling 226 */ 227 228 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 229 { 230 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 231 232 return info->ngroups; 233 } 234 235 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 236 unsigned selector) 237 { 238 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 239 240 return info->groups[selector].name; 241 } 242 243 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 244 unsigned selector, const unsigned **pins, 245 unsigned *npins) 246 { 247 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 248 249 if (selector >= info->ngroups) 250 return -EINVAL; 251 252 *pins = info->groups[selector].pins; 253 *npins = info->groups[selector].npins; 254 255 return 0; 256 } 257 258 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 259 struct device_node *np, 260 struct pinctrl_map **map, unsigned *num_maps) 261 { 262 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 263 const struct rockchip_pin_group *grp; 264 struct pinctrl_map *new_map; 265 struct device_node *parent; 266 int map_num = 1; 267 int i; 268 269 /* 270 * first find the group of this node and check if we need to create 271 * config maps for pins 272 */ 273 grp = pinctrl_name_to_group(info, np->name); 274 if (!grp) { 275 dev_err(info->dev, "unable to find group for node %s\n", 276 np->name); 277 return -EINVAL; 278 } 279 280 map_num += grp->npins; 281 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, 282 GFP_KERNEL); 283 if (!new_map) 284 return -ENOMEM; 285 286 *map = new_map; 287 *num_maps = map_num; 288 289 /* create mux map */ 290 parent = of_get_parent(np); 291 if (!parent) { 292 devm_kfree(pctldev->dev, new_map); 293 return -EINVAL; 294 } 295 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 296 new_map[0].data.mux.function = parent->name; 297 new_map[0].data.mux.group = np->name; 298 of_node_put(parent); 299 300 /* create config map */ 301 new_map++; 302 for (i = 0; i < grp->npins; i++) { 303 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 304 new_map[i].data.configs.group_or_pin = 305 pin_get_name(pctldev, grp->pins[i]); 306 new_map[i].data.configs.configs = grp->data[i].configs; 307 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 308 } 309 310 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 311 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 312 313 return 0; 314 } 315 316 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 317 struct pinctrl_map *map, unsigned num_maps) 318 { 319 } 320 321 static const struct pinctrl_ops rockchip_pctrl_ops = { 322 .get_groups_count = rockchip_get_groups_count, 323 .get_group_name = rockchip_get_group_name, 324 .get_group_pins = rockchip_get_group_pins, 325 .dt_node_to_map = rockchip_dt_node_to_map, 326 .dt_free_map = rockchip_dt_free_map, 327 }; 328 329 /* 330 * Hardware access 331 */ 332 333 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 334 { 335 struct rockchip_pinctrl *info = bank->drvdata; 336 void __iomem *reg = info->reg_base + info->ctrl->mux_offset; 337 u8 bit; 338 339 if (bank->bank_type == RK3188_BANK0 && pin < 16) 340 return RK_FUNC_GPIO; 341 342 /* get basic quadrupel of mux registers and the correct reg inside */ 343 reg += bank->bank_num * 0x10; 344 reg += (pin / 8) * 4; 345 bit = (pin % 8) * 2; 346 347 return ((readl(reg) >> bit) & 3); 348 } 349 350 /* 351 * Set a new mux function for a pin. 352 * 353 * The register is divided into the upper and lower 16 bit. When changing 354 * a value, the previous register value is not read and changed. Instead 355 * it seems the changed bits are marked in the upper 16 bit, while the 356 * changed value gets set in the same offset in the lower 16 bit. 357 * All pin settings seem to be 2 bit wide in both the upper and lower 358 * parts. 359 * @bank: pin bank to change 360 * @pin: pin to change 361 * @mux: new mux function to set 362 */ 363 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 364 { 365 struct rockchip_pinctrl *info = bank->drvdata; 366 void __iomem *reg = info->reg_base + info->ctrl->mux_offset; 367 unsigned long flags; 368 u8 bit; 369 u32 data; 370 371 /* 372 * The first 16 pins of rk3188_bank0 are always gpios and do not have 373 * a mux register at all. 374 */ 375 if (bank->bank_type == RK3188_BANK0 && pin < 16) { 376 if (mux != RK_FUNC_GPIO) { 377 dev_err(info->dev, 378 "pin %d only supports a gpio mux\n", pin); 379 return -ENOTSUPP; 380 } else { 381 return 0; 382 } 383 } 384 385 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 386 bank->bank_num, pin, mux); 387 388 /* get basic quadrupel of mux registers and the correct reg inside */ 389 reg += bank->bank_num * 0x10; 390 reg += (pin / 8) * 4; 391 bit = (pin % 8) * 2; 392 393 spin_lock_irqsave(&bank->slock, flags); 394 395 data = (3 << (bit + 16)); 396 data |= (mux & 3) << bit; 397 writel(data, reg); 398 399 spin_unlock_irqrestore(&bank->slock, flags); 400 401 return 0; 402 } 403 404 #define RK2928_PULL_OFFSET 0x118 405 #define RK2928_PULL_PINS_PER_REG 16 406 #define RK2928_PULL_BANK_STRIDE 8 407 408 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 409 int pin_num, void __iomem **reg, u8 *bit) 410 { 411 struct rockchip_pinctrl *info = bank->drvdata; 412 413 *reg = info->reg_base + RK2928_PULL_OFFSET; 414 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 415 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 416 417 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 418 }; 419 420 #define RK3188_PULL_OFFSET 0x164 421 #define RK3188_PULL_BITS_PER_PIN 2 422 #define RK3188_PULL_PINS_PER_REG 8 423 #define RK3188_PULL_BANK_STRIDE 16 424 425 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 426 int pin_num, void __iomem **reg, u8 *bit) 427 { 428 struct rockchip_pinctrl *info = bank->drvdata; 429 430 /* The first 12 pins of the first bank are located elsewhere */ 431 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) { 432 *reg = bank->reg_pull + 433 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 434 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 435 *bit *= RK3188_PULL_BITS_PER_PIN; 436 } else { 437 *reg = info->reg_pull ? info->reg_pull 438 : info->reg_base + RK3188_PULL_OFFSET; 439 /* correct the offset, as it is the 2nd pull register */ 440 *reg -= 4; 441 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 442 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 443 444 /* 445 * The bits in these registers have an inverse ordering 446 * with the lowest pin being in bits 15:14 and the highest 447 * pin in bits 1:0 448 */ 449 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 450 *bit *= RK3188_PULL_BITS_PER_PIN; 451 } 452 } 453 454 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 455 { 456 struct rockchip_pinctrl *info = bank->drvdata; 457 struct rockchip_pin_ctrl *ctrl = info->ctrl; 458 void __iomem *reg; 459 u8 bit; 460 u32 data; 461 462 /* rk3066b does support any pulls */ 463 if (ctrl->type == RK3066B) 464 return PIN_CONFIG_BIAS_DISABLE; 465 466 ctrl->pull_calc_reg(bank, pin_num, ®, &bit); 467 468 switch (ctrl->type) { 469 case RK2928: 470 return !(readl_relaxed(reg) & BIT(bit)) 471 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 472 : PIN_CONFIG_BIAS_DISABLE; 473 case RK3188: 474 data = readl_relaxed(reg) >> bit; 475 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 476 477 switch (data) { 478 case 0: 479 return PIN_CONFIG_BIAS_DISABLE; 480 case 1: 481 return PIN_CONFIG_BIAS_PULL_UP; 482 case 2: 483 return PIN_CONFIG_BIAS_PULL_DOWN; 484 case 3: 485 return PIN_CONFIG_BIAS_BUS_HOLD; 486 } 487 488 dev_err(info->dev, "unknown pull setting\n"); 489 return -EIO; 490 default: 491 dev_err(info->dev, "unsupported pinctrl type\n"); 492 return -EINVAL; 493 }; 494 } 495 496 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 497 int pin_num, int pull) 498 { 499 struct rockchip_pinctrl *info = bank->drvdata; 500 struct rockchip_pin_ctrl *ctrl = info->ctrl; 501 void __iomem *reg; 502 unsigned long flags; 503 u8 bit; 504 u32 data; 505 506 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 507 bank->bank_num, pin_num, pull); 508 509 /* rk3066b does support any pulls */ 510 if (ctrl->type == RK3066B) 511 return pull ? -EINVAL : 0; 512 513 ctrl->pull_calc_reg(bank, pin_num, ®, &bit); 514 515 switch (ctrl->type) { 516 case RK2928: 517 spin_lock_irqsave(&bank->slock, flags); 518 519 data = BIT(bit + 16); 520 if (pull == PIN_CONFIG_BIAS_DISABLE) 521 data |= BIT(bit); 522 writel(data, reg); 523 524 spin_unlock_irqrestore(&bank->slock, flags); 525 break; 526 case RK3188: 527 spin_lock_irqsave(&bank->slock, flags); 528 529 /* enable the write to the equivalent lower bits */ 530 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 531 532 switch (pull) { 533 case PIN_CONFIG_BIAS_DISABLE: 534 break; 535 case PIN_CONFIG_BIAS_PULL_UP: 536 data |= (1 << bit); 537 break; 538 case PIN_CONFIG_BIAS_PULL_DOWN: 539 data |= (2 << bit); 540 break; 541 case PIN_CONFIG_BIAS_BUS_HOLD: 542 data |= (3 << bit); 543 break; 544 default: 545 spin_unlock_irqrestore(&bank->slock, flags); 546 dev_err(info->dev, "unsupported pull setting %d\n", 547 pull); 548 return -EINVAL; 549 } 550 551 writel(data, reg); 552 553 spin_unlock_irqrestore(&bank->slock, flags); 554 break; 555 default: 556 dev_err(info->dev, "unsupported pinctrl type\n"); 557 return -EINVAL; 558 } 559 560 return 0; 561 } 562 563 /* 564 * Pinmux_ops handling 565 */ 566 567 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 568 { 569 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 570 571 return info->nfunctions; 572 } 573 574 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 575 unsigned selector) 576 { 577 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 578 579 return info->functions[selector].name; 580 } 581 582 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 583 unsigned selector, const char * const **groups, 584 unsigned * const num_groups) 585 { 586 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 587 588 *groups = info->functions[selector].groups; 589 *num_groups = info->functions[selector].ngroups; 590 591 return 0; 592 } 593 594 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 595 unsigned group) 596 { 597 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 598 const unsigned int *pins = info->groups[group].pins; 599 const struct rockchip_pin_config *data = info->groups[group].data; 600 struct rockchip_pin_bank *bank; 601 int cnt, ret = 0; 602 603 dev_dbg(info->dev, "enable function %s group %s\n", 604 info->functions[selector].name, info->groups[group].name); 605 606 /* 607 * for each pin in the pin group selected, program the correspoding pin 608 * pin function number in the config register. 609 */ 610 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 611 bank = pin_to_bank(info, pins[cnt]); 612 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 613 data[cnt].func); 614 if (ret) 615 break; 616 } 617 618 if (ret) { 619 /* revert the already done pin settings */ 620 for (cnt--; cnt >= 0; cnt--) 621 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 622 623 return ret; 624 } 625 626 return 0; 627 } 628 629 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev, 630 unsigned selector, unsigned group) 631 { 632 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 633 const unsigned int *pins = info->groups[group].pins; 634 struct rockchip_pin_bank *bank; 635 int cnt; 636 637 dev_dbg(info->dev, "disable function %s group %s\n", 638 info->functions[selector].name, info->groups[group].name); 639 640 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 641 bank = pin_to_bank(info, pins[cnt]); 642 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 643 } 644 } 645 646 /* 647 * The calls to gpio_direction_output() and gpio_direction_input() 648 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 649 * function called from the gpiolib interface). 650 */ 651 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 652 struct pinctrl_gpio_range *range, 653 unsigned offset, bool input) 654 { 655 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 656 struct rockchip_pin_bank *bank; 657 struct gpio_chip *chip; 658 int pin, ret; 659 u32 data; 660 661 chip = range->gc; 662 bank = gc_to_pin_bank(chip); 663 pin = offset - chip->base; 664 665 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 666 offset, range->name, pin, input ? "input" : "output"); 667 668 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 669 if (ret < 0) 670 return ret; 671 672 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 673 /* set bit to 1 for output, 0 for input */ 674 if (!input) 675 data |= BIT(pin); 676 else 677 data &= ~BIT(pin); 678 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 679 680 return 0; 681 } 682 683 static const struct pinmux_ops rockchip_pmx_ops = { 684 .get_functions_count = rockchip_pmx_get_funcs_count, 685 .get_function_name = rockchip_pmx_get_func_name, 686 .get_function_groups = rockchip_pmx_get_groups, 687 .enable = rockchip_pmx_enable, 688 .disable = rockchip_pmx_disable, 689 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 690 }; 691 692 /* 693 * Pinconf_ops handling 694 */ 695 696 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 697 enum pin_config_param pull) 698 { 699 switch (ctrl->type) { 700 case RK2928: 701 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 702 pull == PIN_CONFIG_BIAS_DISABLE); 703 case RK3066B: 704 return pull ? false : true; 705 case RK3188: 706 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 707 } 708 709 return false; 710 } 711 712 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 713 unsigned offset, int value); 714 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 715 716 /* set the pin config settings for a specified pin */ 717 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 718 unsigned long *configs, unsigned num_configs) 719 { 720 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 721 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 722 enum pin_config_param param; 723 u16 arg; 724 int i; 725 int rc; 726 727 for (i = 0; i < num_configs; i++) { 728 param = pinconf_to_config_param(configs[i]); 729 arg = pinconf_to_config_argument(configs[i]); 730 731 switch (param) { 732 case PIN_CONFIG_BIAS_DISABLE: 733 rc = rockchip_set_pull(bank, pin - bank->pin_base, 734 param); 735 if (rc) 736 return rc; 737 break; 738 case PIN_CONFIG_BIAS_PULL_UP: 739 case PIN_CONFIG_BIAS_PULL_DOWN: 740 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 741 case PIN_CONFIG_BIAS_BUS_HOLD: 742 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 743 return -ENOTSUPP; 744 745 if (!arg) 746 return -EINVAL; 747 748 rc = rockchip_set_pull(bank, pin - bank->pin_base, 749 param); 750 if (rc) 751 return rc; 752 break; 753 case PIN_CONFIG_OUTPUT: 754 rc = rockchip_gpio_direction_output(&bank->gpio_chip, 755 pin - bank->pin_base, 756 arg); 757 if (rc) 758 return rc; 759 break; 760 default: 761 return -ENOTSUPP; 762 break; 763 } 764 } /* for each config */ 765 766 return 0; 767 } 768 769 /* get the pin config settings for a specified pin */ 770 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 771 unsigned long *config) 772 { 773 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 774 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 775 enum pin_config_param param = pinconf_to_config_param(*config); 776 u16 arg; 777 int rc; 778 779 switch (param) { 780 case PIN_CONFIG_BIAS_DISABLE: 781 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 782 return -EINVAL; 783 784 arg = 0; 785 break; 786 case PIN_CONFIG_BIAS_PULL_UP: 787 case PIN_CONFIG_BIAS_PULL_DOWN: 788 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 789 case PIN_CONFIG_BIAS_BUS_HOLD: 790 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 791 return -ENOTSUPP; 792 793 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 794 return -EINVAL; 795 796 arg = 1; 797 break; 798 case PIN_CONFIG_OUTPUT: 799 rc = rockchip_get_mux(bank, pin - bank->pin_base); 800 if (rc != RK_FUNC_GPIO) 801 return -EINVAL; 802 803 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 804 if (rc < 0) 805 return rc; 806 807 arg = rc ? 1 : 0; 808 break; 809 default: 810 return -ENOTSUPP; 811 break; 812 } 813 814 *config = pinconf_to_config_packed(param, arg); 815 816 return 0; 817 } 818 819 static const struct pinconf_ops rockchip_pinconf_ops = { 820 .pin_config_get = rockchip_pinconf_get, 821 .pin_config_set = rockchip_pinconf_set, 822 }; 823 824 static const struct of_device_id rockchip_bank_match[] = { 825 { .compatible = "rockchip,gpio-bank" }, 826 { .compatible = "rockchip,rk3188-gpio-bank0" }, 827 {}, 828 }; 829 830 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 831 struct device_node *np) 832 { 833 struct device_node *child; 834 835 for_each_child_of_node(np, child) { 836 if (of_match_node(rockchip_bank_match, child)) 837 continue; 838 839 info->nfunctions++; 840 info->ngroups += of_get_child_count(child); 841 } 842 } 843 844 static int rockchip_pinctrl_parse_groups(struct device_node *np, 845 struct rockchip_pin_group *grp, 846 struct rockchip_pinctrl *info, 847 u32 index) 848 { 849 struct rockchip_pin_bank *bank; 850 int size; 851 const __be32 *list; 852 int num; 853 int i, j; 854 int ret; 855 856 dev_dbg(info->dev, "group(%d): %s\n", index, np->name); 857 858 /* Initialise group */ 859 grp->name = np->name; 860 861 /* 862 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 863 * do sanity check and calculate pins number 864 */ 865 list = of_get_property(np, "rockchip,pins", &size); 866 /* we do not check return since it's safe node passed down */ 867 size /= sizeof(*list); 868 if (!size || size % 4) { 869 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 870 return -EINVAL; 871 } 872 873 grp->npins = size / 4; 874 875 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), 876 GFP_KERNEL); 877 grp->data = devm_kzalloc(info->dev, grp->npins * 878 sizeof(struct rockchip_pin_config), 879 GFP_KERNEL); 880 if (!grp->pins || !grp->data) 881 return -ENOMEM; 882 883 for (i = 0, j = 0; i < size; i += 4, j++) { 884 const __be32 *phandle; 885 struct device_node *np_config; 886 887 num = be32_to_cpu(*list++); 888 bank = bank_num_to_bank(info, num); 889 if (IS_ERR(bank)) 890 return PTR_ERR(bank); 891 892 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 893 grp->data[j].func = be32_to_cpu(*list++); 894 895 phandle = list++; 896 if (!phandle) 897 return -EINVAL; 898 899 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 900 ret = pinconf_generic_parse_dt_config(np_config, 901 &grp->data[j].configs, &grp->data[j].nconfigs); 902 if (ret) 903 return ret; 904 } 905 906 return 0; 907 } 908 909 static int rockchip_pinctrl_parse_functions(struct device_node *np, 910 struct rockchip_pinctrl *info, 911 u32 index) 912 { 913 struct device_node *child; 914 struct rockchip_pmx_func *func; 915 struct rockchip_pin_group *grp; 916 int ret; 917 static u32 grp_index; 918 u32 i = 0; 919 920 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 921 922 func = &info->functions[index]; 923 924 /* Initialise function */ 925 func->name = np->name; 926 func->ngroups = of_get_child_count(np); 927 if (func->ngroups <= 0) 928 return 0; 929 930 func->groups = devm_kzalloc(info->dev, 931 func->ngroups * sizeof(char *), GFP_KERNEL); 932 if (!func->groups) 933 return -ENOMEM; 934 935 for_each_child_of_node(np, child) { 936 func->groups[i] = child->name; 937 grp = &info->groups[grp_index++]; 938 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 939 if (ret) 940 return ret; 941 } 942 943 return 0; 944 } 945 946 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 947 struct rockchip_pinctrl *info) 948 { 949 struct device *dev = &pdev->dev; 950 struct device_node *np = dev->of_node; 951 struct device_node *child; 952 int ret; 953 int i; 954 955 rockchip_pinctrl_child_count(info, np); 956 957 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 958 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 959 960 info->functions = devm_kzalloc(dev, info->nfunctions * 961 sizeof(struct rockchip_pmx_func), 962 GFP_KERNEL); 963 if (!info->functions) { 964 dev_err(dev, "failed to allocate memory for function list\n"); 965 return -EINVAL; 966 } 967 968 info->groups = devm_kzalloc(dev, info->ngroups * 969 sizeof(struct rockchip_pin_group), 970 GFP_KERNEL); 971 if (!info->groups) { 972 dev_err(dev, "failed allocate memory for ping group list\n"); 973 return -EINVAL; 974 } 975 976 i = 0; 977 978 for_each_child_of_node(np, child) { 979 if (of_match_node(rockchip_bank_match, child)) 980 continue; 981 982 ret = rockchip_pinctrl_parse_functions(child, info, i++); 983 if (ret) { 984 dev_err(&pdev->dev, "failed to parse function\n"); 985 return ret; 986 } 987 } 988 989 return 0; 990 } 991 992 static int rockchip_pinctrl_register(struct platform_device *pdev, 993 struct rockchip_pinctrl *info) 994 { 995 struct pinctrl_desc *ctrldesc = &info->pctl; 996 struct pinctrl_pin_desc *pindesc, *pdesc; 997 struct rockchip_pin_bank *pin_bank; 998 int pin, bank, ret; 999 int k; 1000 1001 ctrldesc->name = "rockchip-pinctrl"; 1002 ctrldesc->owner = THIS_MODULE; 1003 ctrldesc->pctlops = &rockchip_pctrl_ops; 1004 ctrldesc->pmxops = &rockchip_pmx_ops; 1005 ctrldesc->confops = &rockchip_pinconf_ops; 1006 1007 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 1008 info->ctrl->nr_pins, GFP_KERNEL); 1009 if (!pindesc) { 1010 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 1011 return -ENOMEM; 1012 } 1013 ctrldesc->pins = pindesc; 1014 ctrldesc->npins = info->ctrl->nr_pins; 1015 1016 pdesc = pindesc; 1017 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 1018 pin_bank = &info->ctrl->pin_banks[bank]; 1019 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 1020 pdesc->number = k; 1021 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 1022 pin_bank->name, pin); 1023 pdesc++; 1024 } 1025 } 1026 1027 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); 1028 if (!info->pctl_dev) { 1029 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 1030 return -EINVAL; 1031 } 1032 1033 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 1034 pin_bank = &info->ctrl->pin_banks[bank]; 1035 pin_bank->grange.name = pin_bank->name; 1036 pin_bank->grange.id = bank; 1037 pin_bank->grange.pin_base = pin_bank->pin_base; 1038 pin_bank->grange.base = pin_bank->gpio_chip.base; 1039 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 1040 pin_bank->grange.gc = &pin_bank->gpio_chip; 1041 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 1042 } 1043 1044 ret = rockchip_pinctrl_parse_dt(pdev, info); 1045 if (ret) { 1046 pinctrl_unregister(info->pctl_dev); 1047 return ret; 1048 } 1049 1050 return 0; 1051 } 1052 1053 /* 1054 * GPIO handling 1055 */ 1056 1057 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset) 1058 { 1059 return pinctrl_request_gpio(chip->base + offset); 1060 } 1061 1062 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset) 1063 { 1064 pinctrl_free_gpio(chip->base + offset); 1065 } 1066 1067 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 1068 { 1069 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1070 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 1071 unsigned long flags; 1072 u32 data; 1073 1074 spin_lock_irqsave(&bank->slock, flags); 1075 1076 data = readl(reg); 1077 data &= ~BIT(offset); 1078 if (value) 1079 data |= BIT(offset); 1080 writel(data, reg); 1081 1082 spin_unlock_irqrestore(&bank->slock, flags); 1083 } 1084 1085 /* 1086 * Returns the level of the pin for input direction and setting of the DR 1087 * register for output gpios. 1088 */ 1089 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 1090 { 1091 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1092 u32 data; 1093 1094 data = readl(bank->reg_base + GPIO_EXT_PORT); 1095 data >>= offset; 1096 data &= 1; 1097 return data; 1098 } 1099 1100 /* 1101 * gpiolib gpio_direction_input callback function. The setting of the pin 1102 * mux function as 'gpio input' will be handled by the pinctrl susbsystem 1103 * interface. 1104 */ 1105 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 1106 { 1107 return pinctrl_gpio_direction_input(gc->base + offset); 1108 } 1109 1110 /* 1111 * gpiolib gpio_direction_output callback function. The setting of the pin 1112 * mux function as 'gpio output' will be handled by the pinctrl susbsystem 1113 * interface. 1114 */ 1115 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 1116 unsigned offset, int value) 1117 { 1118 rockchip_gpio_set(gc, offset, value); 1119 return pinctrl_gpio_direction_output(gc->base + offset); 1120 } 1121 1122 /* 1123 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 1124 * and a virtual IRQ, if not already present. 1125 */ 1126 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 1127 { 1128 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1129 unsigned int virq; 1130 1131 if (!bank->domain) 1132 return -ENXIO; 1133 1134 virq = irq_create_mapping(bank->domain, offset); 1135 1136 return (virq) ? : -ENXIO; 1137 } 1138 1139 static const struct gpio_chip rockchip_gpiolib_chip = { 1140 .request = rockchip_gpio_request, 1141 .free = rockchip_gpio_free, 1142 .set = rockchip_gpio_set, 1143 .get = rockchip_gpio_get, 1144 .direction_input = rockchip_gpio_direction_input, 1145 .direction_output = rockchip_gpio_direction_output, 1146 .to_irq = rockchip_gpio_to_irq, 1147 .owner = THIS_MODULE, 1148 }; 1149 1150 /* 1151 * Interrupt handling 1152 */ 1153 1154 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) 1155 { 1156 struct irq_chip *chip = irq_get_chip(irq); 1157 struct rockchip_pin_bank *bank = irq_get_handler_data(irq); 1158 u32 polarity = 0, data = 0; 1159 u32 pend; 1160 bool edge_changed = false; 1161 1162 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 1163 1164 chained_irq_enter(chip, desc); 1165 1166 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 1167 1168 if (bank->toggle_edge_mode) { 1169 polarity = readl_relaxed(bank->reg_base + 1170 GPIO_INT_POLARITY); 1171 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 1172 } 1173 1174 while (pend) { 1175 unsigned int virq; 1176 1177 irq = __ffs(pend); 1178 pend &= ~BIT(irq); 1179 virq = irq_linear_revmap(bank->domain, irq); 1180 1181 if (!virq) { 1182 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 1183 continue; 1184 } 1185 1186 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 1187 1188 /* 1189 * Triggering IRQ on both rising and falling edge 1190 * needs manual intervention. 1191 */ 1192 if (bank->toggle_edge_mode & BIT(irq)) { 1193 if (data & BIT(irq)) 1194 polarity &= ~BIT(irq); 1195 else 1196 polarity |= BIT(irq); 1197 1198 edge_changed = true; 1199 } 1200 1201 generic_handle_irq(virq); 1202 } 1203 1204 if (bank->toggle_edge_mode && edge_changed) { 1205 /* Interrupt params should only be set with ints disabled */ 1206 data = readl_relaxed(bank->reg_base + GPIO_INTEN); 1207 writel_relaxed(0, bank->reg_base + GPIO_INTEN); 1208 writel(polarity, bank->reg_base + GPIO_INT_POLARITY); 1209 writel(data, bank->reg_base + GPIO_INTEN); 1210 } 1211 1212 chained_irq_exit(chip, desc); 1213 } 1214 1215 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 1216 { 1217 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1218 struct rockchip_pin_bank *bank = gc->private; 1219 u32 mask = BIT(d->hwirq); 1220 u32 polarity; 1221 u32 level; 1222 u32 data; 1223 int ret; 1224 1225 /* make sure the pin is configured as gpio input */ 1226 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 1227 if (ret < 0) 1228 return ret; 1229 1230 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1231 data &= ~mask; 1232 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 1233 1234 if (type & IRQ_TYPE_EDGE_BOTH) 1235 __irq_set_handler_locked(d->irq, handle_edge_irq); 1236 else 1237 __irq_set_handler_locked(d->irq, handle_level_irq); 1238 1239 irq_gc_lock(gc); 1240 1241 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 1242 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 1243 1244 switch (type) { 1245 case IRQ_TYPE_EDGE_BOTH: 1246 bank->toggle_edge_mode |= mask; 1247 level |= mask; 1248 1249 /* 1250 * Determine gpio state. If 1 next interrupt should be falling 1251 * otherwise rising. 1252 */ 1253 data = readl(bank->reg_base + GPIO_EXT_PORT); 1254 if (data & mask) 1255 polarity &= ~mask; 1256 else 1257 polarity |= mask; 1258 break; 1259 case IRQ_TYPE_EDGE_RISING: 1260 bank->toggle_edge_mode &= ~mask; 1261 level |= mask; 1262 polarity |= mask; 1263 break; 1264 case IRQ_TYPE_EDGE_FALLING: 1265 bank->toggle_edge_mode &= ~mask; 1266 level |= mask; 1267 polarity &= ~mask; 1268 break; 1269 case IRQ_TYPE_LEVEL_HIGH: 1270 bank->toggle_edge_mode &= ~mask; 1271 level &= ~mask; 1272 polarity |= mask; 1273 break; 1274 case IRQ_TYPE_LEVEL_LOW: 1275 bank->toggle_edge_mode &= ~mask; 1276 level &= ~mask; 1277 polarity &= ~mask; 1278 break; 1279 default: 1280 irq_gc_unlock(gc); 1281 return -EINVAL; 1282 } 1283 1284 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 1285 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 1286 1287 irq_gc_unlock(gc); 1288 1289 return 0; 1290 } 1291 1292 static int rockchip_interrupts_register(struct platform_device *pdev, 1293 struct rockchip_pinctrl *info) 1294 { 1295 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1296 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1297 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 1298 struct irq_chip_generic *gc; 1299 int ret; 1300 int i; 1301 1302 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1303 if (!bank->valid) { 1304 dev_warn(&pdev->dev, "bank %s is not valid\n", 1305 bank->name); 1306 continue; 1307 } 1308 1309 bank->domain = irq_domain_add_linear(bank->of_node, 32, 1310 &irq_generic_chip_ops, NULL); 1311 if (!bank->domain) { 1312 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 1313 bank->name); 1314 continue; 1315 } 1316 1317 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 1318 "rockchip_gpio_irq", handle_level_irq, 1319 clr, 0, IRQ_GC_INIT_MASK_CACHE); 1320 if (ret) { 1321 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 1322 bank->name); 1323 irq_domain_remove(bank->domain); 1324 continue; 1325 } 1326 1327 gc = irq_get_domain_generic_chip(bank->domain, 0); 1328 gc->reg_base = bank->reg_base; 1329 gc->private = bank; 1330 gc->chip_types[0].regs.mask = GPIO_INTEN; 1331 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 1332 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 1333 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; 1334 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; 1335 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 1336 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 1337 1338 irq_set_handler_data(bank->irq, bank); 1339 irq_set_chained_handler(bank->irq, rockchip_irq_demux); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int rockchip_gpiolib_register(struct platform_device *pdev, 1346 struct rockchip_pinctrl *info) 1347 { 1348 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1349 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1350 struct gpio_chip *gc; 1351 int ret; 1352 int i; 1353 1354 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1355 if (!bank->valid) { 1356 dev_warn(&pdev->dev, "bank %s is not valid\n", 1357 bank->name); 1358 continue; 1359 } 1360 1361 bank->gpio_chip = rockchip_gpiolib_chip; 1362 1363 gc = &bank->gpio_chip; 1364 gc->base = bank->pin_base; 1365 gc->ngpio = bank->nr_pins; 1366 gc->dev = &pdev->dev; 1367 gc->of_node = bank->of_node; 1368 gc->label = bank->name; 1369 1370 ret = gpiochip_add(gc); 1371 if (ret) { 1372 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 1373 gc->label, ret); 1374 goto fail; 1375 } 1376 } 1377 1378 rockchip_interrupts_register(pdev, info); 1379 1380 return 0; 1381 1382 fail: 1383 for (--i, --bank; i >= 0; --i, --bank) { 1384 if (!bank->valid) 1385 continue; 1386 1387 if (gpiochip_remove(&bank->gpio_chip)) 1388 dev_err(&pdev->dev, "gpio chip %s remove failed\n", 1389 bank->gpio_chip.label); 1390 } 1391 return ret; 1392 } 1393 1394 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 1395 struct rockchip_pinctrl *info) 1396 { 1397 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1398 struct rockchip_pin_bank *bank = ctrl->pin_banks; 1399 int ret = 0; 1400 int i; 1401 1402 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) { 1403 if (!bank->valid) 1404 continue; 1405 1406 ret = gpiochip_remove(&bank->gpio_chip); 1407 } 1408 1409 if (ret) 1410 dev_err(&pdev->dev, "gpio chip remove failed\n"); 1411 1412 return ret; 1413 } 1414 1415 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 1416 struct device *dev) 1417 { 1418 struct resource res; 1419 1420 if (of_address_to_resource(bank->of_node, 0, &res)) { 1421 dev_err(dev, "cannot find IO resource for bank\n"); 1422 return -ENOENT; 1423 } 1424 1425 bank->reg_base = devm_ioremap_resource(dev, &res); 1426 if (IS_ERR(bank->reg_base)) 1427 return PTR_ERR(bank->reg_base); 1428 1429 /* 1430 * special case, where parts of the pull setting-registers are 1431 * part of the PMU register space 1432 */ 1433 if (of_device_is_compatible(bank->of_node, 1434 "rockchip,rk3188-gpio-bank0")) { 1435 1436 bank->bank_type = RK3188_BANK0; 1437 1438 if (of_address_to_resource(bank->of_node, 1, &res)) { 1439 dev_err(dev, "cannot find IO resource for bank\n"); 1440 return -ENOENT; 1441 } 1442 1443 bank->reg_pull = devm_ioremap_resource(dev, &res); 1444 if (IS_ERR(bank->reg_pull)) 1445 return PTR_ERR(bank->reg_pull); 1446 } else { 1447 bank->bank_type = COMMON_BANK; 1448 } 1449 1450 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 1451 1452 bank->clk = of_clk_get(bank->of_node, 0); 1453 if (IS_ERR(bank->clk)) 1454 return PTR_ERR(bank->clk); 1455 1456 return clk_prepare_enable(bank->clk); 1457 } 1458 1459 static const struct of_device_id rockchip_pinctrl_dt_match[]; 1460 1461 /* retrieve the soc specific data */ 1462 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 1463 struct rockchip_pinctrl *d, 1464 struct platform_device *pdev) 1465 { 1466 const struct of_device_id *match; 1467 struct device_node *node = pdev->dev.of_node; 1468 struct device_node *np; 1469 struct rockchip_pin_ctrl *ctrl; 1470 struct rockchip_pin_bank *bank; 1471 int i; 1472 1473 match = of_match_node(rockchip_pinctrl_dt_match, node); 1474 ctrl = (struct rockchip_pin_ctrl *)match->data; 1475 1476 for_each_child_of_node(node, np) { 1477 if (!of_find_property(np, "gpio-controller", NULL)) 1478 continue; 1479 1480 bank = ctrl->pin_banks; 1481 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1482 if (!strcmp(bank->name, np->name)) { 1483 bank->of_node = np; 1484 1485 if (!rockchip_get_bank_data(bank, &pdev->dev)) 1486 bank->valid = true; 1487 1488 break; 1489 } 1490 } 1491 } 1492 1493 bank = ctrl->pin_banks; 1494 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1495 spin_lock_init(&bank->slock); 1496 bank->drvdata = d; 1497 bank->pin_base = ctrl->nr_pins; 1498 ctrl->nr_pins += bank->nr_pins; 1499 } 1500 1501 return ctrl; 1502 } 1503 1504 static int rockchip_pinctrl_probe(struct platform_device *pdev) 1505 { 1506 struct rockchip_pinctrl *info; 1507 struct device *dev = &pdev->dev; 1508 struct rockchip_pin_ctrl *ctrl; 1509 struct resource *res; 1510 int ret; 1511 1512 if (!dev->of_node) { 1513 dev_err(dev, "device tree node not found\n"); 1514 return -ENODEV; 1515 } 1516 1517 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); 1518 if (!info) 1519 return -ENOMEM; 1520 1521 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 1522 if (!ctrl) { 1523 dev_err(dev, "driver data not available\n"); 1524 return -EINVAL; 1525 } 1526 info->ctrl = ctrl; 1527 info->dev = dev; 1528 1529 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1530 info->reg_base = devm_ioremap_resource(&pdev->dev, res); 1531 if (IS_ERR(info->reg_base)) 1532 return PTR_ERR(info->reg_base); 1533 1534 /* to check for the old dt-bindings */ 1535 info->reg_size = resource_size(res); 1536 1537 /* Honor the old binding, with pull registers as 2nd resource */ 1538 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 1539 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1540 info->reg_pull = devm_ioremap_resource(&pdev->dev, res); 1541 if (IS_ERR(info->reg_pull)) 1542 return PTR_ERR(info->reg_pull); 1543 } 1544 1545 ret = rockchip_gpiolib_register(pdev, info); 1546 if (ret) 1547 return ret; 1548 1549 ret = rockchip_pinctrl_register(pdev, info); 1550 if (ret) { 1551 rockchip_gpiolib_unregister(pdev, info); 1552 return ret; 1553 } 1554 1555 platform_set_drvdata(pdev, info); 1556 1557 return 0; 1558 } 1559 1560 static struct rockchip_pin_bank rk2928_pin_banks[] = { 1561 PIN_BANK(0, 32, "gpio0"), 1562 PIN_BANK(1, 32, "gpio1"), 1563 PIN_BANK(2, 32, "gpio2"), 1564 PIN_BANK(3, 32, "gpio3"), 1565 }; 1566 1567 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 1568 .pin_banks = rk2928_pin_banks, 1569 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 1570 .label = "RK2928-GPIO", 1571 .type = RK2928, 1572 .mux_offset = 0xa8, 1573 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 1574 }; 1575 1576 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 1577 PIN_BANK(0, 32, "gpio0"), 1578 PIN_BANK(1, 32, "gpio1"), 1579 PIN_BANK(2, 32, "gpio2"), 1580 PIN_BANK(3, 32, "gpio3"), 1581 PIN_BANK(4, 32, "gpio4"), 1582 PIN_BANK(6, 16, "gpio6"), 1583 }; 1584 1585 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 1586 .pin_banks = rk3066a_pin_banks, 1587 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 1588 .label = "RK3066a-GPIO", 1589 .type = RK2928, 1590 .mux_offset = 0xa8, 1591 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 1592 }; 1593 1594 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 1595 PIN_BANK(0, 32, "gpio0"), 1596 PIN_BANK(1, 32, "gpio1"), 1597 PIN_BANK(2, 32, "gpio2"), 1598 PIN_BANK(3, 32, "gpio3"), 1599 }; 1600 1601 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 1602 .pin_banks = rk3066b_pin_banks, 1603 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 1604 .label = "RK3066b-GPIO", 1605 .type = RK3066B, 1606 .mux_offset = 0x60, 1607 }; 1608 1609 static struct rockchip_pin_bank rk3188_pin_banks[] = { 1610 PIN_BANK(0, 32, "gpio0"), 1611 PIN_BANK(1, 32, "gpio1"), 1612 PIN_BANK(2, 32, "gpio2"), 1613 PIN_BANK(3, 32, "gpio3"), 1614 }; 1615 1616 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 1617 .pin_banks = rk3188_pin_banks, 1618 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 1619 .label = "RK3188-GPIO", 1620 .type = RK3188, 1621 .mux_offset = 0x60, 1622 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 1623 }; 1624 1625 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 1626 { .compatible = "rockchip,rk2928-pinctrl", 1627 .data = (void *)&rk2928_pin_ctrl }, 1628 { .compatible = "rockchip,rk3066a-pinctrl", 1629 .data = (void *)&rk3066a_pin_ctrl }, 1630 { .compatible = "rockchip,rk3066b-pinctrl", 1631 .data = (void *)&rk3066b_pin_ctrl }, 1632 { .compatible = "rockchip,rk3188-pinctrl", 1633 .data = (void *)&rk3188_pin_ctrl }, 1634 {}, 1635 }; 1636 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); 1637 1638 static struct platform_driver rockchip_pinctrl_driver = { 1639 .probe = rockchip_pinctrl_probe, 1640 .driver = { 1641 .name = "rockchip-pinctrl", 1642 .owner = THIS_MODULE, 1643 .of_match_table = rockchip_pinctrl_dt_match, 1644 }, 1645 }; 1646 1647 static int __init rockchip_pinctrl_drv_register(void) 1648 { 1649 return platform_driver_register(&rockchip_pinctrl_driver); 1650 } 1651 postcore_initcall(rockchip_pinctrl_drv_register); 1652 1653 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); 1654 MODULE_DESCRIPTION("Rockchip pinctrl driver"); 1655 MODULE_LICENSE("GPL v2"); 1656