| Kconfig (9d066a252786e1a18484a6283f82614d42a9f4ac) | Kconfig (4e80c8f505741cbdef3e10862ea36057e8d85e7c) |
|---|---|
| 1# 2# Intel pin control drivers 3# 4 5config PINCTRL_BAYTRAIL 6 bool "Intel Baytrail GPIO pin control" 7 depends on GPIOLIB && ACPI 8 select GPIOLIB_IRQCHIP --- 15 unchanged lines hidden (view full) --- 24 select PINCONF 25 select GENERIC_PINCONF 26 select GPIOLIB 27 select GPIOLIB_IRQCHIP 28 help 29 Cherryview/Braswell pinctrl driver provides an interface that 30 allows configuring of SoC pins and using them as GPIOs. 31 | 1# 2# Intel pin control drivers 3# 4 5config PINCTRL_BAYTRAIL 6 bool "Intel Baytrail GPIO pin control" 7 depends on GPIOLIB && ACPI 8 select GPIOLIB_IRQCHIP --- 15 unchanged lines hidden (view full) --- 24 select PINCONF 25 select GENERIC_PINCONF 26 select GPIOLIB 27 select GPIOLIB_IRQCHIP 28 help 29 Cherryview/Braswell pinctrl driver provides an interface that 30 allows configuring of SoC pins and using them as GPIOs. 31 |
| 32config PINCTRL_MERRIFIELD 33 tristate "Intel Merrifield pinctrl driver" 34 depends on X86_INTEL_MID 35 select PINMUX 36 select PINCONF 37 select GENERIC_PINCONF 38 help 39 Merrifield Family-Level Interface Shim (FLIS) driver provides an 40 interface that allows configuring of SoC pins and using them as 41 GPIOs. 42 |
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| 32config PINCTRL_INTEL 33 tristate 34 select PINMUX 35 select PINCONF 36 select GENERIC_PINCONF 37 select GPIOLIB 38 select GPIOLIB_IRQCHIP 39 --- 16 unchanged lines hidden --- | 43config PINCTRL_INTEL 44 tristate 45 select PINMUX 46 select PINCONF 47 select GENERIC_PINCONF 48 select GPIOLIB 49 select GPIOLIB_IRQCHIP 50 --- 16 unchanged lines hidden --- |