| Kconfig (22f57707fa0c17072851de60706d01f5836cd36b) | Kconfig (c5860e4a2737a8b29dc426c800d01c5be6aad811) |
|---|---|
| 1# SPDX-License-Identifier: GPL-2.0 2# Intel pin control drivers 3menu "Intel pinctrl drivers" 4 depends on (ACPI && X86) || COMPILE_TEST 5 6config PINCTRL_BAYTRAIL 7 bool "Intel Baytrail GPIO pin control" 8 select PINCTRL_INTEL --- 23 unchanged lines hidden (view full) --- 32config PINCTRL_INTEL 33 tristate 34 select PINMUX 35 select PINCONF 36 select GENERIC_PINCONF 37 select GPIOLIB 38 select GPIOLIB_IRQCHIP 39 | 1# SPDX-License-Identifier: GPL-2.0 2# Intel pin control drivers 3menu "Intel pinctrl drivers" 4 depends on (ACPI && X86) || COMPILE_TEST 5 6config PINCTRL_BAYTRAIL 7 bool "Intel Baytrail GPIO pin control" 8 select PINCTRL_INTEL --- 23 unchanged lines hidden (view full) --- 32config PINCTRL_INTEL 33 tristate 34 select PINMUX 35 select PINCONF 36 select GENERIC_PINCONF 37 select GPIOLIB 38 select GPIOLIB_IRQCHIP 39 |
| 40config PINCTRL_INTEL_PLATFORM 41 tristate "Intel pinctrl and GPIO platform driver" 42 depends on ACPI 43 select PINCTRL_INTEL 44 help 45 This pinctrl driver provides an interface that allows configuring 46 of Intel PCH pins and using them as GPIOs. Currently the following 47 Intel SoCs / platforms require this to be functional: 48 - Lunar Lake 49 |
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| 40config PINCTRL_ALDERLAKE 41 tristate "Intel Alder Lake pinctrl and GPIO driver" 42 select PINCTRL_INTEL 43 help 44 This pinctrl driver provides an interface that allows configuring 45 of Intel Alder Lake PCH pins and using them as GPIOs. 46 47config PINCTRL_BROXTON --- 100 unchanged lines hidden --- | 50config PINCTRL_ALDERLAKE 51 tristate "Intel Alder Lake pinctrl and GPIO driver" 52 select PINCTRL_INTEL 53 help 54 This pinctrl driver provides an interface that allows configuring 55 of Intel Alder Lake PCH pins and using them as GPIOs. 56 57config PINCTRL_BROXTON --- 100 unchanged lines hidden --- |