regs.h (b662b71ac3cccb50e9a45aae194591fc50e433ce) regs.h (4dbcb9125cc3e10a6d879c10e4f5816d05a87c49)
1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT7915_REGS_H
5#define __MT7915_REGS_H
6
7/* used to differentiate between generations */
8struct mt7915_reg_desc {

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19 INT1_MASK_CSR,
20 INT_MCU_CMD_SOURCE,
21 INT_MCU_CMD_EVENT,
22 WFDMA0_ADDR,
23 WFDMA0_PCIE1_ADDR,
24 WFDMA_EXT_CSR_ADDR,
25 CBTOP1_PHY_END,
26 INFRA_MCU_ADDR_END,
1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT7915_REGS_H
5#define __MT7915_REGS_H
6
7/* used to differentiate between generations */
8struct mt7915_reg_desc {

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19 INT1_MASK_CSR,
20 INT_MCU_CMD_SOURCE,
21 INT_MCU_CMD_EVENT,
22 WFDMA0_ADDR,
23 WFDMA0_PCIE1_ADDR,
24 WFDMA_EXT_CSR_ADDR,
25 CBTOP1_PHY_END,
26 INFRA_MCU_ADDR_END,
27 FW_EXCEPTION_ADDR,
27 FW_ASSERT_STAT_ADDR,
28 FW_EXCEPT_TYPE_ADDR,
29 FW_EXCEPT_COUNT_ADDR,
30 FW_CIRQ_COUNT_ADDR,
31 FW_CIRQ_IDX_ADDR,
32 FW_CIRQ_LISR_ADDR,
33 FW_TASK_ID_ADDR,
34 FW_TASK_IDX_ADDR,
35 FW_TASK_QID1_ADDR,
36 FW_TASK_QID2_ADDR,
37 FW_TASK_START_ADDR,
38 FW_TASK_END_ADDR,
39 FW_TASK_SIZE_ADDR,
40 FW_LAST_MSG_ID_ADDR,
41 FW_EINT_INFO_ADDR,
42 FW_SCHED_INFO_ADDR,
28 SWDEF_BASE_ADDR,
29 TXQ_WED_RING_BASE,
30 RXQ_WED_RING_BASE,
31 __MT_REG_MAX,
32};
33
34enum offs_rev {
35 TMAC_CDTR,

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974#define MT_INFRA_BUS_EMI_END MT_INFRA_BUS(0x364)
975
976/* CONN_INFRA_SKU */
977#define MT_CONNINFRA_SKU_DEC_ADDR 0x18050000
978#define MT_CONNINFRA_SKU_MASK GENMASK(15, 0)
979#define MT_ADIE_TYPE_MASK BIT(1)
980
981/* FW MODE SYNC */
43 SWDEF_BASE_ADDR,
44 TXQ_WED_RING_BASE,
45 RXQ_WED_RING_BASE,
46 __MT_REG_MAX,
47};
48
49enum offs_rev {
50 TMAC_CDTR,

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989#define MT_INFRA_BUS_EMI_END MT_INFRA_BUS(0x364)
990
991/* CONN_INFRA_SKU */
992#define MT_CONNINFRA_SKU_DEC_ADDR 0x18050000
993#define MT_CONNINFRA_SKU_MASK GENMASK(15, 0)
994#define MT_ADIE_TYPE_MASK BIT(1)
995
996/* FW MODE SYNC */
982#define MT_FW_EXCEPTION __REG(FW_EXCEPTION_ADDR)
997#define MT_FW_ASSERT_STAT __REG(FW_ASSERT_STAT_ADDR)
998#define MT_FW_EXCEPT_TYPE __REG(FW_EXCEPT_TYPE_ADDR)
999#define MT_FW_EXCEPT_COUNT __REG(FW_EXCEPT_COUNT_ADDR)
1000#define MT_FW_CIRQ_COUNT __REG(FW_CIRQ_COUNT_ADDR)
1001#define MT_FW_CIRQ_IDX __REG(FW_CIRQ_IDX_ADDR)
1002#define MT_FW_CIRQ_LISR __REG(FW_CIRQ_LISR_ADDR)
1003#define MT_FW_TASK_ID __REG(FW_TASK_ID_ADDR)
1004#define MT_FW_TASK_IDX __REG(FW_TASK_IDX_ADDR)
1005#define MT_FW_TASK_QID1 __REG(FW_TASK_QID1_ADDR)
1006#define MT_FW_TASK_QID2 __REG(FW_TASK_QID2_ADDR)
1007#define MT_FW_TASK_START __REG(FW_TASK_START_ADDR)
1008#define MT_FW_TASK_END __REG(FW_TASK_END_ADDR)
1009#define MT_FW_TASK_SIZE __REG(FW_TASK_SIZE_ADDR)
1010#define MT_FW_LAST_MSG_ID __REG(FW_LAST_MSG_ID_ADDR)
1011#define MT_FW_EINT_INFO __REG(FW_EINT_INFO_ADDR)
1012#define MT_FW_SCHED_INFO __REG(FW_SCHED_INFO_ADDR)
983
984#define MT_SWDEF_BASE __REG(SWDEF_BASE_ADDR)
985
986#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))
987#define MT_SWDEF_MODE MT_SWDEF(0x3c)
988#define MT_SWDEF_NORMAL_MODE 0
989#define MT_SWDEF_ICAP_MODE 1
990#define MT_SWDEF_SPECTRUM_MODE 2

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1014#define MT_SWDEF_BASE __REG(SWDEF_BASE_ADDR)
1015
1016#define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))
1017#define MT_SWDEF_MODE MT_SWDEF(0x3c)
1018#define MT_SWDEF_NORMAL_MODE 0
1019#define MT_SWDEF_ICAP_MODE 1
1020#define MT_SWDEF_SPECTRUM_MODE 2

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