1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_REGS_H 5 #define __MT7915_REGS_H 6 7 /* used to differentiate between generations */ 8 struct mt7915_reg_desc { 9 const u32 *reg_rev; 10 const u32 *offs_rev; 11 const struct mt76_connac_reg_map *map; 12 u32 map_size; 13 }; 14 15 enum reg_rev { 16 INT_SOURCE_CSR, 17 INT_MASK_CSR, 18 INT1_SOURCE_CSR, 19 INT1_MASK_CSR, 20 INT_MCU_CMD_SOURCE, 21 INT_MCU_CMD_EVENT, 22 WFDMA0_ADDR, 23 WFDMA0_PCIE1_ADDR, 24 WFDMA_EXT_CSR_ADDR, 25 CBTOP1_PHY_END, 26 INFRA_MCU_ADDR_END, 27 FW_ASSERT_STAT_ADDR, 28 FW_EXCEPT_TYPE_ADDR, 29 FW_EXCEPT_COUNT_ADDR, 30 FW_CIRQ_COUNT_ADDR, 31 FW_CIRQ_IDX_ADDR, 32 FW_CIRQ_LISR_ADDR, 33 FW_TASK_ID_ADDR, 34 FW_TASK_IDX_ADDR, 35 FW_TASK_QID1_ADDR, 36 FW_TASK_QID2_ADDR, 37 FW_TASK_START_ADDR, 38 FW_TASK_END_ADDR, 39 FW_TASK_SIZE_ADDR, 40 FW_LAST_MSG_ID_ADDR, 41 FW_EINT_INFO_ADDR, 42 FW_SCHED_INFO_ADDR, 43 SWDEF_BASE_ADDR, 44 TXQ_WED_RING_BASE, 45 RXQ_WED_RING_BASE, 46 __MT_REG_MAX, 47 }; 48 49 enum offs_rev { 50 TMAC_CDTR, 51 TMAC_ODTR, 52 TMAC_ATCR, 53 TMAC_TRCR0, 54 TMAC_ICR0, 55 TMAC_ICR1, 56 TMAC_CTCR0, 57 TMAC_TFCR0, 58 MDP_BNRCFR0, 59 MDP_BNRCFR1, 60 ARB_DRNGR0, 61 ARB_SCR, 62 RMAC_MIB_AIRTIME14, 63 AGG_AWSCR0, 64 AGG_PCR0, 65 AGG_ACR0, 66 AGG_ACR4, 67 AGG_MRCR, 68 AGG_ATCR1, 69 AGG_ATCR3, 70 LPON_UTTR0, 71 LPON_UTTR1, 72 LPON_FRCR, 73 MIB_SDR3, 74 MIB_SDR4, 75 MIB_SDR5, 76 MIB_SDR7, 77 MIB_SDR8, 78 MIB_SDR9, 79 MIB_SDR10, 80 MIB_SDR11, 81 MIB_SDR12, 82 MIB_SDR13, 83 MIB_SDR14, 84 MIB_SDR15, 85 MIB_SDR16, 86 MIB_SDR17, 87 MIB_SDR18, 88 MIB_SDR19, 89 MIB_SDR20, 90 MIB_SDR21, 91 MIB_SDR22, 92 MIB_SDR23, 93 MIB_SDR24, 94 MIB_SDR25, 95 MIB_SDR27, 96 MIB_SDR28, 97 MIB_SDR29, 98 MIB_SDRVEC, 99 MIB_SDR31, 100 MIB_SDR32, 101 MIB_SDRMUBF, 102 MIB_DR8, 103 MIB_DR9, 104 MIB_DR11, 105 MIB_MB_SDR0, 106 MIB_MB_SDR1, 107 TX_AGG_CNT, 108 TX_AGG_CNT2, 109 MIB_ARNG, 110 WTBLON_TOP_WDUCR, 111 WTBL_UPDATE, 112 PLE_FL_Q_EMPTY, 113 PLE_FL_Q_CTRL, 114 PLE_AC_QEMPTY, 115 PLE_FREEPG_CNT, 116 PLE_FREEPG_HEAD_TAIL, 117 PLE_PG_HIF_GROUP, 118 PLE_HIF_PG_INFO, 119 AC_OFFSET, 120 ETBF_PAR_RPT0, 121 __MT_OFFS_MAX, 122 }; 123 124 #define __REG(id) (dev->reg.reg_rev[(id)]) 125 #define __OFFS(id) (dev->reg.offs_rev[(id)]) 126 127 /* MCU WFDMA0 */ 128 #define MT_MCU_WFDMA0_BASE 0x2000 129 #define MT_MCU_WFDMA0(ofs) (MT_MCU_WFDMA0_BASE + (ofs)) 130 131 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120) 132 133 /* MCU WFDMA1 */ 134 #define MT_MCU_WFDMA1_BASE 0x3000 135 #define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs)) 136 137 #define MT_MCU_INT_EVENT __REG(INT_MCU_CMD_EVENT) 138 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0) 139 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1) 140 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2) 141 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3) 142 143 /* PLE */ 144 #define MT_PLE_BASE 0x820c0000 145 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs)) 146 147 #define MT_FL_Q_EMPTY MT_PLE(__OFFS(PLE_FL_Q_EMPTY)) 148 #define MT_FL_Q0_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL)) 149 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8) 150 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc) 151 152 #define MT_PLE_FREEPG_CNT MT_PLE(__OFFS(PLE_FREEPG_CNT)) 153 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(__OFFS(PLE_FREEPG_HEAD_TAIL)) 154 #define MT_PLE_PG_HIF_GROUP MT_PLE(__OFFS(PLE_PG_HIF_GROUP)) 155 #define MT_PLE_HIF_PG_INFO MT_PLE(__OFFS(PLE_HIF_PG_INFO)) 156 157 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(__OFFS(PLE_AC_QEMPTY) + \ 158 __OFFS(AC_OFFSET) * \ 159 (ac) + ((n) << 2)) 160 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2)) 161 162 #define MT_PSE_BASE 0x820c8000 163 #define MT_PSE(ofs) (MT_PSE_BASE + (ofs)) 164 165 /* WF MDP TOP */ 166 #define MT_MDP_BASE 0x820cd000 167 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs)) 168 169 #define MT_MDP_DCR0 MT_MDP(0x000) 170 #define MT_MDP_DCR0_DAMSDU_EN BIT(15) 171 172 #define MT_MDP_DCR1 MT_MDP(0x004) 173 #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3) 174 175 #define MT_MDP_DCR2 MT_MDP(0x0e8) 176 #define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2) 177 178 #define MT_MDP_BNRCFR0(_band) MT_MDP(__OFFS(MDP_BNRCFR0) + \ 179 ((_band) << 8)) 180 #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4) 181 #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6) 182 #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8) 183 184 #define MT_MDP_BNRCFR1(_band) MT_MDP(__OFFS(MDP_BNRCFR1) + \ 185 ((_band) << 8)) 186 #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22) 187 #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27) 188 #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29) 189 #define MT_MDP_TO_HIF 0 190 #define MT_MDP_TO_WM 1 191 192 /* TRB: band 0(0x820e1000), band 1(0x820f1000) */ 193 #define MT_WF_TRB_BASE(_band) ((_band) ? 0x820f1000 : 0x820e1000) 194 #define MT_WF_TRB(_band, ofs) (MT_WF_TRB_BASE(_band) + (ofs)) 195 196 #define MT_TRB_RXPSR0(_band) MT_WF_TRB(_band, 0x03c) 197 #define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16) 198 #define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0) 199 200 /* TMAC: band 0(0x820e4000), band 1(0x820f4000) */ 201 #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000) 202 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs)) 203 204 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0) 205 #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6) 206 #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25) 207 208 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR)) 209 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR)) 210 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 211 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 212 213 #define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ATCR)) 214 #define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0) 215 216 #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TRCR0)) 217 #define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0) 218 #define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16) 219 220 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR0)) 221 #define MT_IFS_EIFS_OFDM GENMASK(8, 0) 222 #define MT_IFS_RIFS GENMASK(14, 10) 223 #define MT_IFS_SIFS GENMASK(22, 16) 224 #define MT_IFS_SLOT GENMASK(30, 24) 225 226 #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR1)) 227 #define MT_IFS_EIFS_CCK GENMASK(8, 0) 228 229 #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CTCR0)) 230 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0) 231 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17) 232 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18) 233 234 #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TFCR0)) 235 236 /* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */ 237 #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000) 238 #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs)) 239 240 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000) 241 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3) 242 #define MT_DMA_DCR0_RXD_G5_EN BIT(23) 243 244 /* WTBLOFF TOP: band 0(0x820e9000),band 1(0x820f9000) */ 245 #define MT_WTBLOFF_TOP_BASE(_band) ((_band) ? 0x820f9000 : 0x820e9000) 246 #define MT_WTBLOFF_TOP(_band, ofs) (MT_WTBLOFF_TOP_BASE(_band) + (ofs)) 247 248 #define MT_WTBLOFF_TOP_RSCR(_band) MT_WTBLOFF_TOP(_band, 0x008) 249 #define MT_WTBLOFF_TOP_RSCR_RCPI_MODE GENMASK(31, 30) 250 #define MT_WTBLOFF_TOP_RSCR_RCPI_PARAM GENMASK(25, 24) 251 252 /* ETBF: band 0(0x820ea000), band 1(0x820fa000) */ 253 #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000) 254 #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs)) 255 256 #define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040) 257 #define MT_ETBF_TX_FB_CPL GENMASK(31, 16) 258 #define MT_ETBF_TX_FB_TRI GENMASK(15, 0) 259 260 #define MT_ETBF_PAR_RPT0(_band) MT_WF_ETBF(_band, __OFFS(ETBF_PAR_RPT0)) 261 #define MT_ETBF_PAR_RPT0_FB_BW GENMASK(7, 6) 262 #define MT_ETBF_PAR_RPT0_FB_NC GENMASK(5, 3) 263 #define MT_ETBF_PAR_RPT0_FB_NR GENMASK(2, 0) 264 265 #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0) 266 #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16) 267 #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0) 268 269 #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8) 270 #define MT_ETBF_RX_FB_ALL GENMASK(31, 24) 271 #define MT_ETBF_RX_FB_HE GENMASK(23, 16) 272 #define MT_ETBF_RX_FB_VHT GENMASK(15, 8) 273 #define MT_ETBF_RX_FB_HT GENMASK(7, 0) 274 275 /* LPON: band 0(0x820eb000), band 1(0x820fb000) */ 276 #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000) 277 #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs)) 278 279 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR0)) 280 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR1)) 281 #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, __OFFS(LPON_FRCR)) 282 283 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + \ 284 (((n) * 4) << 1)) 285 #define MT_LPON_TCR_MT7916(_band, n) MT_WF_LPON(_band, 0x0a8 + \ 286 (((n) * 4) << 4)) 287 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0) 288 #define MT_LPON_TCR_SW_WRITE BIT(0) 289 #define MT_LPON_TCR_SW_ADJUST BIT(1) 290 #define MT_LPON_TCR_SW_READ GENMASK(1, 0) 291 292 /* MIB: band 0(0x820ed000), band 1(0x820fd000) */ 293 /* These counters are (mostly?) clear-on-read. So, some should not 294 * be read at all in case firmware is already reading them. These 295 * are commented with 'DNR' below. The DNR stats will be read by querying 296 * the firmware API for the appropriate message. For counters the driver 297 * does read, the driver should accumulate the counters. 298 */ 299 #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000) 300 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs)) 301 302 #define MT_MIB_SDR0(_band) MT_WF_MIB(_band, 0x010) 303 #define MT_MIB_SDR0_BERACON_TX_CNT_MASK GENMASK(15, 0) 304 305 #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR3)) 306 #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0) 307 #define MT_MIB_SDR3_FCS_ERR_MASK_MT7916 GENMASK(31, 16) 308 309 #define MT_MIB_SDR4(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR4)) 310 #define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0) 311 312 /* rx mpdu counter, full 32 bits */ 313 #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR5)) 314 315 #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020) 316 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0) 317 318 #define MT_MIB_SDR7(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR7)) 319 #define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK GENMASK(15, 0) 320 321 #define MT_MIB_SDR8(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR8)) 322 #define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK GENMASK(15, 0) 323 324 /* aka CCA_NAV_TX_TIME */ 325 #define MT_MIB_SDR9_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR9)) 326 #define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0) 327 328 #define MT_MIB_SDR10(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR10)) 329 #define MT_MIB_SDR10_MRDY_COUNT_MASK GENMASK(25, 0) 330 #define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916 GENMASK(31, 0) 331 332 #define MT_MIB_SDR11(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR11)) 333 #define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK GENMASK(15, 0) 334 335 /* tx ampdu cnt, full 32 bits */ 336 #define MT_MIB_SDR12(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR12)) 337 338 #define MT_MIB_SDR13(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR13)) 339 #define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK GENMASK(15, 0) 340 341 /* counts all mpdus in ampdu, regardless of success */ 342 #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR14)) 343 #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK GENMASK(23, 0) 344 #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916 GENMASK(31, 0) 345 346 /* counts all successfully tx'd mpdus in ampdu */ 347 #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR15)) 348 #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK GENMASK(23, 0) 349 #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916 GENMASK(31, 0) 350 351 /* in units of 'us' */ 352 #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR16)) 353 #define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK GENMASK(23, 0) 354 355 #define MT_MIB_SDR17(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR17)) 356 #define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK GENMASK(23, 0) 357 358 #define MT_MIB_SDR18(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR18)) 359 #define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK GENMASK(23, 0) 360 361 /* units are us */ 362 #define MT_MIB_SDR19(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR19)) 363 #define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK GENMASK(23, 0) 364 365 #define MT_MIB_SDR20(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR20)) 366 #define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK GENMASK(23, 0) 367 368 #define MT_MIB_SDR21(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR21)) 369 #define MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK GENMASK(23, 0) 370 371 /* rx ampdu count, 32-bit */ 372 #define MT_MIB_SDR22(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR22)) 373 374 /* rx ampdu bytes count, 32-bit */ 375 #define MT_MIB_SDR23(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR23)) 376 377 /* rx ampdu valid subframe count */ 378 #define MT_MIB_SDR24(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR24)) 379 #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK GENMASK(23, 0) 380 #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916 GENMASK(31, 0) 381 382 /* rx ampdu valid subframe bytes count, 32bits */ 383 #define MT_MIB_SDR25(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR25)) 384 385 /* remaining windows protected stats */ 386 #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR27)) 387 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK GENMASK(15, 0) 388 389 #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR28)) 390 #define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK GENMASK(15, 0) 391 392 #define MT_MIB_SDR29(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR29)) 393 #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK GENMASK(7, 0) 394 #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916 GENMASK(15, 0) 395 396 #define MT_MIB_SDRVEC(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRVEC)) 397 #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK GENMASK(15, 0) 398 #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916 GENMASK(31, 16) 399 400 /* rx blockack count, 32 bits */ 401 #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR31)) 402 403 #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR32)) 404 #define MT_MIB_SDR32_TX_PKT_EBF_CNT GENMASK(15, 0) 405 #define MT_MIB_SDR32_TX_PKT_IBF_CNT GENMASK(31, 16) 406 407 #define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x088) 408 #define MT_MIB_SDR33_TX_PKT_IBF_CNT GENMASK(15, 0) 409 410 #define MT_MIB_SDRMUBF(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRMUBF)) 411 #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0) 412 413 /* 36, 37 both DNR */ 414 415 #define MT_MIB_DR8(_band) MT_WF_MIB(_band, __OFFS(MIB_DR8)) 416 #define MT_MIB_DR9(_band) MT_WF_MIB(_band, __OFFS(MIB_DR9)) 417 #define MT_MIB_DR11(_band) MT_WF_MIB(_band, __OFFS(MIB_DR11)) 418 419 #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR0) + (n)) 420 #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16) 421 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0) 422 423 #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR1) + (n)) 424 #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0) 425 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16) 426 427 #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x518 + (n)) 428 #define MT_MIB_MB_BFTF(_band, n) MT_WF_MIB(_band, 0x510 + (n)) 429 430 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT) + \ 431 ((n) << 2)) 432 #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT2) + \ 433 ((n) << 2)) 434 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, __OFFS(MIB_ARNG) + \ 435 ((n) << 2)) 436 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0)) 437 438 #define MT_MIB_BFCR0(_band) MT_WF_MIB(_band, 0x7b0) 439 #define MT_MIB_BFCR0_RX_FB_HT GENMASK(15, 0) 440 #define MT_MIB_BFCR0_RX_FB_VHT GENMASK(31, 16) 441 442 #define MT_MIB_BFCR1(_band) MT_WF_MIB(_band, 0x7b4) 443 #define MT_MIB_BFCR1_RX_FB_HE GENMASK(15, 0) 444 445 #define MT_MIB_BFCR2(_band) MT_WF_MIB(_band, 0x7b8) 446 #define MT_MIB_BFCR2_BFEE_TX_FB_TRIG GENMASK(15, 0) 447 448 #define MT_MIB_BFCR7(_band) MT_WF_MIB(_band, 0x7cc) 449 #define MT_MIB_BFCR7_BFEE_TX_FB_CPL GENMASK(15, 0) 450 451 /* WTBLON TOP */ 452 #define MT_WTBLON_TOP_BASE 0x820d4000 453 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs)) 454 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_TOP_WDUCR)) 455 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0) 456 457 #define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE)) 458 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0) 459 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) 460 #define MT_WTBL_UPDATE_BUSY BIT(31) 461 462 /* WTBL */ 463 #define MT_WTBL_BASE 0x820d8000 464 #define MT_WTBL_LMAC_ID GENMASK(14, 8) 465 #define MT_WTBL_LMAC_DW GENMASK(7, 2) 466 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \ 467 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \ 468 FIELD_PREP(MT_WTBL_LMAC_DW, _dw)) 469 470 /* AGG: band 0(0x820e2000), band 1(0x820f2000) */ 471 #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000) 472 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs)) 473 474 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) + \ 475 (_n) * 4)) 476 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_PCR0) + \ 477 (_n) * 4)) 478 #define MT_AGG_PCR0_MM_PROT BIT(0) 479 #define MT_AGG_PCR0_GF_PROT BIT(1) 480 #define MT_AGG_PCR0_BW20_PROT BIT(2) 481 #define MT_AGG_PCR0_BW40_PROT BIT(4) 482 #define MT_AGG_PCR0_BW80_PROT BIT(6) 483 #define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8) 484 #define MT_AGG_PCR0_VHT_PROT BIT(13) 485 #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15) 486 487 #define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23) 488 #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0) 489 490 #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR0)) 491 #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0) 492 #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16) 493 494 #define MT_AGG_ACR4(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR4)) 495 #define MT_AGG_ACR_PPDU_TXS2H BIT(1) 496 497 #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, __OFFS(AGG_MRCR)) 498 #define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12) 499 #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6) 500 #define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7) 501 #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24) 502 503 #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR1)) 504 #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR3)) 505 506 /* ARB: band 0(0x820e3000), band 1(0x820f3000) */ 507 #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000) 508 #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs)) 509 510 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, __OFFS(ARB_SCR)) 511 #define MT_ARB_SCR_TX_DISABLE BIT(8) 512 #define MT_ARB_SCR_RX_DISABLE BIT(9) 513 514 #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, (__OFFS(ARB_DRNGR0) + \ 515 (_n) * 4)) 516 517 /* RMAC: band 0(0x820e5000), band 1(0x820f5000) */ 518 #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000) 519 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs)) 520 521 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000) 522 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 523 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 524 #define MT_WF_RFCR_DROP_VERSION BIT(3) 525 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 526 #define MT_WF_RFCR_DROP_MCAST BIT(5) 527 #define MT_WF_RFCR_DROP_BCAST BIT(6) 528 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 529 #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 530 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 531 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 532 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 533 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 534 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 535 #define MT_WF_RFCR_DROP_CTS BIT(14) 536 #define MT_WF_RFCR_DROP_RTS BIT(15) 537 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 538 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 539 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 540 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 541 #define MT_WF_RFCR_DROP_NDPA BIT(20) 542 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 543 544 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004) 545 #define MT_WF_RFCR1_DROP_ACK BIT(4) 546 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5) 547 #define MT_WF_RFCR1_DROP_BA BIT(6) 548 #define MT_WF_RFCR1_DROP_CFEND BIT(7) 549 #define MT_WF_RFCR1_DROP_CFACK BIT(8) 550 551 #define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x02e0) 552 #define MT_WF_RMAC_RSVD0_EIFS_CLR BIT(21) 553 554 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380) 555 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31) 556 #define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0) 557 #define MT_WF_RMAC_MIB_ED_OFFSET GENMASK(20, 16) 558 559 #define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384) 560 #define MT_WF_RMAC_MIB_NONQOSD_BACKOFF GENMASK(31, 16) 561 562 #define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c) 563 #define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0) 564 565 #define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390) 566 #define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0) 567 568 /* WFDMA0 */ 569 #define MT_WFDMA0_BASE __REG(WFDMA0_ADDR) 570 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs)) 571 572 #define MT_WFDMA0_RST MT_WFDMA0(0x100) 573 #define MT_WFDMA0_RST_LOGIC_RST BIT(4) 574 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5) 575 576 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c) 577 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0) 578 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1) 579 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2) 580 581 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4) 582 583 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208) 584 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0) 585 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2) 586 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28) 587 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) 588 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 589 590 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c) 591 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0) 592 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4) 593 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8) 594 595 /* WFDMA1 */ 596 #define MT_WFDMA1_BASE 0xd5000 597 #define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs)) 598 599 #define MT_WFDMA1_RST MT_WFDMA1(0x100) 600 #define MT_WFDMA1_RST_LOGIC_RST BIT(4) 601 #define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5) 602 603 #define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c) 604 #define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0) 605 #define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1) 606 #define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2) 607 608 #define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208) 609 #define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0) 610 #define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2) 611 #define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28) 612 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27) 613 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) 614 615 #define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c) 616 #define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0) 617 618 /* WFDMA CSR */ 619 #define MT_WFDMA_EXT_CSR_BASE __REG(WFDMA_EXT_CSR_ADDR) 620 #define MT_WFDMA_EXT_CSR_PHYS_BASE 0x18027000 621 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs)) 622 #define MT_WFDMA_EXT_CSR_PHYS(ofs) (MT_WFDMA_EXT_CSR_PHYS_BASE + (ofs)) 623 624 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR_PHYS(0x30) 625 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) 626 #define MT_WFDMA_HOST_CONFIG_WED BIT(1) 627 628 #define MT_WFDMA_WED_RING_CONTROL MT_WFDMA_EXT_CSR_PHYS(0x34) 629 #define MT_WFDMA_WED_RING_CONTROL_TX0 GENMASK(4, 0) 630 #define MT_WFDMA_WED_RING_CONTROL_TX1 GENMASK(12, 8) 631 #define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16) 632 633 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR_PHYS(0x44) 634 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) 635 636 #define MT_PCIE_RECOG_ID 0xd7090 637 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) 638 #define MT_PCIE_RECOG_ID_SEM BIT(31) 639 640 #define MT_INT_WED_SOURCE_CSR MT_WFDMA_EXT_CSR(0x200) 641 #define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204) 642 643 #define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300) 644 #define MT_WED_RX_RING_BASE MT_WFDMA_EXT_CSR(0x400) 645 646 /* WFDMA0 PCIE1 */ 647 #define MT_WFDMA0_PCIE1_BASE __REG(WFDMA0_PCIE1_ADDR) 648 #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs)) 649 650 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c) 651 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 652 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 653 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 654 655 /* WFDMA1 PCIE1 */ 656 #define MT_WFDMA1_PCIE1_BASE 0xd9000 657 #define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA1_PCIE1_BASE + (ofs)) 658 659 #define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c) 660 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0) 661 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1) 662 #define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2) 663 664 /* WFDMA COMMON */ 665 #define __RXQ(q) ((q) + __MT_MCUQ_MAX) 666 #define __TXQ(q) (__RXQ(q) + MT_RXQ_BAND2) 667 668 #define MT_Q_ID(q) (dev->q_id[(q)]) 669 #define MT_Q_BASE(q) ((dev->wfdma_mask >> (q)) & 0x1 ? \ 670 MT_WFDMA1_BASE : MT_WFDMA0_BASE) 671 672 #define MT_MCUQ_ID(q) MT_Q_ID(q) 673 #define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q)) 674 #define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q)) 675 676 #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300) 677 #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300) 678 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500) 679 680 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \ 681 MT_MCUQ_ID(q)* 0x4) 682 #define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \ 683 MT_RXQ_ID(q)* 0x4) 684 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \ 685 MT_TXQ_ID(q)* 0x4) 686 687 #define MT_TXQ_WED_RING_BASE __REG(TXQ_WED_RING_BASE) 688 #define MT_RXQ_WED_RING_BASE __REG(RXQ_WED_RING_BASE) 689 690 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR) 691 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR) 692 693 #define MT_INT1_SOURCE_CSR __REG(INT1_SOURCE_CSR) 694 #define MT_INT1_MASK_CSR __REG(INT1_MASK_CSR) 695 696 #define MT_INT_RX_DONE_BAND0 BIT(16) 697 #define MT_INT_RX_DONE_BAND1 BIT(17) 698 #define MT_INT_RX_DONE_WM BIT(0) 699 #define MT_INT_RX_DONE_WA BIT(1) 700 #define MT_INT_RX_DONE_WA_MAIN BIT(1) 701 #define MT_INT_RX_DONE_WA_EXT BIT(2) 702 #define MT_INT_MCU_CMD BIT(29) 703 #define MT_INT_RX_DONE_BAND0_MT7916 BIT(22) 704 #define MT_INT_RX_DONE_BAND1_MT7916 BIT(23) 705 #define MT_INT_RX_DONE_WA_MAIN_MT7916 BIT(2) 706 #define MT_INT_RX_DONE_WA_EXT_MT7916 BIT(3) 707 708 #define MT_INT_WED_RX_DONE_BAND0_MT7916 BIT(18) 709 #define MT_INT_WED_RX_DONE_BAND1_MT7916 BIT(19) 710 #define MT_INT_WED_RX_DONE_WA_MAIN_MT7916 BIT(1) 711 #define MT_INT_WED_RX_DONE_WA_MT7916 BIT(17) 712 713 #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)]) 714 #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)]) 715 716 #define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \ 717 MT_INT_RX(MT_RXQ_MCU_WA)) 718 719 #define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \ 720 MT_INT_RX(MT_RXQ_MAIN_WA)) 721 722 #define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \ 723 MT_INT_RX(MT_RXQ_BAND1_WA) | \ 724 MT_INT_RX(MT_RXQ_MAIN_WA)) 725 726 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \ 727 MT_INT_BAND0_RX_DONE | \ 728 MT_INT_BAND1_RX_DONE) 729 730 #define MT_INT_TX_DONE_FWDL BIT(26) 731 #define MT_INT_TX_DONE_MCU_WM BIT(27) 732 #define MT_INT_TX_DONE_MCU_WA BIT(15) 733 #define MT_INT_TX_DONE_BAND0 BIT(30) 734 #define MT_INT_TX_DONE_BAND1 BIT(31) 735 #define MT_INT_TX_DONE_MCU_WA_MT7916 BIT(25) 736 #define MT_INT_WED_TX_DONE_BAND0 BIT(4) 737 #define MT_INT_WED_TX_DONE_BAND1 BIT(5) 738 739 #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \ 740 MT_INT_TX_MCU(MT_MCUQ_WM) | \ 741 MT_INT_TX_MCU(MT_MCUQ_FWDL)) 742 743 #define MT_MCU_CMD __REG(INT_MCU_CMD_SOURCE) 744 #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1) 745 #define MT_MCU_CMD_STOP_DMA BIT(2) 746 #define MT_MCU_CMD_RESET_DONE BIT(3) 747 #define MT_MCU_CMD_RECOVERY_DONE BIT(4) 748 #define MT_MCU_CMD_NORMAL_STATE BIT(5) 749 #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1) 750 751 #define MT_MCU_CMD_WA_WDT BIT(31) 752 #define MT_MCU_CMD_WM_WDT BIT(30) 753 #define MT_MCU_CMD_WDT_MASK GENMASK(31, 30) 754 755 /* TOP RGU */ 756 #define MT_TOP_RGU_BASE 0x18000000 757 #define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0)) 758 #define MT_TOP_PWR_KEY (0x5746 << 16) 759 #define MT_TOP_PWR_SW_RST BIT(0) 760 #define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2) 761 #define MT_TOP_PWR_HW_CTRL BIT(4) 762 #define MT_TOP_PWR_PWR_ON BIT(7) 763 764 #define MT_TOP_RGU_SYSRAM_PDN (MT_TOP_RGU_BASE + 0x050) 765 #define MT_TOP_RGU_SYSRAM_SLP (MT_TOP_RGU_BASE + 0x054) 766 #define MT_TOP_WFSYS_PWR (MT_TOP_RGU_BASE + 0x010) 767 #define MT_TOP_PWR_EN_MASK BIT(7) 768 #define MT_TOP_PWR_ACK_MASK BIT(6) 769 #define MT_TOP_PWR_KEY_MASK GENMASK(31, 16) 770 771 #define MT7986_TOP_WM_RESET (MT_TOP_RGU_BASE + 0x120) 772 #define MT7986_TOP_WM_RESET_MASK BIT(0) 773 774 /* l1/l2 remap */ 775 #define MT_HIF_REMAP_L1 0xf11ac 776 #define MT_HIF_REMAP_L1_MT7916 0xfe260 777 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0) 778 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0) 779 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16) 780 #define MT_HIF_REMAP_BASE_L1 0xe0000 781 782 #define MT_HIF_REMAP_L2 0xf11b0 783 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0) 784 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0) 785 #define MT_HIF_REMAP_L2_BASE GENMASK(31, 12) 786 #define MT_HIF_REMAP_L2_MT7916 0x1b8 787 #define MT_HIF_REMAP_L2_MASK_MT7916 GENMASK(31, 16) 788 #define MT_HIF_REMAP_L2_OFFSET_MT7916 GENMASK(15, 0) 789 #define MT_HIF_REMAP_L2_BASE_MT7916 GENMASK(31, 16) 790 #define MT_HIF_REMAP_BASE_L2_MT7916 0x40000 791 792 #define MT_INFRA_BASE 0x18000000 793 #define MT_WFSYS0_PHY_START 0x18400000 794 #define MT_WFSYS1_PHY_START 0x18800000 795 #define MT_WFSYS1_PHY_END 0x18bfffff 796 #define MT_CBTOP1_PHY_START 0x70000000 797 #define MT_CBTOP1_PHY_END __REG(CBTOP1_PHY_END) 798 #define MT_CBTOP2_PHY_START 0xf0000000 799 #define MT_CBTOP2_PHY_END 0xffffffff 800 #define MT_INFRA_MCU_START 0x7c000000 801 #define MT_INFRA_MCU_END __REG(INFRA_MCU_ADDR_END) 802 #define MT_CONN_INFRA_OFFSET(p) ((p) - MT_INFRA_BASE) 803 804 /* CONN INFRA CFG */ 805 #define MT_CONN_INFRA_BASE 0x18001000 806 #define MT_CONN_INFRA(ofs) (MT_CONN_INFRA_BASE + (ofs)) 807 808 #define MT_CONN_INFRA_EFUSE MT_CONN_INFRA(0x020) 809 810 #define MT_CONN_INFRA_ADIE_RESET MT_CONN_INFRA(0x030) 811 #define MT_CONN_INFRA_ADIE1_RESET_MASK BIT(0) 812 #define MT_CONN_INFRA_ADIE2_RESET_MASK BIT(2) 813 814 #define MT_CONN_INFRA_OSC_RC_EN MT_CONN_INFRA(0x380) 815 816 #define MT_CONN_INFRA_OSC_CTRL MT_CONN_INFRA(0x300) 817 #define MT_CONN_INFRA_OSC_RC_EN_MASK BIT(7) 818 #define MT_CONN_INFRA_OSC_STB_TIME_MASK GENMASK(23, 0) 819 820 #define MT_CONN_INFRA_HW_CTRL MT_CONN_INFRA(0x200) 821 #define MT_CONN_INFRA_HW_CTRL_MASK BIT(0) 822 823 #define MT_CONN_INFRA_WF_SLP_PROT MT_CONN_INFRA(0x540) 824 #define MT_CONN_INFRA_WF_SLP_PROT_MASK BIT(0) 825 826 #define MT_CONN_INFRA_WF_SLP_PROT_RDY MT_CONN_INFRA(0x544) 827 #define MT_CONN_INFRA_CONN_WF_MASK (BIT(29) | BIT(31)) 828 #define MT_CONN_INFRA_CONN (BIT(25) | BIT(29) | BIT(31)) 829 830 #define MT_CONN_INFRA_EMI_REQ MT_CONN_INFRA(0x414) 831 #define MT_CONN_INFRA_EMI_REQ_MASK BIT(0) 832 #define MT_CONN_INFRA_INFRA_REQ_MASK BIT(5) 833 834 /* AFE */ 835 #define MT_AFE_CTRL_BASE(_band) (0x18003000 + ((_band) << 19)) 836 #define MT_AFE_CTRL(_band, ofs) (MT_AFE_CTRL_BASE(_band) + (ofs)) 837 838 #define MT_AFE_DIG_EN_01(_band) MT_AFE_CTRL(_band, 0x00) 839 #define MT_AFE_DIG_EN_02(_band) MT_AFE_CTRL(_band, 0x04) 840 #define MT_AFE_DIG_EN_03(_band) MT_AFE_CTRL(_band, 0x08) 841 #define MT_AFE_DIG_TOP_01(_band) MT_AFE_CTRL(_band, 0x0c) 842 843 #define MT_AFE_PLL_STB_TIME(_band) MT_AFE_CTRL(_band, 0xf4) 844 #define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0)) 845 #define MT_AFE_PLL_STB_TIME_VAL (FIELD_PREP(GENMASK(30, 16), 0x4bc) | \ 846 FIELD_PREP(GENMASK(14, 0), 0x7e4)) 847 #define MT_AFE_BPLL_CFG_MASK GENMASK(7, 6) 848 #define MT_AFE_WPLL_CFG_MASK GENMASK(1, 0) 849 #define MT_AFE_MCU_WPLL_CFG_MASK GENMASK(3, 2) 850 #define MT_AFE_MCU_BPLL_CFG_MASK GENMASK(17, 16) 851 #define MT_AFE_PLL_CFG_MASK (MT_AFE_BPLL_CFG_MASK | \ 852 MT_AFE_WPLL_CFG_MASK | \ 853 MT_AFE_MCU_WPLL_CFG_MASK | \ 854 MT_AFE_MCU_BPLL_CFG_MASK) 855 #define MT_AFE_PLL_CFG_VAL (FIELD_PREP(MT_AFE_BPLL_CFG_MASK, 0x1) | \ 856 FIELD_PREP(MT_AFE_WPLL_CFG_MASK, 0x2) | \ 857 FIELD_PREP(MT_AFE_MCU_WPLL_CFG_MASK, 0x1) | \ 858 FIELD_PREP(MT_AFE_MCU_BPLL_CFG_MASK, 0x2)) 859 860 #define MT_AFE_DIG_TOP_01_MASK GENMASK(18, 15) 861 #define MT_AFE_DIG_TOP_01_VAL FIELD_PREP(MT_AFE_DIG_TOP_01_MASK, 0x9) 862 863 #define MT_AFE_RG_WBG_EN_RCK_MASK BIT(0) 864 #define MT_AFE_RG_WBG_EN_BPLL_UP_MASK BIT(21) 865 #define MT_AFE_RG_WBG_EN_WPLL_UP_MASK BIT(20) 866 #define MT_AFE_RG_WBG_EN_PLL_UP_MASK (MT_AFE_RG_WBG_EN_BPLL_UP_MASK | \ 867 MT_AFE_RG_WBG_EN_WPLL_UP_MASK) 868 #define MT_AFE_RG_WBG_EN_TXCAL_MASK GENMASK(21, 17) 869 870 #define MT_ADIE_SLP_CTRL_BASE(_band) (0x18005000 + ((_band) << 19)) 871 #define MT_ADIE_SLP_CTRL(_band, ofs) (MT_ADIE_SLP_CTRL_BASE(_band) + (ofs)) 872 873 #define MT_ADIE_SLP_CTRL_CK0(_band) MT_ADIE_SLP_CTRL(_band, 0x120) 874 875 /* ADIE */ 876 #define MT_ADIE_CHIP_ID 0x02c 877 #define MT_ADIE_VERSION_MASK GENMASK(15, 0) 878 #define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16) 879 #define MT_ADIE_IDX0 GENMASK(15, 0) 880 #define MT_ADIE_IDX1 GENMASK(31, 16) 881 882 #define MT_ADIE_RG_TOP_THADC_BG 0x034 883 #define MT_ADIE_VRPI_SEL_CR_MASK GENMASK(15, 12) 884 #define MT_ADIE_VRPI_SEL_EFUSE_MASK GENMASK(6, 3) 885 886 #define MT_ADIE_RG_TOP_THADC 0x038 887 #define MT_ADIE_PGA_GAIN_MASK GENMASK(25, 23) 888 #define MT_ADIE_PGA_GAIN_EFUSE_MASK GENMASK(2, 0) 889 #define MT_ADIE_LDO_CTRL_MASK GENMASK(27, 26) 890 #define MT_ADIE_LDO_CTRL_EFUSE_MASK GENMASK(6, 5) 891 892 #define MT_AFE_RG_ENCAL_WBTAC_IF_SW 0x070 893 #define MT_ADIE_EFUSE_RDATA0 0x130 894 895 #define MT_ADIE_EFUSE2_CTRL 0x148 896 #define MT_ADIE_EFUSE_CTRL_MASK BIT(1) 897 898 #define MT_ADIE_EFUSE_CFG 0x144 899 #define MT_ADIE_EFUSE_MODE_MASK GENMASK(7, 6) 900 #define MT_ADIE_EFUSE_ADDR_MASK GENMASK(25, 16) 901 #define MT_ADIE_EFUSE_VALID_MASK BIT(29) 902 #define MT_ADIE_EFUSE_KICK_MASK BIT(30) 903 904 #define MT_ADIE_THADC_ANALOG 0x3a6 905 906 #define MT_ADIE_THADC_SLOP 0x3a7 907 #define MT_ADIE_ANA_EN_MASK BIT(7) 908 909 #define MT_ADIE_7975_XTAL_CAL 0x3a1 910 #define MT_ADIE_TRIM_MASK GENMASK(6, 0) 911 #define MT_ADIE_EFUSE_TRIM_MASK GENMASK(5, 0) 912 #define MT_ADIE_XO_TRIM_EN_MASK BIT(7) 913 #define MT_ADIE_XTAL_DECREASE_MASK BIT(6) 914 915 #define MT_ADIE_7975_XO_TRIM2 0x3a2 916 #define MT_ADIE_7975_XO_TRIM3 0x3a3 917 #define MT_ADIE_7975_XO_TRIM4 0x3a4 918 #define MT_ADIE_7975_XTAL_EN 0x3a5 919 920 #define MT_ADIE_XO_TRIM_FLOW 0x3ac 921 #define MT_ADIE_XTAL_AXM_80M_OSC 0x390 922 #define MT_ADIE_XTAL_AXM_40M_OSC 0x391 923 #define MT_ADIE_XTAL_TRIM1_80M_OSC 0x398 924 #define MT_ADIE_XTAL_TRIM1_40M_OSC 0x399 925 #define MT_ADIE_WRI_CK_SEL 0x4ac 926 #define MT_ADIE_RG_STRAP_PIN_IN 0x4fc 927 #define MT_ADIE_XTAL_C1 0x654 928 #define MT_ADIE_XTAL_C2 0x658 929 #define MT_ADIE_RG_XO_01 0x65c 930 #define MT_ADIE_RG_XO_03 0x664 931 932 #define MT_ADIE_CLK_EN 0xa00 933 934 #define MT_ADIE_7975_XTAL 0xa18 935 #define MT_ADIE_7975_XTAL_EN_MASK BIT(29) 936 937 #define MT_ADIE_7975_COCLK 0xa1c 938 #define MT_ADIE_7975_XO_2 0xa84 939 #define MT_ADIE_7975_XO_2_FIX_EN BIT(31) 940 941 #define MT_ADIE_7975_XO_CTRL2 0xa94 942 #define MT_ADIE_7975_XO_CTRL2_C1_MASK GENMASK(26, 20) 943 #define MT_ADIE_7975_XO_CTRL2_C2_MASK GENMASK(18, 12) 944 #define MT_ADIE_7975_XO_CTRL2_MASK (MT_ADIE_7975_XO_CTRL2_C1_MASK | \ 945 MT_ADIE_7975_XO_CTRL2_C2_MASK) 946 947 #define MT_ADIE_7975_XO_CTRL6 0xaa4 948 #define MT_ADIE_7975_XO_CTRL6_MASK BIT(16) 949 950 /* TOP SPI */ 951 #define MT_TOP_SPI_ADIE_BASE(_band) (0x18004000 + ((_band) << 19)) 952 #define MT_TOP_SPI_ADIE(_band, ofs) (MT_TOP_SPI_ADIE_BASE(_band) + (ofs)) 953 954 #define MT_TOP_SPI_BUSY_CR(_band) MT_TOP_SPI_ADIE(_band, 0) 955 #define MT_TOP_SPI_POLLING_BIT BIT(5) 956 957 #define MT_TOP_SPI_ADDR_CR(_band) MT_TOP_SPI_ADIE(_band, 0x50) 958 #define MT_TOP_SPI_READ_ADDR_FORMAT (BIT(12) | BIT(13) | BIT(15)) 959 #define MT_TOP_SPI_WRITE_ADDR_FORMAT (BIT(13) | BIT(15)) 960 961 #define MT_TOP_SPI_WRITE_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x54) 962 #define MT_TOP_SPI_READ_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x58) 963 964 /* CONN INFRA CKGEN */ 965 #define MT_INFRA_CKGEN_BASE 0x18009000 966 #define MT_INFRA_CKGEN(ofs) (MT_INFRA_CKGEN_BASE + (ofs)) 967 968 #define MT_INFRA_CKGEN_BUS MT_INFRA_CKGEN(0xa00) 969 #define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK BIT(23) 970 #define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK BIT(29) 971 972 #define MT_INFRA_CKGEN_BUS_WPLL_DIV_1 MT_INFRA_CKGEN(0x008) 973 #define MT_INFRA_CKGEN_BUS_WPLL_DIV_2 MT_INFRA_CKGEN(0x00c) 974 975 #define MT_INFRA_CKGEN_RFSPI_WPLL_DIV MT_INFRA_CKGEN(0x040) 976 #define MT_INFRA_CKGEN_DIV_SEL_MASK GENMASK(7, 2) 977 #define MT_INFRA_CKGEN_DIV_EN_MASK BIT(0) 978 979 /* CONN INFRA BUS */ 980 #define MT_INFRA_BUS_BASE 0x1800e000 981 #define MT_INFRA_BUS(ofs) (MT_INFRA_BUS_BASE + (ofs)) 982 983 #define MT_INFRA_BUS_OFF_TIMEOUT MT_INFRA_BUS(0x300) 984 #define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK GENMASK(14, 7) 985 #define MT_INFRA_BUS_TIMEOUT_EN_MASK GENMASK(3, 0) 986 987 #define MT_INFRA_BUS_ON_TIMEOUT MT_INFRA_BUS(0x31c) 988 #define MT_INFRA_BUS_EMI_START MT_INFRA_BUS(0x360) 989 #define MT_INFRA_BUS_EMI_END MT_INFRA_BUS(0x364) 990 991 /* CONN_INFRA_SKU */ 992 #define MT_CONNINFRA_SKU_DEC_ADDR 0x18050000 993 #define MT_CONNINFRA_SKU_MASK GENMASK(15, 0) 994 #define MT_ADIE_TYPE_MASK BIT(1) 995 996 /* FW MODE SYNC */ 997 #define MT_FW_ASSERT_STAT __REG(FW_ASSERT_STAT_ADDR) 998 #define MT_FW_EXCEPT_TYPE __REG(FW_EXCEPT_TYPE_ADDR) 999 #define MT_FW_EXCEPT_COUNT __REG(FW_EXCEPT_COUNT_ADDR) 1000 #define MT_FW_CIRQ_COUNT __REG(FW_CIRQ_COUNT_ADDR) 1001 #define MT_FW_CIRQ_IDX __REG(FW_CIRQ_IDX_ADDR) 1002 #define MT_FW_CIRQ_LISR __REG(FW_CIRQ_LISR_ADDR) 1003 #define MT_FW_TASK_ID __REG(FW_TASK_ID_ADDR) 1004 #define MT_FW_TASK_IDX __REG(FW_TASK_IDX_ADDR) 1005 #define MT_FW_TASK_QID1 __REG(FW_TASK_QID1_ADDR) 1006 #define MT_FW_TASK_QID2 __REG(FW_TASK_QID2_ADDR) 1007 #define MT_FW_TASK_START __REG(FW_TASK_START_ADDR) 1008 #define MT_FW_TASK_END __REG(FW_TASK_END_ADDR) 1009 #define MT_FW_TASK_SIZE __REG(FW_TASK_SIZE_ADDR) 1010 #define MT_FW_LAST_MSG_ID __REG(FW_LAST_MSG_ID_ADDR) 1011 #define MT_FW_EINT_INFO __REG(FW_EINT_INFO_ADDR) 1012 #define MT_FW_SCHED_INFO __REG(FW_SCHED_INFO_ADDR) 1013 1014 #define MT_SWDEF_BASE __REG(SWDEF_BASE_ADDR) 1015 1016 #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs)) 1017 #define MT_SWDEF_MODE MT_SWDEF(0x3c) 1018 #define MT_SWDEF_NORMAL_MODE 0 1019 #define MT_SWDEF_ICAP_MODE 1 1020 #define MT_SWDEF_SPECTRUM_MODE 2 1021 1022 #define MT_SWDEF_SER_STATS MT_SWDEF(0x040) 1023 #define MT_SWDEF_PLE_STATS MT_SWDEF(0x044) 1024 #define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048) 1025 #define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04C) 1026 #define MT_SWDEF_PSE_STATS MT_SWDEF(0x050) 1027 #define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054) 1028 #define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058) 1029 #define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05C) 1030 #define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x060) 1031 #define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x064) 1032 1033 #define MT_DIC_CMD_REG_BASE 0x41f000 1034 #define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs)) 1035 #define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10) 1036 1037 #define MT_CPU_UTIL_BASE 0x41f030 1038 #define MT_CPU_UTIL(ofs) (MT_CPU_UTIL_BASE + (ofs)) 1039 #define MT_CPU_UTIL_BUSY_PCT MT_CPU_UTIL(0x00) 1040 #define MT_CPU_UTIL_PEAK_BUSY_PCT MT_CPU_UTIL(0x04) 1041 #define MT_CPU_UTIL_IDLE_CNT MT_CPU_UTIL(0x08) 1042 #define MT_CPU_UTIL_PEAK_IDLE_CNT MT_CPU_UTIL(0x0c) 1043 #define MT_CPU_UTIL_CTRL MT_CPU_UTIL(0x1c) 1044 1045 /* LED */ 1046 #define MT_LED_TOP_BASE 0x18013000 1047 #define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n)) 1048 1049 #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4)) 1050 #define MT_LED_CTRL_KICK BIT(7) 1051 #define MT_LED_CTRL_BLINK_MODE BIT(2) 1052 #define MT_LED_CTRL_POLARITY BIT(1) 1053 1054 #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4)) 1055 #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0) 1056 #define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8) 1057 1058 #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4)) 1059 1060 #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */ 1061 #define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */ 1062 #define MT_LED_GPIO_SEL_MASK GENMASK(11, 8) 1063 1064 /* MT TOP */ 1065 #define MT_TOP_BASE 0x18060000 1066 #define MT_TOP(ofs) (MT_TOP_BASE + (ofs)) 1067 1068 #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10)) 1069 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0) 1070 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1) 1071 #define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2) 1072 1073 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10)) 1074 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0) 1075 1076 #define MT_TOP_MISC MT_TOP(0xf0) 1077 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0) 1078 1079 #define MT_TOP_WFSYS_WAKEUP MT_TOP(0x1a4) 1080 #define MT_TOP_WFSYS_WAKEUP_MASK BIT(0) 1081 1082 #define MT_TOP_MCU_EMI_BASE MT_TOP(0x1c4) 1083 #define MT_TOP_MCU_EMI_BASE_MASK GENMASK(19, 0) 1084 1085 #define MT_TOP_CONN_INFRA_WAKEUP MT_TOP(0x1a0) 1086 #define MT_TOP_CONN_INFRA_WAKEUP_MASK BIT(0) 1087 1088 #define MT_TOP_WFSYS_RESET_STATUS MT_TOP(0x2cc) 1089 #define MT_TOP_WFSYS_RESET_STATUS_MASK BIT(30) 1090 1091 /* SEMA */ 1092 #define MT_SEMA_BASE 0x18070000 1093 #define MT_SEMA(ofs) (MT_SEMA_BASE + (ofs)) 1094 1095 #define MT_SEMA_RFSPI_STATUS (MT_SEMA(0x2000) + (11 * 4)) 1096 #define MT_SEMA_RFSPI_RELEASE (MT_SEMA(0x2200) + (11 * 4)) 1097 #define MT_SEMA_RFSPI_STATUS_MASK BIT(1) 1098 1099 /* MCU BUS */ 1100 #define MT_MCU_BUS_BASE 0x18400000 1101 #define MT_MCU_BUS(ofs) (MT_MCU_BUS_BASE + (ofs)) 1102 1103 #define MT_MCU_BUS_TIMEOUT MT_MCU_BUS(0xf0440) 1104 #define MT_MCU_BUS_TIMEOUT_SET_MASK GENMASK(7, 0) 1105 #define MT_MCU_BUS_TIMEOUT_CG_EN_MASK BIT(28) 1106 #define MT_MCU_BUS_TIMEOUT_EN_MASK BIT(31) 1107 1108 #define MT_MCU_BUS_REMAP MT_MCU_BUS(0x120) 1109 1110 /* TOP CFG */ 1111 #define MT_TOP_CFG_BASE 0x184b0000 1112 #define MT_TOP_CFG(ofs) (MT_TOP_CFG_BASE + (ofs)) 1113 1114 #define MT_TOP_CFG_IP_VERSION_ADDR MT_TOP_CFG(0x010) 1115 1116 /* TOP CFG ON */ 1117 #define MT_TOP_CFG_ON_BASE 0x184c1000 1118 #define MT_TOP_CFG_ON(ofs) (MT_TOP_CFG_ON_BASE + (ofs)) 1119 1120 #define MT_TOP_CFG_ON_ROM_IDX MT_TOP_CFG_ON(0x604) 1121 1122 /* SLP CTRL */ 1123 #define MT_SLP_BASE 0x184c3000 1124 #define MT_SLP(ofs) (MT_SLP_BASE + (ofs)) 1125 1126 #define MT_SLP_STATUS MT_SLP(0x00c) 1127 #define MT_SLP_WFDMA2CONN_MASK (BIT(21) | BIT(23)) 1128 #define MT_SLP_CTRL_EN_MASK BIT(0) 1129 #define MT_SLP_CTRL_BSY_MASK BIT(1) 1130 1131 /* MCU BUS DBG */ 1132 #define MT_MCU_BUS_DBG_BASE 0x18500000 1133 #define MT_MCU_BUS_DBG(ofs) (MT_MCU_BUS_DBG_BASE + (ofs)) 1134 1135 #define MT_MCU_BUS_DBG_TIMEOUT MT_MCU_BUS_DBG(0x0) 1136 #define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16) 1137 #define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3) 1138 #define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK BIT(2) 1139 1140 #define MT_HW_BOUND 0x70010020 1141 #define MT_HW_REV 0x70010204 1142 #define MT_WF_SUBSYS_RST 0x70002600 1143 1144 /* PCIE MAC */ 1145 #define MT_PCIE_MAC_BASE 0x74030000 1146 #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs)) 1147 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188) 1148 1149 #define MT_PCIE1_MAC_INT_ENABLE 0x74020188 1150 #define MT_PCIE1_MAC_INT_ENABLE_MT7916 0x74090188 1151 1152 #define MT_WM_MCU_PC 0x7c060204 1153 #define MT_WA_MCU_PC 0x7c06020c 1154 1155 /* PP TOP */ 1156 #define MT_WF_PP_TOP_BASE 0x820cc000 1157 #define MT_WF_PP_TOP(ofs) (MT_WF_PP_TOP_BASE + (ofs)) 1158 1159 #define MT_WF_PP_TOP_RXQ_WFDMA_CF_5 MT_WF_PP_TOP(0x0e8) 1160 #define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK BIT(6) 1161 1162 #define MT_WF_IRPI_BASE 0x83000000 1163 #define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + (ofs)) 1164 1165 #define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16)) 1166 #define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16)) 1167 1168 /* PHY */ 1169 #define MT_WF_PHY_BASE 0x83080000 1170 #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs)) 1171 1172 #define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16)) 1173 #define MT_WF_PHY_RX_CTRL1_MT7916(_phy) MT_WF_PHY(0x2004 + ((_phy) << 20)) 1174 #define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0) 1175 #define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9) 1176 1177 #define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16)) 1178 #define MT_WF_PHY_RXTD12_MT7916(_phy) MT_WF_PHY(0x8230 + ((_phy) << 20)) 1179 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18) 1180 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29) 1181 1182 #define MT_MCU_WM_CIRQ_BASE 0x89010000 1183 #define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs)) 1184 #define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80) 1185 #define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR MT_MCU_WM_CIRQ(0xc0) 1186 #define MT_MCU_WM_CIRQ_EINT_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x108) 1187 #define MT_MCU_WM_CIRQ_EINT_SOFT_ADDR MT_MCU_WM_CIRQ(0x118) 1188 1189 #endif 1190