reg.h (eeb8832b3181d6ca8593051b68c466e5d2653bb3) reg.h (a0b907ee2a71052fefdf6151764095f3f97b3275)
1/*
2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.

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2557#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
2558#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
2559
2560/*
2561 * PHY PDADC Tx power table
2562 */
2563#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
2564#define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
1/*
2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.

--- 2548 unchanged lines hidden (view full) ---

2557#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000
2558#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22
2559
2560/*
2561 * PHY PDADC Tx power table
2562 */
2563#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280
2564#define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
2565
2566/*
2567 * Platform registers for WiSoC
2568 */
2569#define AR5K_AR5312_RESET 0xbc003020
2570#define AR5K_AR5312_RESET_BB0_COLD 0x00000004
2571#define AR5K_AR5312_RESET_BB1_COLD 0x00000200
2572#define AR5K_AR5312_RESET_WMAC0 0x00002000
2573#define AR5K_AR5312_RESET_BB0_WARM 0x00004000
2574#define AR5K_AR5312_RESET_WMAC1 0x00020000
2575#define AR5K_AR5312_RESET_BB1_WARM 0x00040000
2576
2577#define AR5K_AR5312_ENABLE 0xbc003080
2578#define AR5K_AR5312_ENABLE_WLAN0 0x00000001
2579#define AR5K_AR5312_ENABLE_WLAN1 0x00000008
2580
2581#define AR5K_AR2315_RESET 0xb1000004
2582#define AR5K_AR2315_RESET_WMAC 0x00000001
2583#define AR5K_AR2315_RESET_BB_WARM 0x00000002
2584
2585#define AR5K_AR2315_AHB_ARB_CTL 0xb1000008
2586#define AR5K_AR2315_AHB_ARB_CTL_WLAN 0x00000002
2587
2588#define AR5K_AR2315_BYTESWAP 0xb100000c
2589#define AR5K_AR2315_BYTESWAP_WMAC 0x00000002