1 /* 2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 */ 19 20 /* 21 * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k 22 * maintained by Reyk Floeter 23 * 24 * I tried to document those registers by looking at ar5k code, some 25 * 802.11 (802.11e mostly) papers and by reading various public available 26 * Atheros presentations and papers like these: 27 * 28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf 29 * 30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf 31 * 32 * This file also contains register values found on a memory dump of 33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal 34 * released by Atheros and on various debug messages found on the net. 35 */ 36 37 #include "../reg.h" 38 39 /*====MAC DMA REGISTERS====*/ 40 41 /* 42 * AR5210-Specific TXDP registers 43 * 5210 has only 2 transmit queues so no DCU/QCU, just 44 * 2 transmit descriptor pointers... 45 */ 46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */ 47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */ 48 49 /* 50 * Mac Control Register 51 */ 52 #define AR5K_CR 0x0008 /* Register Address */ 53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */ 54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */ 55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */ 56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ 57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ 58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */ 59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */ 60 61 /* 62 * RX Descriptor Pointer register 63 */ 64 #define AR5K_RXDP 0x000c 65 66 /* 67 * Configuration and status register 68 */ 69 #define AR5K_CFG 0x0014 /* Register Address */ 70 #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ 71 #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */ 72 #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ 73 #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */ 74 #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */ 75 #define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */ 76 #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ 77 #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ 78 #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */ 79 #define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ 80 #define AR5K_CFG_TXCNT_S 11 81 #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ 82 #define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ 83 #define AR5K_CFG_PCI_THRES 0x00060000 /* PCI Master req q threshold [5211+] */ 84 #define AR5K_CFG_PCI_THRES_S 17 85 86 /* 87 * Interrupt enable register 88 */ 89 #define AR5K_IER 0x0024 /* Register Address */ 90 #define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */ 91 #define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */ 92 93 94 /* 95 * 0x0028 is Beacon Control Register on 5210 96 * and first RTS duration register on 5211 97 */ 98 99 /* 100 * Beacon control register [5210] 101 */ 102 #define AR5K_BCR 0x0028 /* Register Address */ 103 #define AR5K_BCR_AP 0x00000000 /* AP mode */ 104 #define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */ 105 #define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */ 106 #define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */ 107 #define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */ 108 #define AR5K_BCR_BCGET 0x00000010 109 110 /* 111 * First RTS duration register [5211] 112 */ 113 #define AR5K_RTSD0 0x0028 /* Register Address */ 114 #define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */ 115 #define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */ 116 #define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/ 117 #define AR5K_RTSD0_9_S 8 118 #define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/ 119 #define AR5K_RTSD0_12_S 16 120 #define AR5K_RTSD0_18 0xff000000 /* 16Mb*/ 121 #define AR5K_RTSD0_18_S 24 122 123 124 /* 125 * 0x002c is Beacon Status Register on 5210 126 * and second RTS duration register on 5211 127 */ 128 129 /* 130 * Beacon status register [5210] 131 * 132 * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR 133 * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning 134 * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). 135 * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i 136 * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what 137 * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. 138 */ 139 #define AR5K_BSR 0x002c /* Register Address */ 140 #define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */ 141 #define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */ 142 #define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */ 143 #define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */ 144 #define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */ 145 #define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */ 146 #define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */ 147 #define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */ 148 #define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */ 149 #define AR5K_BSR_SWBA_CNT 0x00ff0000 150 151 /* 152 * Second RTS duration register [5211] 153 */ 154 #define AR5K_RTSD1 0x002c /* Register Address */ 155 #define AR5K_RTSD1_24 0x000000ff /* 24Mb */ 156 #define AR5K_RTSD1_24_S 0 157 #define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */ 158 #define AR5K_RTSD1_36_S 8 159 #define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */ 160 #define AR5K_RTSD1_48_S 16 161 #define AR5K_RTSD1_54 0xff000000 /* 54Mb */ 162 #define AR5K_RTSD1_54_S 24 163 164 165 /* 166 * Transmit configuration register 167 */ 168 #define AR5K_TXCFG 0x0030 /* Register Address */ 169 #define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size (read) */ 170 #define AR5K_TXCFG_SDMAMR_S 0 171 #define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ 172 #define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ 173 #define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ 174 #define AR5K_TXCFG_TXFULL_S 4 175 #define AR5K_TXCFG_TXFULL_0B 0x00000000 176 #define AR5K_TXCFG_TXFULL_64B 0x00000010 177 #define AR5K_TXCFG_TXFULL_128B 0x00000020 178 #define AR5K_TXCFG_TXFULL_192B 0x00000030 179 #define AR5K_TXCFG_TXFULL_256B 0x00000040 180 #define AR5K_TXCFG_TXCONT_EN 0x00000080 181 #define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ 182 #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */ 183 #define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 /* Adhoc Beacon ATIM Policy */ 184 #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 /* Disable ATIM window defer [5211+] */ 185 #define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ 186 #define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ 187 #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */ 188 #define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */ 189 #define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */ 190 #define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */ 191 192 /* 193 * Receive configuration register 194 */ 195 #define AR5K_RXCFG 0x0034 /* Register Address */ 196 #define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size (write) */ 197 #define AR5K_RXCFG_SDMAMW_S 0 198 #define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */ 199 #define AR5K_RXCFG_DEF_ANTENNA 0x00000010 /* Default antenna (?) */ 200 #define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */ 201 #define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames [5211+] */ 202 #define AR5K_RXCFG_SLE_ENTRY 0x00000080 /* Sleep entry policy */ 203 204 /* 205 * Receive jumbo descriptor last address register 206 * Only found in 5211 (?) 207 */ 208 #define AR5K_RXJLA 0x0038 209 210 /* 211 * MIB control register 212 */ 213 #define AR5K_MIBC 0x0040 /* Register Address */ 214 #define AR5K_MIBC_COW 0x00000001 /* Counter Overflow Warning */ 215 #define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */ 216 #define AR5K_MIBC_CMC 0x00000004 /* Clear MIB Counters */ 217 #define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */ 218 219 /* 220 * Timeout prescale register 221 */ 222 #define AR5K_TOPS 0x0044 223 #define AR5K_TOPS_M 0x0000ffff 224 225 /* 226 * Receive timeout register (no frame received) 227 */ 228 #define AR5K_RXNOFRM 0x0048 229 #define AR5K_RXNOFRM_M 0x000003ff 230 231 /* 232 * Transmit timeout register (no frame sent) 233 */ 234 #define AR5K_TXNOFRM 0x004c 235 #define AR5K_TXNOFRM_M 0x000003ff 236 #define AR5K_TXNOFRM_QCU 0x000ffc00 237 #define AR5K_TXNOFRM_QCU_S 10 238 239 /* 240 * Receive frame gap timeout register 241 */ 242 #define AR5K_RPGTO 0x0050 243 #define AR5K_RPGTO_M 0x000003ff 244 245 /* 246 * Receive frame count limit register 247 */ 248 #define AR5K_RFCNT 0x0054 249 #define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */ 250 #define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */ 251 252 /* 253 * Misc settings register 254 * (reserved0-3) 255 */ 256 #define AR5K_MISC 0x0058 /* Register Address */ 257 #define AR5K_MISC_DMA_OBS_M 0x000001e0 258 #define AR5K_MISC_DMA_OBS_S 5 259 #define AR5K_MISC_MISC_OBS_M 0x00000e00 260 #define AR5K_MISC_MISC_OBS_S 9 261 #define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 262 #define AR5K_MISC_MAC_OBS_LSB_S 12 263 #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 264 #define AR5K_MISC_MAC_OBS_MSB_S 15 265 #define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */ 266 #define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */ 267 268 /* 269 * QCU/DCU clock gating register (5311) 270 * (reserved4-5) 271 */ 272 #define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ 273 #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ 274 #define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */ 275 276 /* 277 * Interrupt Status Registers 278 * 279 * For 5210 there is only one status register but for 280 * 5211/5212 we have one primary and 4 secondary registers. 281 * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. 282 * Most of these bits are common for all chipsets. 283 */ 284 #define AR5K_ISR 0x001c /* Register Address [5210] */ 285 #define AR5K_PISR 0x0080 /* Register Address [5211+] */ 286 #define AR5K_ISR_RXOK 0x00000001 /* Frame successfuly recieved */ 287 #define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */ 288 #define AR5K_ISR_RXERR 0x00000004 /* Receive error */ 289 #define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */ 290 #define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */ 291 #define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */ 292 #define AR5K_ISR_TXOK 0x00000040 /* Frame successfuly transmited */ 293 #define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ 294 #define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ 295 #define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout) */ 296 #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ 297 #define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ 298 #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ 299 #define AR5K_ISR_SWI 0x00002000 /* Software interrupt */ 300 #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ 301 #define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */ 302 #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ 303 #define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ 304 #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ 305 #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 306 #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ 307 #define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ 308 #define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ 309 #define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ 310 #define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */ 311 #define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ 312 #define AR5K_ISR_TIM 0x00800000 /* [5211+] */ 313 #define AR5K_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, 314 CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ 315 #define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */ 316 #define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */ 317 #define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */ 318 #define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ 319 320 /* 321 * Secondary status registers [5211+] (0 - 4) 322 * 323 * These give the status for each QCU, only QCUs 0-9 are 324 * represented. 325 */ 326 #define AR5K_SISR0 0x0084 /* Register Address [5211+] */ 327 #define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ 328 #define AR5K_SISR0_QCU_TXOK_S 0 329 #define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ 330 #define AR5K_SISR0_QCU_TXDESC_S 16 331 332 #define AR5K_SISR1 0x0088 /* Register Address [5211+] */ 333 #define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ 334 #define AR5K_SISR1_QCU_TXERR_S 0 335 #define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ 336 #define AR5K_SISR1_QCU_TXEOL_S 16 337 338 #define AR5K_SISR2 0x008c /* Register Address [5211+] */ 339 #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ 340 #define AR5K_SISR2_QCU_TXURN_S 0 341 #define AR5K_SISR2_MCABT 0x00010000 /* Master Cycle Abort */ 342 #define AR5K_SISR2_SSERR 0x00020000 /* Signaled System Error */ 343 #define AR5K_SISR2_DPERR 0x00040000 /* Bus parity error */ 344 #define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ 345 #define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ 346 #define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */ 347 #define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ 348 #define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ 349 #define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ 350 #define AR5K_SISR2_TSFOOR 0x80000000 /* TSF OOR (?) */ 351 352 #define AR5K_SISR3 0x0090 /* Register Address [5211+] */ 353 #define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ 354 #define AR5K_SISR3_QCBRORN_S 0 355 #define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ 356 #define AR5K_SISR3_QCBRURN_S 16 357 358 #define AR5K_SISR4 0x0094 /* Register Address [5211+] */ 359 #define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */ 360 #define AR5K_SISR4_QTRIG_S 0 361 362 /* 363 * Shadow read-and-clear interrupt status registers [5211+] 364 */ 365 #define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */ 366 #define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */ 367 #define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */ 368 #define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */ 369 #define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */ 370 #define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */ 371 372 /* 373 * Interrupt Mask Registers 374 * 375 * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary 376 * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match. 377 */ 378 #define AR5K_IMR 0x0020 /* Register Address [5210] */ 379 #define AR5K_PIMR 0x00a0 /* Register Address [5211+] */ 380 #define AR5K_IMR_RXOK 0x00000001 /* Frame successfuly recieved*/ 381 #define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/ 382 #define AR5K_IMR_RXERR 0x00000004 /* Receive error*/ 383 #define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/ 384 #define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/ 385 #define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/ 386 #define AR5K_IMR_TXOK 0x00000040 /* Frame successfuly transmited*/ 387 #define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/ 388 #define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/ 389 #define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout)*/ 390 #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ 391 #define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ 392 #define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ 393 #define AR5K_IMR_SWI 0x00002000 /* Software interrupt */ 394 #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ 395 #define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */ 396 #define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ 397 #define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ 398 #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ 399 #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 400 #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ 401 #define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ 402 #define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/ 403 #define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */ 404 #define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */ 405 #define AR5K_IMR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ 406 #define AR5K_IMR_TIM 0x00800000 /* [5211+] */ 407 #define AR5K_IMR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, 408 CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ 409 #define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ 410 #define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */ 411 #define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */ 412 #define AR5K_IMR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ 413 414 /* 415 * Secondary interrupt mask registers [5211+] (0 - 4) 416 */ 417 #define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */ 418 #define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ 419 #define AR5K_SIMR0_QCU_TXOK_S 0 420 #define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ 421 #define AR5K_SIMR0_QCU_TXDESC_S 16 422 423 #define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */ 424 #define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ 425 #define AR5K_SIMR1_QCU_TXERR_S 0 426 #define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ 427 #define AR5K_SIMR1_QCU_TXEOL_S 16 428 429 #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ 430 #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ 431 #define AR5K_SIMR2_QCU_TXURN_S 0 432 #define AR5K_SIMR2_MCABT 0x00010000 /* Master Cycle Abort */ 433 #define AR5K_SIMR2_SSERR 0x00020000 /* Signaled System Error */ 434 #define AR5K_SIMR2_DPERR 0x00040000 /* Bus parity error */ 435 #define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ 436 #define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ 437 #define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */ 438 #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ 439 #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ 440 #define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ 441 #define AR5K_SIMR2_TSFOOR 0x80000000 /* TSF OOR (?) */ 442 443 #define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ 444 #define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ 445 #define AR5K_SIMR3_QCBRORN_S 0 446 #define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ 447 #define AR5K_SIMR3_QCBRURN_S 16 448 449 #define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */ 450 #define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ 451 #define AR5K_SIMR4_QTRIG_S 0 452 453 /* 454 * DMA Debug registers 0-7 455 * 0xe0 - 0xfc 456 */ 457 458 /* 459 * Decompression mask registers [5212+] 460 */ 461 #define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */ 462 #define AR5K_DCM_DATA 0x0404 /*Decompression mask data */ 463 464 /* 465 * Wake On Wireless pattern control register [5212+] 466 */ 467 #define AR5K_WOW_PCFG 0x0410 /* Register Address */ 468 #define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */ 469 #define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 /* Long frame policy */ 470 #define AR5K_WOW_PCFG_WOBMISS 0x00000004 /* Wake on bea(con) miss (?) */ 471 #define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */ 472 #define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */ 473 #define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */ 474 #define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */ 475 #define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */ 476 #define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */ 477 478 /* 479 * Wake On Wireless pattern index register (?) [5212+] 480 */ 481 #define AR5K_WOW_PAT_IDX 0x0414 482 483 /* 484 * Wake On Wireless pattern data register [5212+] 485 */ 486 #define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */ 487 #define AR5K_WOW_PAT_DATA_0_3_V 0x00000001 /* Pattern 0, 3 value */ 488 #define AR5K_WOW_PAT_DATA_1_4_V 0x00000100 /* Pattern 1, 4 value */ 489 #define AR5K_WOW_PAT_DATA_2_5_V 0x00010000 /* Pattern 2, 5 value */ 490 #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */ 491 #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */ 492 #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */ 493 494 /* 495 * Decompression configuration registers [5212+] 496 */ 497 #define AR5K_DCCFG 0x0420 /* Register Address */ 498 #define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */ 499 #define AR5K_DCCFG_BYPASS_EN 0x00000002 /* Bypass decompression */ 500 #define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */ 501 #define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */ 502 503 /* 504 * Compression configuration registers [5212+] 505 */ 506 #define AR5K_CCFG 0x0600 /* Register Address */ 507 #define AR5K_CCFG_WINDOW_SIZE 0x00000007 /* Compression window size */ 508 #define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */ 509 510 #define AR5K_CCFG_CCU 0x0604 /* Register Address */ 511 #define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */ 512 #define AR5K_CCFG_CCU_CREDIT 0x00000002 /* CCU Credit (field) */ 513 #define AR5K_CCFG_CCU_CD_THRES 0x00000080 /* CCU Cyc(lic?) debt threshold (field) */ 514 #define AR5K_CCFG_CCU_CUP_LCNT 0x00010000 /* CCU Catchup lit(?) count */ 515 #define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */ 516 517 /* 518 * Compression performance counter registers [5212+] 519 */ 520 #define AR5K_CPC0 0x0610 /* Compression performance counter 0 */ 521 #define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ 522 #define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ 523 #define AR5K_CPC3 0x061c /* Compression performance counter 3 */ 524 #define AR5K_CPCOVF 0x0620 /* Compression performance overflow */ 525 526 527 /* 528 * Queue control unit (QCU) registers [5211+] 529 * 530 * Card has 12 TX Queues but i see that only 0-9 are used (?) 531 * both in binary HAL (see ah.h) and ar5k. Each queue has it's own 532 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) 533 * configuration register (0x08c0 - 0x08ec), a ready time configuration 534 * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - 535 * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some 536 * global registers, QCU transmit enable/disable and "one shot arm (?)" 537 * set/clear, which contain status for all queues (we shift by 1 for each 538 * queue). To access these registers easily we define some macros here 539 * that are used inside HAL. For more infos check out *_tx_queue functs. 540 */ 541 542 /* 543 * Generic QCU Register access macros 544 */ 545 #define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r) 546 #define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q)) 547 #define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q)) 548 549 /* 550 * QCU Transmit descriptor pointer registers 551 */ 552 #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */ 553 #define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q) 554 555 /* 556 * QCU Transmit enable register 557 */ 558 #define AR5K_QCU_TXE 0x0840 559 #define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q) 560 #define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q) 561 562 /* 563 * QCU Transmit disable register 564 */ 565 #define AR5K_QCU_TXD 0x0880 566 #define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q) 567 #define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q) 568 569 /* 570 * QCU Constant Bit Rate configuration registers 571 */ 572 #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */ 573 #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */ 574 #define AR5K_QCU_CBRCFG_INTVAL_S 0 575 #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */ 576 #define AR5K_QCU_CBRCFG_ORN_THRES_S 24 577 #define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q) 578 579 /* 580 * QCU Ready time configuration registers 581 */ 582 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ 583 #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ 584 #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 585 #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ 586 #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) 587 588 /* 589 * QCU one shot arm set registers 590 */ 591 #define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */ 592 #define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff 593 594 /* 595 * QCU one shot arm clear registers 596 */ 597 #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */ 598 #define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff 599 600 /* 601 * QCU misc registers 602 */ 603 #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ 604 #define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ 605 #define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ 606 #define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ 607 #define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */ 608 #define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* TIMT gated */ 609 #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated */ 610 #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ 611 #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */ 612 #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */ 613 #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */ 614 #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */ 615 #define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */ 616 #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */ 617 #define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */ 618 #define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */ 619 #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) 620 621 622 /* 623 * QCU status registers 624 */ 625 #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ 626 #define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ 627 #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */ 628 #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) 629 630 /* 631 * QCU ready time shutdown register 632 */ 633 #define AR5K_QCU_RDYTIMESHDN 0x0a40 634 #define AR5K_QCU_RDYTIMESHDN_M 0x000003ff 635 636 /* 637 * QCU compression buffer base registers [5212+] 638 */ 639 #define AR5K_QCU_CBB_SELECT 0x0b00 640 #define AR5K_QCU_CBB_ADDR 0x0b04 641 #define AR5K_QCU_CBB_ADDR_S 9 642 643 /* 644 * QCU compression buffer configuration register [5212+] 645 * (buffer size) 646 */ 647 #define AR5K_QCU_CBCFG 0x0b08 648 649 650 651 /* 652 * Distributed Coordination Function (DCF) control unit (DCU) 653 * registers [5211+] 654 * 655 * These registers control the various characteristics of each queue 656 * for 802.11e (WME) combatibility so they go together with 657 * QCU registers in pairs. For each queue we have a QCU mask register, 658 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c), 659 * a retry limit register (0x1080 - 0x10ac), a channel time register 660 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and 661 * a sequence number register (0x1140 - 0x116c). It seems that "global" 662 * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). 663 * We use the same macros here for easier register access. 664 * 665 */ 666 667 /* 668 * DCU QCU mask registers 669 */ 670 #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */ 671 #define AR5K_DCU_QCUMASK_M 0x000003ff 672 #define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q) 673 674 /* 675 * DCU local Inter Frame Space settings register 676 */ 677 #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */ 678 #define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */ 679 #define AR5K_DCU_LCL_IFS_CW_MIN_S 0 680 #define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */ 681 #define AR5K_DCU_LCL_IFS_CW_MAX_S 10 682 #define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */ 683 #define AR5K_DCU_LCL_IFS_AIFS_S 20 684 #define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc /* Anything above that can cause DCU to hang */ 685 #define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) 686 687 /* 688 * DCU retry limit registers 689 */ 690 #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */ 691 #define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ 692 #define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0 693 #define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry limit mask */ 694 #define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4 695 #define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask (?) */ 696 #define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 697 #define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask (?) */ 698 #define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 699 #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q) 700 701 /* 702 * DCU channel time registers 703 */ 704 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */ 705 #define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */ 706 #define AR5K_DCU_CHAN_TIME_DUR_S 0 707 #define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */ 708 #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q) 709 710 /* 711 * DCU misc registers [5211+] 712 * 713 * Note: Arbiter lockout control controls the 714 * behaviour on low priority queues when we have multiple queues 715 * with pending frames. Intra-frame lockout means we wait until 716 * the queue's current frame transmits (with post frame backoff and bursting) 717 * before we transmit anything else and global lockout means we 718 * wait for the whole queue to finish before higher priority queues 719 * can transmit (this is used on beacon and CAB queues). 720 * No lockout means there is no special handling. 721 */ 722 #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ 723 #define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */ 724 #define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040 /* End of transmission series 725 station RTS/data failure count 726 reset policy (?) */ 727 #define AR5K_DCU_MISC_ETS_CW_POL 0x00000080 /* End of transmission series 728 CW reset policy */ 729 #define AR5K_DCU_MISC_FRAG_WAIT 0x00000100 /* Wait for next fragment */ 730 #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ 731 #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */ 732 #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */ 733 #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */ 734 #define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ 735 #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 736 #define AR5K_DCU_MISC_VIRTCOL_IGNORE 1 737 #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */ 738 #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ 739 #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 740 #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ 741 #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ 742 #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ 743 #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 /* Ignore Arbiter lockout */ 744 #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment */ 745 #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */ 746 #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision cw policy */ 747 #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS policy (?) */ 748 #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ 749 #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) 750 751 /* 752 * DCU frame sequence number registers 753 */ 754 #define AR5K_DCU_SEQNUM_BASE 0x1140 755 #define AR5K_DCU_SEQNUM_M 0x00000fff 756 #define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) 757 758 /* 759 * DCU global IFS SIFS register 760 */ 761 #define AR5K_DCU_GBL_IFS_SIFS 0x1030 762 #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff 763 764 /* 765 * DCU global IFS slot interval register 766 */ 767 #define AR5K_DCU_GBL_IFS_SLOT 0x1070 768 #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff 769 770 /* 771 * DCU global IFS EIFS register 772 */ 773 #define AR5K_DCU_GBL_IFS_EIFS 0x10b0 774 #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff 775 776 /* 777 * DCU global IFS misc register 778 * 779 * LFSR stands for Linear Feedback Shift Register 780 * and it's used for generating pseudo-random 781 * number sequences. 782 * 783 * (If i understand corectly, random numbers are 784 * used for idle sensing -multiplied with cwmin/max etc-) 785 */ 786 #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ 787 #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 /* LFSR Slice Select */ 788 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */ 789 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */ 790 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S 4 791 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */ 792 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10 793 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */ 794 #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */ 795 #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */ 796 #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */ 797 798 /* 799 * DCU frame prefetch control register 800 */ 801 #define AR5K_DCU_FP 0x1230 /* Register Address */ 802 #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */ 803 #define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */ 804 #define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */ 805 806 /* 807 * DCU transmit pause control/status register 808 */ 809 #define AR5K_DCU_TXP 0x1270 /* Register Address */ 810 #define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */ 811 #define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */ 812 813 /* 814 * DCU transmit filter table 0 (32 entries) 815 * each entry contains a 32bit slice of the 816 * 128bit tx filter for each DCU (4 slices per DCU) 817 */ 818 #define AR5K_DCU_TX_FILTER_0_BASE 0x1038 819 #define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64)) 820 821 /* 822 * DCU transmit filter table 1 (16 entries) 823 */ 824 #define AR5K_DCU_TX_FILTER_1_BASE 0x103c 825 #define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64)) 826 827 /* 828 * DCU clear transmit filter register 829 */ 830 #define AR5K_DCU_TX_FILTER_CLR 0x143c 831 832 /* 833 * DCU set transmit filter register 834 */ 835 #define AR5K_DCU_TX_FILTER_SET 0x147c 836 837 /* 838 * Reset control register 839 */ 840 #define AR5K_RESET_CTL 0x4000 /* Register Address */ 841 #define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ 842 #define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */ 843 #define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */ 844 #define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ 845 #define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */ 846 #define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */ 847 848 /* 849 * Sleep control register 850 */ 851 #define AR5K_SLEEP_CTL 0x4004 /* Register Address */ 852 #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */ 853 #define AR5K_SLEEP_CTL_SLDUR_S 0 854 #define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */ 855 #define AR5K_SLEEP_CTL_SLE_S 16 856 #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ 857 #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ 858 #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 /* Normal sleep policy */ 859 #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ 860 #define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */ 861 #define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */ 862 #define AR5K_SLEEP_CTL_SLE_POL 0x00100000 /* Sleep policy mode */ 863 864 /* 865 * Interrupt pending register 866 */ 867 #define AR5K_INTPEND 0x4008 868 #define AR5K_INTPEND_M 0x00000001 869 870 /* 871 * Sleep force register 872 */ 873 #define AR5K_SFR 0x400c 874 #define AR5K_SFR_EN 0x00000001 875 876 /* 877 * PCI configuration register 878 * TODO: Fix LED stuff 879 */ 880 #define AR5K_PCICFG 0x4010 /* Register Address */ 881 #define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ 882 #define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */ 883 #define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ 884 #define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ 885 #define AR5K_PCICFG_EESIZE_S 3 886 #define AR5K_PCICFG_EESIZE_4K 0 /* 4K */ 887 #define AR5K_PCICFG_EESIZE_8K 1 /* 8K */ 888 #define AR5K_PCICFG_EESIZE_16K 2 /* 16K */ 889 #define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size [5211+] */ 890 #define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */ 891 #define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */ 892 #define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */ 893 #define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */ 894 #define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */ 895 #define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */ 896 #define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */ 897 #define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ 898 #define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */ 899 #define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even whith pending interrupts*/ 900 #define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ 901 #define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ 902 #define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ 903 #define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ 904 #define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ 905 #define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ 906 #define AR5K_PCICFG_LEDBLINK 0x00700000 /* Led blink rate */ 907 #define AR5K_PCICFG_LEDBLINK_S 20 908 #define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slowest led blink rate [5211+] */ 909 #define AR5K_PCICFG_LEDSTATE \ 910 (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ 911 AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) 912 #define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate */ 913 #define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24 914 915 /* 916 * "General Purpose Input/Output" (GPIO) control register 917 * 918 * I'm not sure about this but after looking at the code 919 * for all chipsets here is what i got. 920 * 921 * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits) 922 * Mode 0 -> always input 923 * Mode 1 -> output when GPIODO for this GPIO is set to 0 924 * Mode 2 -> output when GPIODO for this GPIO is set to 1 925 * Mode 3 -> always output 926 * 927 * For more infos check out get_gpio/set_gpio and 928 * set_gpio_input/set_gpio_output functs. 929 * For more infos on gpio interrupt check out set_gpio_intr. 930 */ 931 #define AR5K_NUM_GPIO 6 932 933 #define AR5K_GPIOCR 0x4014 /* Register Address */ 934 #define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ 935 #define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is low */ 936 #define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is high */ 937 #define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */ 938 #define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */ 939 #define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */ 940 #define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */ 941 #define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */ 942 943 /* 944 * "General Purpose Input/Output" (GPIO) data output register 945 */ 946 #define AR5K_GPIODO 0x4018 947 948 /* 949 * "General Purpose Input/Output" (GPIO) data input register 950 */ 951 #define AR5K_GPIODI 0x401c 952 #define AR5K_GPIODI_M 0x0000002f 953 954 /* 955 * Silicon revision register 956 */ 957 #define AR5K_SREV 0x4020 /* Register Address */ 958 #define AR5K_SREV_REV 0x0000000f /* Mask for revision */ 959 #define AR5K_SREV_REV_S 0 960 #define AR5K_SREV_VER 0x000000ff /* Mask for version */ 961 #define AR5K_SREV_VER_S 4 962 963 /* 964 * TXE write posting register 965 */ 966 #define AR5K_TXEPOST 0x4028 967 968 /* 969 * QCU sleep mask 970 */ 971 #define AR5K_QCU_SLEEP_MASK 0x402c 972 973 /* 0x4068 is compression buffer configuration 974 * register on 5414 and pm configuration register 975 * on 5424 and newer pci-e chips. */ 976 977 /* 978 * Compression buffer configuration 979 * register (enable/disable) [5414] 980 */ 981 #define AR5K_5414_CBCFG 0x4068 982 #define AR5K_5414_CBCFG_BUF_DIS 0x10 /* Disable buffer */ 983 984 /* 985 * PCI-E Power management configuration 986 * and status register [5424+] 987 */ 988 #define AR5K_PCIE_PM_CTL 0x4068 /* Register address */ 989 /* Only 5424 */ 990 #define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L1 991 when d2_sleep_en is asserted */ 992 #define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 /* Clear L0 and L0S counters */ 993 #define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 /* Start L0 nd L0S counters */ 994 #define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes 995 down */ 996 /* Wake On Wireless */ 997 #define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */ 998 #define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 /* Aux power detect */ 999 #define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 /* Clear PME */ 1000 #define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080 1001 #define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100 1002 #define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200 1003 #define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400 1004 1005 /* 1006 * PCI-E Workaround enable register 1007 */ 1008 #define AR5K_PCIE_WAEN 0x407c 1009 1010 /* 1011 * PCI-E Serializer/Desirializer 1012 * registers 1013 */ 1014 #define AR5K_PCIE_SERDES 0x4080 1015 #define AR5K_PCIE_SERDES_RESET 0x4084 1016 1017 /*====EEPROM REGISTERS====*/ 1018 1019 /* 1020 * EEPROM access registers 1021 * 1022 * Here we got a difference between 5210/5211-12 1023 * read data register for 5210 is at 0x6800 and 1024 * status register is at 0x6c00. There is also 1025 * no eeprom command register on 5210 and the 1026 * offsets are different. 1027 * 1028 * To read eeprom data for a specific offset: 1029 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) 1030 * read AR5K_EEPROM_BASE +(4 * offset) 1031 * check the eeprom status register 1032 * and read eeprom data register. 1033 * 1034 * 5211 - write offset to AR5K_EEPROM_BASE 1035 * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD 1036 * check the eeprom status register 1037 * and read eeprom data register. 1038 * 1039 * To write eeprom data for a specific offset: 1040 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) 1041 * write data to AR5K_EEPROM_BASE +(4 * offset) 1042 * check the eeprom status register 1043 * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD 1044 * 5212 write offset to AR5K_EEPROM_BASE 1045 * write data to data register 1046 * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD 1047 * check the eeprom status register 1048 * 1049 * For more infos check eeprom_* functs and the ar5k.c 1050 * file posted in madwifi-devel mailing list. 1051 * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 1052 * 1053 */ 1054 #define AR5K_EEPROM_BASE 0x6000 1055 1056 /* 1057 * EEPROM data register 1058 */ 1059 #define AR5K_EEPROM_DATA_5211 0x6004 1060 #define AR5K_EEPROM_DATA_5210 0x6800 1061 #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \ 1062 AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) 1063 1064 /* 1065 * EEPROM command register 1066 */ 1067 #define AR5K_EEPROM_CMD 0x6008 /* Register Addres */ 1068 #define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */ 1069 #define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */ 1070 #define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */ 1071 1072 /* 1073 * EEPROM status register 1074 */ 1075 #define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */ 1076 #define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */ 1077 #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \ 1078 AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) 1079 #define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */ 1080 #define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */ 1081 #define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */ 1082 #define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ 1083 1084 /* 1085 * EEPROM config register 1086 */ 1087 #define AR5K_EEPROM_CFG 0x6010 /* Register Addres */ 1088 #define AR5K_EEPROM_CFG_SIZE 0x00000003 /* Size determination override */ 1089 #define AR5K_EEPROM_CFG_SIZE_AUTO 0 1090 #define AR5K_EEPROM_CFG_SIZE_4KBIT 1 1091 #define AR5K_EEPROM_CFG_SIZE_8KBIT 2 1092 #define AR5K_EEPROM_CFG_SIZE_16KBIT 3 1093 #define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */ 1094 #define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */ 1095 #define AR5K_EEPROM_CFG_CLK_RATE_S 3 1096 #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0 1097 #define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1 1098 #define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2 1099 #define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protection key */ 1100 #define AR5K_EEPROM_CFG_PROT_KEY_S 8 1101 #define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */ 1102 1103 1104 /* 1105 * TODO: Wake On Wireless registers 1106 * Range 0x7000 - 0x7ce0 1107 */ 1108 1109 /* 1110 * Protocol Control Unit (PCU) registers 1111 */ 1112 /* 1113 * Used for checking initial register writes 1114 * during channel reset (see reset func) 1115 */ 1116 #define AR5K_PCU_MIN 0x8000 1117 #define AR5K_PCU_MAX 0x8fff 1118 1119 /* 1120 * First station id register (Lower 32 bits of MAC address) 1121 */ 1122 #define AR5K_STA_ID0 0x8000 1123 #define AR5K_STA_ID0_ARRD_L32 0xffffffff 1124 1125 /* 1126 * Second station id register (Upper 16 bits of MAC address + PCU settings) 1127 */ 1128 #define AR5K_STA_ID1 0x8004 /* Register Address */ 1129 #define AR5K_STA_ID1_ADDR_U16 0x0000ffff /* Upper 16 bits of MAC addres */ 1130 #define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ 1131 #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ 1132 #define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */ 1133 #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ 1134 #define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ 1135 #define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ 1136 #define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/ 1137 #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \ 1138 AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) 1139 #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ 1140 #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ 1141 #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */ 1142 #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Rate to use for ACK/CTS. 0: highest mandatory rate <= RX rate; 1: 1Mbps in B mode */ 1143 #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* 802.11b base rate. 0: 1, 2, 5.5 and 11Mbps; 1: 1 and 2Mbps. [5211+] */ 1144 #define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 /* Use def. antenna for self generated frames */ 1145 #define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */ 1146 #define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Look up key when key id != 0 */ 1147 #define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */ 1148 #define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 /* ??? */ 1149 #define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 /* Do key cache search for mcast frames */ 1150 1151 #define AR5K_STA_ID1_ANTENNA_SETTINGS (AR5K_STA_ID1_DEFAULT_ANTENNA | \ 1152 AR5K_STA_ID1_DESC_ANTENNA | \ 1153 AR5K_STA_ID1_RTS_DEF_ANTENNA | \ 1154 AR5K_STA_ID1_SELFGEN_DEF_ANT) 1155 1156 /* 1157 * First BSSID register (MAC address, lower 32bits) 1158 */ 1159 #define AR5K_BSS_ID0 0x8008 1160 1161 /* 1162 * Second BSSID register (MAC address in upper 16 bits) 1163 * 1164 * AID: Association ID 1165 */ 1166 #define AR5K_BSS_ID1 0x800c 1167 #define AR5K_BSS_ID1_AID 0xffff0000 1168 #define AR5K_BSS_ID1_AID_S 16 1169 1170 /* 1171 * Backoff slot time register 1172 */ 1173 #define AR5K_SLOT_TIME 0x8010 1174 1175 /* 1176 * ACK/CTS timeout register 1177 */ 1178 #define AR5K_TIME_OUT 0x8014 /* Register Address */ 1179 #define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */ 1180 #define AR5K_TIME_OUT_ACK_S 0 1181 #define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */ 1182 #define AR5K_TIME_OUT_CTS_S 16 1183 1184 /* 1185 * RSSI threshold register 1186 */ 1187 #define AR5K_RSSI_THR 0x8018 /* Register Address */ 1188 #define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */ 1189 #define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */ 1190 #define AR5K_RSSI_THR_BMISS_5210_S 8 1191 #define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */ 1192 #define AR5K_RSSI_THR_BMISS_5211_S 8 1193 #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \ 1194 AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) 1195 #define AR5K_RSSI_THR_BMISS_S 8 1196 1197 /* 1198 * 5210 has more PCU registers because there is no QCU/DCU 1199 * so queue parameters are set here, this way a lot common 1200 * registers have different address for 5210. To make things 1201 * easier we define a macro based on ah->ah_version for common 1202 * registers with different addresses and common flags. 1203 */ 1204 1205 /* 1206 * Retry limit register 1207 * 1208 * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) 1209 */ 1210 #define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */ 1211 #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ 1212 #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 1213 #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ 1214 #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 1215 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */ 1216 #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8 1217 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */ 1218 #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14 1219 #define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */ 1220 #define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20 1221 1222 /* 1223 * Transmit latency register 1224 */ 1225 #define AR5K_USEC_5210 0x8020 /* Register Address [5210] */ 1226 #define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ 1227 #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ 1228 AR5K_USEC_5210 : AR5K_USEC_5211) 1229 #define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */ 1230 #define AR5K_USEC_1_S 0 1231 #define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32Mhz clock */ 1232 #define AR5K_USEC_32_S 7 1233 #define AR5K_USEC_TX_LATENCY_5211 0x007fc000 1234 #define AR5K_USEC_TX_LATENCY_5211_S 14 1235 #define AR5K_USEC_RX_LATENCY_5211 0x1f800000 1236 #define AR5K_USEC_RX_LATENCY_5211_S 23 1237 #define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /* also for 5311 */ 1238 #define AR5K_USEC_TX_LATENCY_5210_S 14 1239 #define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /* also for 5311 */ 1240 #define AR5K_USEC_RX_LATENCY_5210_S 20 1241 1242 /* 1243 * PCU beacon control register 1244 */ 1245 #define AR5K_BEACON_5210 0x8024 /*Register Address [5210] */ 1246 #define AR5K_BEACON_5211 0x8020 /*Register Address [5211+] */ 1247 #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ 1248 AR5K_BEACON_5210 : AR5K_BEACON_5211) 1249 #define AR5K_BEACON_PERIOD 0x0000ffff /* Mask for beacon period */ 1250 #define AR5K_BEACON_PERIOD_S 0 1251 #define AR5K_BEACON_TIM 0x007f0000 /* Mask for TIM offset */ 1252 #define AR5K_BEACON_TIM_S 16 1253 #define AR5K_BEACON_ENABLE 0x00800000 /* Enable beacons */ 1254 #define AR5K_BEACON_RESET_TSF 0x01000000 /* Force TSF reset */ 1255 1256 /* 1257 * CFP period register 1258 */ 1259 #define AR5K_CFP_PERIOD_5210 0x8028 1260 #define AR5K_CFP_PERIOD_5211 0x8024 1261 #define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \ 1262 AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) 1263 1264 /* 1265 * Next beacon time register 1266 */ 1267 #define AR5K_TIMER0_5210 0x802c 1268 #define AR5K_TIMER0_5211 0x8028 1269 #define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \ 1270 AR5K_TIMER0_5210 : AR5K_TIMER0_5211) 1271 1272 /* 1273 * Next DMA beacon alert register 1274 */ 1275 #define AR5K_TIMER1_5210 0x8030 1276 #define AR5K_TIMER1_5211 0x802c 1277 #define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \ 1278 AR5K_TIMER1_5210 : AR5K_TIMER1_5211) 1279 1280 /* 1281 * Next software beacon alert register 1282 */ 1283 #define AR5K_TIMER2_5210 0x8034 1284 #define AR5K_TIMER2_5211 0x8030 1285 #define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \ 1286 AR5K_TIMER2_5210 : AR5K_TIMER2_5211) 1287 1288 /* 1289 * Next ATIM window time register 1290 */ 1291 #define AR5K_TIMER3_5210 0x8038 1292 #define AR5K_TIMER3_5211 0x8034 1293 #define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \ 1294 AR5K_TIMER3_5210 : AR5K_TIMER3_5211) 1295 1296 1297 /* 1298 * 5210 First inter frame spacing register (IFS) 1299 */ 1300 #define AR5K_IFS0 0x8040 1301 #define AR5K_IFS0_SIFS 0x000007ff 1302 #define AR5K_IFS0_SIFS_S 0 1303 #define AR5K_IFS0_DIFS 0x007ff800 1304 #define AR5K_IFS0_DIFS_S 11 1305 1306 /* 1307 * 5210 Second inter frame spacing register (IFS) 1308 */ 1309 #define AR5K_IFS1 0x8044 1310 #define AR5K_IFS1_PIFS 0x00000fff 1311 #define AR5K_IFS1_PIFS_S 0 1312 #define AR5K_IFS1_EIFS 0x03fff000 1313 #define AR5K_IFS1_EIFS_S 12 1314 #define AR5K_IFS1_CS_EN 0x04000000 1315 #define AR5K_IFS1_CS_EN_S 26 1316 1317 /* 1318 * CFP duration register 1319 */ 1320 #define AR5K_CFP_DUR_5210 0x8048 1321 #define AR5K_CFP_DUR_5211 0x8038 1322 #define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \ 1323 AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) 1324 1325 /* 1326 * Receive filter register 1327 */ 1328 #define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ 1329 #define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ 1330 #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ 1331 AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) 1332 #define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ 1333 #define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ 1334 #define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ 1335 #define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ 1336 #define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ 1337 #define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ 1338 #define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ 1339 #define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ 1340 #define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ 1341 #define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ 1342 #define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ 1343 #define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ 1344 #define AR5K_RX_FILTER_PHYERR \ 1345 ((ah->ah_version == AR5K_AR5211 ? \ 1346 AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212)) 1347 #define AR5K_RX_FILTER_RADARERR \ 1348 ((ah->ah_version == AR5K_AR5211 ? \ 1349 AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212)) 1350 1351 /* 1352 * Multicast filter register (lower 32 bits) 1353 */ 1354 #define AR5K_MCAST_FILTER0_5210 0x8050 1355 #define AR5K_MCAST_FILTER0_5211 0x8040 1356 #define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \ 1357 AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) 1358 1359 /* 1360 * Multicast filter register (higher 16 bits) 1361 */ 1362 #define AR5K_MCAST_FILTER1_5210 0x8054 1363 #define AR5K_MCAST_FILTER1_5211 0x8044 1364 #define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \ 1365 AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) 1366 1367 1368 /* 1369 * Transmit mask register (lower 32 bits) [5210] 1370 */ 1371 #define AR5K_TX_MASK0 0x8058 1372 1373 /* 1374 * Transmit mask register (higher 16 bits) [5210] 1375 */ 1376 #define AR5K_TX_MASK1 0x805c 1377 1378 /* 1379 * Clear transmit mask [5210] 1380 */ 1381 #define AR5K_CLR_TMASK 0x8060 1382 1383 /* 1384 * Trigger level register (before transmission) [5210] 1385 */ 1386 #define AR5K_TRIG_LVL 0x8064 1387 1388 1389 /* 1390 * PCU Diagnostic register 1391 * 1392 * Used for tweaking/diagnostics. 1393 */ 1394 #define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */ 1395 #define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ 1396 #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ 1397 AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) 1398 #define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */ 1399 #define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */ 1400 #define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */ 1401 #define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable HW encryption */ 1402 #define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable HW decryption */ 1403 #define AR5K_DIAG_SW_DIS_TX_5210 0x00000020 /* Disable transmit [5210] */ 1404 #define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable receive */ 1405 #define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 1406 #define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \ 1407 AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) 1408 #define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* TX Data Loopback (i guess it goes with DIS_TX) [5210] */ 1409 #define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 1410 #define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ 1411 AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) 1412 #define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Generate invalid TX FCS */ 1413 #define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 1414 #define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ 1415 AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) 1416 #define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Add 56 bytes of channel info before the frame data in the RX buffer */ 1417 #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 1418 #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ 1419 AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) 1420 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 /* Enable fixed scrambler seed */ 1421 #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 1422 #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ 1423 AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) 1424 #define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ 1425 #define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ 1426 #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */ 1427 #define AR5K_DIAG_SW_SCRAM_SEED_S 10 1428 #define AR5K_DIAG_SW_DIS_SEQ_INC_5210 0x00040000 /* Disable seqnum increment (?)[5210] */ 1429 #define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 1430 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */ 1431 #define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ 1432 AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) 1433 #define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */ 1434 #define AR5K_DIAG_SW_OBSPT_S 18 1435 #define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x00100000 /* Ignore carrier sense */ 1436 #define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x00200000 /* Ignore virtual carrier sense */ 1437 #define AR5K_DIAG_SW_CHANNEL_IDLE_HIGH 0x00400000 /* Force channel idle high */ 1438 #define AR5K_DIAG_SW_PHEAR_ME 0x00800000 /* ??? */ 1439 1440 /* 1441 * TSF (clock) register (lower 32 bits) 1442 */ 1443 #define AR5K_TSF_L32_5210 0x806c 1444 #define AR5K_TSF_L32_5211 0x804c 1445 #define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \ 1446 AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) 1447 1448 /* 1449 * TSF (clock) register (higher 32 bits) 1450 */ 1451 #define AR5K_TSF_U32_5210 0x8070 1452 #define AR5K_TSF_U32_5211 0x8050 1453 #define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \ 1454 AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) 1455 1456 /* 1457 * Last beacon timestamp register (Read Only) 1458 */ 1459 #define AR5K_LAST_TSTP 0x8080 1460 1461 /* 1462 * ADDAC test register [5211+] 1463 */ 1464 #define AR5K_ADDAC_TEST 0x8054 /* Register Address */ 1465 #define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */ 1466 #define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */ 1467 #define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */ 1468 #define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */ 1469 #define AR5K_ADDAC_TEST_USE_U8 0x00004000 /* Use upper 8 bits */ 1470 #define AR5K_ADDAC_TEST_MSB 0x00008000 /* State of MSB */ 1471 #define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000 /* Trigger select */ 1472 #define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */ 1473 #define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */ 1474 #define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */ 1475 #define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* ARM rx buffer for capture */ 1476 1477 /* 1478 * Default antenna register [5211+] 1479 */ 1480 #define AR5K_DEFAULT_ANTENNA 0x8058 1481 1482 /* 1483 * Frame control QoS mask register (?) [5211+] 1484 * (FC_QOS_MASK) 1485 */ 1486 #define AR5K_FRAME_CTL_QOSM 0x805c 1487 1488 /* 1489 * Seq mask register (?) [5211+] 1490 */ 1491 #define AR5K_SEQ_MASK 0x8060 1492 1493 /* 1494 * Retry count register [5210] 1495 */ 1496 #define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */ 1497 #define AR5K_RETRY_CNT_SSH 0x0000003f /* Station short retry count (?) */ 1498 #define AR5K_RETRY_CNT_SLG 0x00000fc0 /* Station long retry count (?) */ 1499 1500 /* 1501 * Back-off status register [5210] 1502 */ 1503 #define AR5K_BACKOFF 0x8088 /* Register Address [5210] */ 1504 #define AR5K_BACKOFF_CW 0x000003ff /* Backoff Contention Window (?) */ 1505 #define AR5K_BACKOFF_CNT 0x03ff0000 /* Backoff count (?) */ 1506 1507 1508 1509 /* 1510 * NAV register (current) 1511 */ 1512 #define AR5K_NAV_5210 0x808c 1513 #define AR5K_NAV_5211 0x8084 1514 #define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \ 1515 AR5K_NAV_5210 : AR5K_NAV_5211) 1516 1517 /* 1518 * MIB counters: 1519 * 1520 * max value is 0xc000, if this is reached we get a MIB interrupt. 1521 * they can be controlled via AR5K_MIBC and are cleared on read. 1522 */ 1523 1524 /* 1525 * RTS success (MIB counter) 1526 */ 1527 #define AR5K_RTS_OK_5210 0x8090 1528 #define AR5K_RTS_OK_5211 0x8088 1529 #define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \ 1530 AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) 1531 1532 /* 1533 * RTS failure (MIB counter) 1534 */ 1535 #define AR5K_RTS_FAIL_5210 0x8094 1536 #define AR5K_RTS_FAIL_5211 0x808c 1537 #define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \ 1538 AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) 1539 1540 /* 1541 * ACK failure (MIB counter) 1542 */ 1543 #define AR5K_ACK_FAIL_5210 0x8098 1544 #define AR5K_ACK_FAIL_5211 0x8090 1545 #define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \ 1546 AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) 1547 1548 /* 1549 * FCS failure (MIB counter) 1550 */ 1551 #define AR5K_FCS_FAIL_5210 0x809c 1552 #define AR5K_FCS_FAIL_5211 0x8094 1553 #define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \ 1554 AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) 1555 1556 /* 1557 * Beacon count register 1558 */ 1559 #define AR5K_BEACON_CNT_5210 0x80a0 1560 #define AR5K_BEACON_CNT_5211 0x8098 1561 #define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \ 1562 AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) 1563 1564 1565 /*===5212 Specific PCU registers===*/ 1566 1567 /* 1568 * Transmit power control register 1569 */ 1570 #define AR5K_TPC 0x80e8 1571 #define AR5K_TPC_ACK 0x0000003f /* ack frames */ 1572 #define AR5K_TPC_ACK_S 0 1573 #define AR5K_TPC_CTS 0x00003f00 /* cts frames */ 1574 #define AR5K_TPC_CTS_S 8 1575 #define AR5K_TPC_CHIRP 0x003f0000 /* chirp frames */ 1576 #define AR5K_TPC_CHIRP_S 16 1577 #define AR5K_TPC_DOPPLER 0x0f000000 /* doppler chirp span */ 1578 #define AR5K_TPC_DOPPLER_S 24 1579 1580 /* 1581 * XR (eXtended Range) mode register 1582 */ 1583 #define AR5K_XRMODE 0x80c0 /* Register Address */ 1584 #define AR5K_XRMODE_POLL_TYPE_M 0x0000003f /* Mask for Poll type (?) */ 1585 #define AR5K_XRMODE_POLL_TYPE_S 0 1586 #define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c /* Mask for Poll subtype (?) */ 1587 #define AR5K_XRMODE_POLL_SUBTYPE_S 2 1588 #define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 /* Wait for poll */ 1589 #define AR5K_XRMODE_SIFS_DELAY 0x000fff00 /* Mask for SIFS delay */ 1590 #define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 /* Mask for frame hold (?) */ 1591 #define AR5K_XRMODE_FRAME_HOLD_S 20 1592 1593 /* 1594 * XR delay register 1595 */ 1596 #define AR5K_XRDELAY 0x80c4 /* Register Address */ 1597 #define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff /* Mask for slot delay */ 1598 #define AR5K_XRDELAY_SLOT_DELAY_S 0 1599 #define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 /* Mask for CHIRP data delay */ 1600 #define AR5K_XRDELAY_CHIRP_DELAY_S 16 1601 1602 /* 1603 * XR timeout register 1604 */ 1605 #define AR5K_XRTIMEOUT 0x80c8 /* Register Address */ 1606 #define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff /* Mask for CHIRP timeout */ 1607 #define AR5K_XRTIMEOUT_CHIRP_S 0 1608 #define AR5K_XRTIMEOUT_POLL_M 0xffff0000 /* Mask for Poll timeout */ 1609 #define AR5K_XRTIMEOUT_POLL_S 16 1610 1611 /* 1612 * XR chirp register 1613 */ 1614 #define AR5K_XRCHIRP 0x80cc /* Register Address */ 1615 #define AR5K_XRCHIRP_SEND 0x00000001 /* Send CHIRP */ 1616 #define AR5K_XRCHIRP_GAP 0xffff0000 /* Mask for CHIRP gap (?) */ 1617 1618 /* 1619 * XR stomp register 1620 */ 1621 #define AR5K_XRSTOMP 0x80d0 /* Register Address */ 1622 #define AR5K_XRSTOMP_TX 0x00000001 /* Stomp Tx (?) */ 1623 #define AR5K_XRSTOMP_RX 0x00000002 /* Stomp Rx (?) */ 1624 #define AR5K_XRSTOMP_TX_RSSI 0x00000004 /* Stomp Tx RSSI (?) */ 1625 #define AR5K_XRSTOMP_TX_BSSID 0x00000008 /* Stomp Tx BSSID (?) */ 1626 #define AR5K_XRSTOMP_DATA 0x00000010 /* Stomp data (?)*/ 1627 #define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 /* Mask for XR RSSI threshold */ 1628 1629 /* 1630 * First enhanced sleep register 1631 */ 1632 #define AR5K_SLEEP0 0x80d4 /* Register Address */ 1633 #define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */ 1634 #define AR5K_SLEEP0_NEXT_DTIM_S 0 1635 #define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 /* Assume DTIM */ 1636 #define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enchanced sleep control */ 1637 #define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */ 1638 #define AR5K_SLEEP0_CABTO_S 24 1639 1640 /* 1641 * Second enhanced sleep register 1642 */ 1643 #define AR5K_SLEEP1 0x80d8 /* Register Address */ 1644 #define AR5K_SLEEP1_NEXT_TIM 0x0007ffff /* Mask for next TIM (?) */ 1645 #define AR5K_SLEEP1_NEXT_TIM_S 0 1646 #define AR5K_SLEEP1_BEACON_TO 0xff000000 /* Mask for Beacon Time Out */ 1647 #define AR5K_SLEEP1_BEACON_TO_S 24 1648 1649 /* 1650 * Third enhanced sleep register 1651 */ 1652 #define AR5K_SLEEP2 0x80dc /* Register Address */ 1653 #define AR5K_SLEEP2_TIM_PER 0x0000ffff /* Mask for TIM period (?) */ 1654 #define AR5K_SLEEP2_TIM_PER_S 0 1655 #define AR5K_SLEEP2_DTIM_PER 0xffff0000 /* Mask for DTIM period (?) */ 1656 #define AR5K_SLEEP2_DTIM_PER_S 16 1657 1658 /* 1659 * TX power control (TPC) register 1660 * 1661 * XXX: PCDAC steps (0.5dbm) or DBM ? 1662 * 1663 */ 1664 #define AR5K_TXPC 0x80e8 /* Register Address */ 1665 #define AR5K_TXPC_ACK_M 0x0000003f /* ACK tx power */ 1666 #define AR5K_TXPC_ACK_S 0 1667 #define AR5K_TXPC_CTS_M 0x00003f00 /* CTS tx power */ 1668 #define AR5K_TXPC_CTS_S 8 1669 #define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */ 1670 #define AR5K_TXPC_CHIRP_S 16 1671 #define AR5K_TXPC_DOPPLER 0x0f000000 /* Doppler chirp span (?) */ 1672 #define AR5K_TXPC_DOPPLER_S 24 1673 1674 /* 1675 * Profile count registers 1676 * 1677 * These registers can be cleared and freezed with ATH5K_MIBC, but they do not 1678 * generate a MIB interrupt. 1679 * Instead of overflowing, they shift by one bit to the right. All registers 1680 * shift together, i.e. when one reaches the max, all shift at the same time by 1681 * one bit to the right. This way we should always get consistent values. 1682 */ 1683 #define AR5K_PROFCNT_TX 0x80ec /* Tx count */ 1684 #define AR5K_PROFCNT_RX 0x80f0 /* Rx count */ 1685 #define AR5K_PROFCNT_RXCLR 0x80f4 /* Busy count */ 1686 #define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle counter */ 1687 1688 /* 1689 * Quiet period control registers 1690 */ 1691 #define AR5K_QUIET_CTL1 0x80fc /* Register Address */ 1692 #define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff /* Next quiet period TSF (TU) */ 1693 #define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0 1694 #define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */ 1695 #define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 /* Send ACK/CTS during quiet period */ 1696 1697 #define AR5K_QUIET_CTL2 0x8100 /* Register Address */ 1698 #define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period periodicity */ 1699 #define AR5K_QUIET_CTL2_QT_PER_S 0 1700 #define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet period duration */ 1701 #define AR5K_QUIET_CTL2_QT_DUR_S 16 1702 1703 /* 1704 * TSF parameter register 1705 */ 1706 #define AR5K_TSF_PARM 0x8104 /* Register Address */ 1707 #define AR5K_TSF_PARM_INC 0x000000ff /* Mask for TSF increment */ 1708 #define AR5K_TSF_PARM_INC_S 0 1709 1710 /* 1711 * QoS NOACK policy 1712 */ 1713 #define AR5K_QOS_NOACK 0x8108 /* Register Address */ 1714 #define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f /* ??? */ 1715 #define AR5K_QOS_NOACK_2BIT_VALUES_S 0 1716 #define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */ 1717 #define AR5K_QOS_NOACK_BIT_OFFSET_S 4 1718 #define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */ 1719 #define AR5K_QOS_NOACK_BYTE_OFFSET_S 7 1720 1721 /* 1722 * PHY error filter register 1723 */ 1724 #define AR5K_PHY_ERR_FIL 0x810c 1725 #define AR5K_PHY_ERR_FIL_RADAR 0x00000020 /* Radar signal */ 1726 #define AR5K_PHY_ERR_FIL_OFDM 0x00020000 /* OFDM false detect (ANI) */ 1727 #define AR5K_PHY_ERR_FIL_CCK 0x02000000 /* CCK false detect (ANI) */ 1728 1729 /* 1730 * XR latency register 1731 */ 1732 #define AR5K_XRLAT_TX 0x8110 1733 1734 /* 1735 * ACK SIFS register 1736 */ 1737 #define AR5K_ACKSIFS 0x8114 /* Register Address */ 1738 #define AR5K_ACKSIFS_INC 0x00000000 /* ACK SIFS Increment (field) */ 1739 1740 /* 1741 * MIC QoS control register (?) 1742 */ 1743 #define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */ 1744 #define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2)) 1745 #define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */ 1746 1747 /* 1748 * MIC QoS select register (?) 1749 */ 1750 #define AR5K_MIC_QOS_SEL 0x811c 1751 #define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4)) 1752 1753 /* 1754 * Misc mode control register (?) 1755 */ 1756 #define AR5K_MISC_MODE 0x8120 /* Register Address */ 1757 #define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001 /* Force BSSID match */ 1758 #define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 /* ACK SIFS memory (?) */ 1759 #define AR5K_MISC_MODE_COMBINED_MIC 0x00000004 /* use rx/tx MIC key */ 1760 /* more bits */ 1761 1762 /* 1763 * OFDM Filter counter 1764 */ 1765 #define AR5K_OFDM_FIL_CNT 0x8124 1766 1767 /* 1768 * CCK Filter counter 1769 */ 1770 #define AR5K_CCK_FIL_CNT 0x8128 1771 1772 /* 1773 * PHY Error Counters (same masks as AR5K_PHY_ERR_FIL) 1774 */ 1775 #define AR5K_PHYERR_CNT1 0x812c 1776 #define AR5K_PHYERR_CNT1_MASK 0x8130 1777 1778 #define AR5K_PHYERR_CNT2 0x8134 1779 #define AR5K_PHYERR_CNT2_MASK 0x8138 1780 1781 /* if the PHY Error Counters reach this maximum, we get MIB interrupts */ 1782 #define ATH5K_PHYERR_CNT_MAX 0x00c00000 1783 1784 /* 1785 * TSF Threshold register (?) 1786 */ 1787 #define AR5K_TSF_THRES 0x813c 1788 1789 /* 1790 * TODO: Wake On Wireless registers 1791 * Range: 0x8147 - 0x818c 1792 */ 1793 1794 /* 1795 * Rate -> ACK SIFS mapping table (32 entries) 1796 */ 1797 #define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */ 1798 #define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2)) 1799 #define AR5K_RATE_ACKSIFS_NORMAL 0x00000001 /* Normal SIFS (field) */ 1800 #define AR5K_RATE_ACKSIFS_TURBO 0x00000400 /* Turbo SIFS (field) */ 1801 1802 /* 1803 * Rate -> duration mapping table (32 entries) 1804 */ 1805 #define AR5K_RATE_DUR_BASE 0x8700 1806 #define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) 1807 1808 /* 1809 * Rate -> db mapping table 1810 * (8 entries, each one has 4 8bit fields) 1811 */ 1812 #define AR5K_RATE2DB_BASE 0x87c0 1813 #define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2)) 1814 1815 /* 1816 * db -> Rate mapping table 1817 * (8 entries, each one has 4 8bit fields) 1818 */ 1819 #define AR5K_DB2RATE_BASE 0x87e0 1820 #define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2)) 1821 1822 /*===5212 end===*/ 1823 1824 #define AR5K_KEYTABLE_SIZE_5210 64 1825 #define AR5K_KEYTABLE_SIZE_5211 128 1826 1827 /*===PHY REGISTERS===*/ 1828 1829 /* 1830 * PHY registers start 1831 */ 1832 #define AR5K_PHY_BASE 0x9800 1833 #define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) 1834 1835 /* 1836 * TST_2 (Misc config parameters) 1837 */ 1838 #define AR5K_PHY_TST2 0x9800 /* Register Address */ 1839 #define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/ 1840 #define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */ 1841 #define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */ 1842 #define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */ 1843 #define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */ 1844 #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */ 1845 #define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */ 1846 #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */ 1847 #define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */ 1848 #define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */ 1849 #define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */ 1850 #define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 /* AGC OBS Select 3 (?) */ 1851 #define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 /* BB OBS Select (field ?) */ 1852 #define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 /* ADC OBS Select (field ?) */ 1853 #define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000 /* RX Clear Select (?) */ 1854 #define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 /* Force AGC clear (?) */ 1855 #define AR5K_PHY_SHIFT_2GHZ 0x00004007 /* Used to access 2GHz radios */ 1856 #define AR5K_PHY_SHIFT_5GHZ 0x00000007 /* Used to access 5GHz radios (default) */ 1857 1858 /* 1859 * PHY frame control register [5110] /turbo mode register [5111+] 1860 * 1861 * There is another frame control register for [5111+] 1862 * at address 0x9944 (see below) but the 2 first flags 1863 * are common here between 5110 frame control register 1864 * and [5111+] turbo mode register, so this also works as 1865 * a "turbo mode register" for 5110. We treat this one as 1866 * a frame control register for 5110 below. 1867 */ 1868 #define AR5K_PHY_TURBO 0x9804 /* Register Address */ 1869 #define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */ 1870 #define AR5K_PHY_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode */ 1871 #define AR5K_PHY_TURBO_MIMO 0x00000004 /* Set turbo for mimo */ 1872 1873 /* 1874 * PHY agility command register 1875 * (aka TST_1) 1876 */ 1877 #define AR5K_PHY_AGC 0x9808 /* Register Address */ 1878 #define AR5K_PHY_TST1 0x9808 1879 #define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/ 1880 #define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */ 1881 #define AR5K_PHY_TST1_TXSRC_SRC 0x00000002 /* Used with bit 7 (?) */ 1882 #define AR5K_PHY_TST1_TXSRC_SRC_S 1 1883 #define AR5K_PHY_TST1_TXSRC_ALT 0x00000080 /* Set input to tsdac (?) */ 1884 #define AR5K_PHY_TST1_TXSRC_ALT_S 7 1885 1886 1887 /* 1888 * PHY timing register 3 [5112+] 1889 */ 1890 #define AR5K_PHY_TIMING_3 0x9814 1891 #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 1892 #define AR5K_PHY_TIMING_3_DSC_MAN_S 17 1893 #define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 1894 #define AR5K_PHY_TIMING_3_DSC_EXP_S 13 1895 1896 /* 1897 * PHY chip revision register 1898 */ 1899 #define AR5K_PHY_CHIP_ID 0x9818 1900 1901 /* 1902 * PHY activation register 1903 */ 1904 #define AR5K_PHY_ACT 0x981c /* Register Address */ 1905 #define AR5K_PHY_ACT_ENABLE 0x00000001 /* Activate PHY */ 1906 #define AR5K_PHY_ACT_DISABLE 0x00000002 /* Deactivate PHY */ 1907 1908 /* 1909 * PHY RF control registers 1910 */ 1911 #define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */ 1912 #define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* TX frame to TX data start */ 1913 #define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0 1914 1915 #define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */ 1916 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 /* TX end to XLNA on */ 1917 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8 1918 1919 #define AR5K_PHY_ADC_CTL 0x982c 1920 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003 1921 #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0 1922 #define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000 1923 #define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000 1924 #define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000 1925 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000 1926 #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16 1927 1928 #define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */ 1929 #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */ 1930 #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 /* TX frame to XPA B on (field) */ 1931 #define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 /* TX end to XPA A off (field) */ 1932 #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 /* TX end to XPA B off (field) */ 1933 1934 /* 1935 * Pre-Amplifier control register 1936 * (XPA -> external pre-amplifier) 1937 */ 1938 #define AR5K_PHY_PA_CTL 0x9838 /* Register Address */ 1939 #define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 /* XPA A high (?) */ 1940 #define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 /* XPA B high (?) */ 1941 #define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 /* Enable XPA A */ 1942 #define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */ 1943 1944 /* 1945 * PHY settling register 1946 */ 1947 #define AR5K_PHY_SETTLING 0x9844 /* Register Address */ 1948 #define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */ 1949 #define AR5K_PHY_SETTLING_AGC_S 0 1950 #define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settling time */ 1951 #define AR5K_PHY_SETTLING_SWITCH_S 7 1952 1953 /* 1954 * PHY Gain registers 1955 */ 1956 #define AR5K_PHY_GAIN 0x9848 /* Register Address */ 1957 #define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */ 1958 #define AR5K_PHY_GAIN_TXRX_ATTEN_S 12 1959 #define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000 1960 #define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18 1961 1962 #define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */ 1963 #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */ 1964 1965 /* 1966 * Desired ADC/PGA size register 1967 * (for more infos read ANI patent) 1968 */ 1969 #define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */ 1970 #define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* ADC desired size */ 1971 #define AR5K_PHY_DESIRED_SIZE_ADC_S 0 1972 #define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* PGA desired size */ 1973 #define AR5K_PHY_DESIRED_SIZE_PGA_S 8 1974 #define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Total desired size */ 1975 #define AR5K_PHY_DESIRED_SIZE_TOT_S 20 1976 1977 /* 1978 * PHY signal register 1979 * (for more infos read ANI patent) 1980 */ 1981 #define AR5K_PHY_SIG 0x9858 /* Register Address */ 1982 #define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* FIRSTEP */ 1983 #define AR5K_PHY_SIG_FIRSTEP_S 12 1984 #define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* FIPWR */ 1985 #define AR5K_PHY_SIG_FIRPWR_S 18 1986 1987 /* 1988 * PHY coarse agility control register 1989 * (for more infos read ANI patent) 1990 */ 1991 #define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */ 1992 #define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* AGC Coarse low */ 1993 #define AR5K_PHY_AGCCOARSE_LO_S 7 1994 #define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* AGC Coarse high */ 1995 #define AR5K_PHY_AGCCOARSE_HI_S 15 1996 1997 /* 1998 * PHY agility control register 1999 */ 2000 #define AR5K_PHY_AGCCTL 0x9860 /* Register address */ 2001 #define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */ 2002 #define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */ 2003 #define AR5K_PHY_AGCCTL_OFDM_DIV_DIS 0x00000008 /* Disable antenna diversity on OFDM modes */ 2004 #define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */ 2005 #define AR5K_PHY_AGCTL_FLTR_CAL 0x00010000 /* Allow filter calibration (?) */ 2006 #define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 /* Don't update nf automaticaly */ 2007 2008 /* 2009 * PHY noise floor status register (CCA = Clear Channel Assessment) 2010 */ 2011 #define AR5K_PHY_NF 0x9864 /* Register address */ 2012 #define AR5K_PHY_NF_M 0x000001ff /* Noise floor, written to hardware in 1/2 dBm units */ 2013 #define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) 2014 #define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */ 2015 #define AR5K_PHY_NF_THRESH62_S 12 2016 #define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000 /* Minimum measured noise level, read from hardware in 1 dBm units */ 2017 #define AR5K_PHY_NF_MINCCA_PWR_S 19 2018 2019 /* 2020 * PHY ADC saturation register [5110] 2021 */ 2022 #define AR5K_PHY_ADCSAT 0x9868 2023 #define AR5K_PHY_ADCSAT_ICNT 0x0001f800 2024 #define AR5K_PHY_ADCSAT_ICNT_S 11 2025 #define AR5K_PHY_ADCSAT_THR 0x000007e0 2026 #define AR5K_PHY_ADCSAT_THR_S 5 2027 2028 /* 2029 * PHY Weak ofdm signal detection threshold registers (ANI) [5212+] 2030 */ 2031 2032 /* High thresholds */ 2033 #define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868 2034 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f 2035 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0 2036 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000 2037 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17 2038 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000 2039 #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24 2040 2041 /* Low thresholds */ 2042 #define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c 2043 #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001 2044 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00 2045 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8 2046 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000 2047 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14 2048 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000 2049 #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21 2050 2051 2052 /* 2053 * PHY sleep registers [5112+] 2054 */ 2055 #define AR5K_PHY_SCR 0x9870 2056 2057 #define AR5K_PHY_SLMT 0x9874 2058 #define AR5K_PHY_SLMT_32MHZ 0x0000007f 2059 2060 #define AR5K_PHY_SCAL 0x9878 2061 #define AR5K_PHY_SCAL_32MHZ 0x0000000e 2062 #define AR5K_PHY_SCAL_32MHZ_5311 0x00000008 2063 #define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a 2064 #define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032 2065 2066 /* 2067 * PHY PLL (Phase Locked Loop) control register 2068 */ 2069 #define AR5K_PHY_PLL 0x987c 2070 #define AR5K_PHY_PLL_20MHZ 0x00000013 /* For half rate (?) */ 2071 /* 40MHz -> 5GHz band */ 2072 #define AR5K_PHY_PLL_40MHZ_5211 0x00000018 2073 #define AR5K_PHY_PLL_40MHZ_5212 0x000000aa 2074 #define AR5K_PHY_PLL_40MHZ_5413 0x00000004 2075 #define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \ 2076 AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) 2077 /* 44MHz -> 2.4GHz band */ 2078 #define AR5K_PHY_PLL_44MHZ_5211 0x00000019 2079 #define AR5K_PHY_PLL_44MHZ_5212 0x000000ab 2080 #define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \ 2081 AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) 2082 2083 #define AR5K_PHY_PLL_RF5111 0x00000000 2084 #define AR5K_PHY_PLL_RF5112 0x00000040 2085 #define AR5K_PHY_PLL_HALF_RATE 0x00000100 2086 #define AR5K_PHY_PLL_QUARTER_RATE 0x00000200 2087 2088 /* 2089 * RF Buffer register 2090 * 2091 * It's obvious from the code that 0x989c is the buffer register but 2092 * for the other special registers that we write to after sending each 2093 * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers 2094 * for now. It's interesting that they are also used for some other operations. 2095 */ 2096 2097 #define AR5K_RF_BUFFER 0x989c 2098 #define AR5K_RF_BUFFER_CONTROL_0 0x98c0 /* Channel on 5110 */ 2099 #define AR5K_RF_BUFFER_CONTROL_1 0x98c4 /* Bank 7 on 5112 */ 2100 #define AR5K_RF_BUFFER_CONTROL_2 0x98cc /* Bank 7 on 5111 */ 2101 2102 #define AR5K_RF_BUFFER_CONTROL_3 0x98d0 /* Bank 2 on 5112 */ 2103 /* Channel set on 5111 */ 2104 /* Used to read radio revision*/ 2105 2106 #define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* RF Stage register on 5110 */ 2107 /* Bank 0,1,2,6 on 5111 */ 2108 /* Bank 1 on 5112 */ 2109 /* Used during activation on 5111 */ 2110 2111 #define AR5K_RF_BUFFER_CONTROL_5 0x98d8 /* Bank 3 on 5111 */ 2112 /* Used during activation on 5111 */ 2113 /* Channel on 5112 */ 2114 /* Bank 6 on 5112 */ 2115 2116 #define AR5K_RF_BUFFER_CONTROL_6 0x98dc /* Bank 3 on 5112 */ 2117 2118 /* 2119 * PHY RF stage register [5210] 2120 */ 2121 #define AR5K_PHY_RFSTG 0x98d4 2122 #define AR5K_PHY_RFSTG_DISABLE 0x00000021 2123 2124 /* 2125 * BIN masks (?) 2126 */ 2127 #define AR5K_PHY_BIN_MASK_1 0x9900 2128 #define AR5K_PHY_BIN_MASK_2 0x9904 2129 #define AR5K_PHY_BIN_MASK_3 0x9908 2130 2131 #define AR5K_PHY_BIN_MASK_CTL 0x990c 2132 #define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff 2133 #define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0 2134 #define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000 2135 #define AR5K_PHY_BIN_MASK_CTL_RATE_S 24 2136 2137 /* 2138 * PHY Antenna control register 2139 */ 2140 #define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */ 2141 #define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */ 2142 #define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */ 2143 #define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */ 2144 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 /* Switch table idle (?) */ 2145 #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4 2146 2147 /* 2148 * PHY receiver delay register [5111+] 2149 */ 2150 #define AR5K_PHY_RX_DELAY 0x9914 /* Register Address */ 2151 #define AR5K_PHY_RX_DELAY_M 0x00003fff /* Mask for RX activate to receive delay (/100ns) */ 2152 2153 /* 2154 * PHY max rx length register (?) [5111] 2155 */ 2156 #define AR5K_PHY_MAX_RX_LEN 0x991c 2157 2158 /* 2159 * PHY timing register 4 2160 * I(nphase)/Q(adrature) calibration register [5111+] 2161 */ 2162 #define AR5K_PHY_IQ 0x9920 /* Register Address */ 2163 #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ 2164 #define AR5K_PHY_IQ_CORR_Q_Q_COFF_S 0 2165 #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ 2166 #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 2167 #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ 2168 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */ 2169 #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 2170 #define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */ 2171 #define AR5K_PHY_IQ_USE_PT_DF 0x00020000 /* Use pilot track df (?) */ 2172 #define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 /* Early trigger threshold (?) (field) */ 2173 #define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 /* Enable pilot mask (?) */ 2174 #define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 /* Enable channel mask (?) */ 2175 #define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 /* Enable spur filter */ 2176 #define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 /* Enable spur rssi */ 2177 2178 /* 2179 * PHY timing register 5 2180 * OFDM Self-correlator Cyclic RSSI threshold params 2181 * (Check out bb_cycpwr_thr1 on ANI patent) 2182 */ 2183 #define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */ 2184 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */ 2185 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */ 2186 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1 2187 #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */ 2188 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */ 2189 #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */ 2190 #define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000 /* Long sc threshold hi rssi (?) */ 2191 2192 /* 2193 * PHY-only warm reset register 2194 */ 2195 #define AR5K_PHY_WARM_RESET 0x9928 2196 2197 /* 2198 * PHY-only control register 2199 */ 2200 #define AR5K_PHY_CTL 0x992c /* Register Address */ 2201 #define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 /* RX drain rate (?) */ 2202 #define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 /* Late tx signal symbol (?) */ 2203 #define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 /* Generate scrambler */ 2204 #define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008 /* TX antenna select */ 2205 #define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 /* Static TX antenna */ 2206 #define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020 /* RX antenna select */ 2207 #define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 /* Static RX antenna */ 2208 #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */ 2209 2210 /* 2211 * PHY PAPD probe register [5111+] 2212 */ 2213 #define AR5K_PHY_PAPD_PROBE 0x9930 2214 #define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001 2215 #define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002 2216 #define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040 2217 #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 2218 #define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 2219 #define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 2220 #define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000 2221 #define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ 2222 #define AR5K_PHY_PAPD_PROBE_TYPE_S 23 2223 #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 2224 #define AR5K_PHY_PAPD_PROBE_TYPE_XR 1 2225 #define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2 2226 #define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 2227 #define AR5K_PHY_PAPD_PROBE_GAINF_S 25 2228 #define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */ 2229 #define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */ 2230 2231 /* 2232 * PHY TX rate power registers [5112+] 2233 */ 2234 #define AR5K_PHY_TXPOWER_RATE1 0x9934 2235 #define AR5K_PHY_TXPOWER_RATE2 0x9938 2236 #define AR5K_PHY_TXPOWER_RATE_MAX 0x993c 2237 #define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040 2238 #define AR5K_PHY_TXPOWER_RATE3 0xa234 2239 #define AR5K_PHY_TXPOWER_RATE4 0xa238 2240 2241 /* 2242 * PHY frame control register [5111+] 2243 */ 2244 #define AR5K_PHY_FRAME_CTL_5210 0x9804 2245 #define AR5K_PHY_FRAME_CTL_5211 0x9944 2246 #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ 2247 AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) 2248 /*---[5111+]---*/ 2249 #define AR5K_PHY_FRAME_CTL_WIN_LEN 0x00000003 /* Force window length (?) */ 2250 #define AR5K_PHY_FRAME_CTL_WIN_LEN_S 0 2251 #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */ 2252 #define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 2253 #define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */ 2254 #define AR5K_PHY_FRAME_CTL_EMU 0x80000000 2255 #define AR5K_PHY_FRAME_CTL_EMU_S 31 2256 /*---[5110/5111]---*/ 2257 #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */ 2258 #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */ 2259 #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* Illegal rate */ 2260 #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* Illegal length */ 2261 #define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 2262 #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */ 2263 #define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ 2264 AR5K_PHY_FRAME_CTL_TXURN_ERR | \ 2265 AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ 2266 AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ 2267 AR5K_PHY_FRAME_CTL_PARITY_ERR | \ 2268 AR5K_PHY_FRAME_CTL_TIMING_ERR 2269 2270 /* 2271 * PHY Tx Power adjustment register [5212A+] 2272 */ 2273 #define AR5K_PHY_TX_PWR_ADJ 0x994c 2274 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0 2275 #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6 2276 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000 2277 #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18 2278 2279 /* 2280 * PHY radar detection register [5111+] 2281 */ 2282 #define AR5K_PHY_RADAR 0x9954 2283 #define AR5K_PHY_RADAR_ENABLE 0x00000001 2284 #define AR5K_PHY_RADAR_DISABLE 0x00000000 2285 #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold 2286 5-bits, units unknown {0..31} 2287 (? MHz ?) */ 2288 #define AR5K_PHY_RADAR_INBANDTHR_S 1 2289 2290 #define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold 2291 6-bits, dBm range {0..63} 2292 in dBm units. */ 2293 #define AR5K_PHY_RADAR_PRSSI_THR_S 6 2294 2295 #define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold 2296 6-bits, dBm range {0..63} 2297 in dBm units. */ 2298 #define AR5K_PHY_RADAR_PHEIGHT_THR_S 12 2299 2300 #define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold. 2301 6-bits, dBm range {0..63} 2302 in dBm units. */ 2303 #define AR5K_PHY_RADAR_RSSI_THR_S 18 2304 2305 #define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 /* Finite Impulse Response 2306 filter power out threshold. 2307 7-bits, standard power range 2308 {0..127} in 1/2 dBm units. */ 2309 #define AR5K_PHY_RADAR_FIRPWR_THRS 24 2310 2311 /* 2312 * PHY antenna switch table registers 2313 */ 2314 #define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 2315 #define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 2316 2317 /* 2318 * PHY Noise floor threshold 2319 */ 2320 #define AR5K_PHY_NFTHRES 0x9968 2321 2322 /* 2323 * Sigma Delta register (?) [5213] 2324 */ 2325 #define AR5K_PHY_SIGMA_DELTA 0x996C 2326 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 2327 #define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0 2328 #define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8 2329 #define AR5K_PHY_SIGMA_DELTA_FILT2_S 3 2330 #define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00 2331 #define AR5K_PHY_SIGMA_DELTA_FILT1_S 8 2332 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000 2333 #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13 2334 2335 /* 2336 * RF restart register [5112+] (?) 2337 */ 2338 #define AR5K_PHY_RESTART 0x9970 /* restart */ 2339 #define AR5K_PHY_RESTART_DIV_GC 0x001c0000 /* Fast diversity gc_limit (?) */ 2340 #define AR5K_PHY_RESTART_DIV_GC_S 18 2341 2342 /* 2343 * RF Bus access request register (for synth-oly channel switching) 2344 */ 2345 #define AR5K_PHY_RFBUS_REQ 0x997C 2346 #define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001 2347 2348 /* 2349 * Spur mitigation masks (?) 2350 */ 2351 #define AR5K_PHY_TIMING_7 0x9980 2352 #define AR5K_PHY_TIMING_8 0x9984 2353 #define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff 2354 #define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0 2355 2356 #define AR5K_PHY_BIN_MASK2_1 0x9988 2357 #define AR5K_PHY_BIN_MASK2_2 0x998c 2358 #define AR5K_PHY_BIN_MASK2_3 0x9990 2359 2360 #define AR5K_PHY_BIN_MASK2_4 0x9994 2361 #define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff 2362 #define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0 2363 2364 #define AR5K_PHY_TIMING_9 0x9998 2365 #define AR5K_PHY_TIMING_10 0x999c 2366 #define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff 2367 #define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0 2368 2369 /* 2370 * Spur mitigation control 2371 */ 2372 #define AR5K_PHY_TIMING_11 0x99a0 /* Register address */ 2373 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */ 2374 #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0 2375 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */ 2376 #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20 2377 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */ 2378 #define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */ 2379 2380 /* 2381 * Gain tables 2382 */ 2383 #define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ 2384 #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) 2385 #define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ 2386 #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) 2387 2388 /* 2389 * PHY timing IQ calibration result register [5111+] 2390 */ 2391 #define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */ 2392 #define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */ 2393 #define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */ 2394 2395 /* 2396 * PHY current RSSI register [5111+] 2397 */ 2398 #define AR5K_PHY_CURRENT_RSSI 0x9c1c 2399 2400 /* 2401 * PHY RF Bus grant register 2402 */ 2403 #define AR5K_PHY_RFBUS_GRANT 0x9c20 2404 #define AR5K_PHY_RFBUS_GRANT_OK 0x00000001 2405 2406 /* 2407 * PHY ADC test register 2408 */ 2409 #define AR5K_PHY_ADC_TEST 0x9c24 2410 #define AR5K_PHY_ADC_TEST_I 0x00000001 2411 #define AR5K_PHY_ADC_TEST_Q 0x00000200 2412 2413 /* 2414 * PHY DAC test register 2415 */ 2416 #define AR5K_PHY_DAC_TEST 0x9c28 2417 #define AR5K_PHY_DAC_TEST_I 0x00000001 2418 #define AR5K_PHY_DAC_TEST_Q 0x00000200 2419 2420 /* 2421 * PHY PTAT register (?) 2422 */ 2423 #define AR5K_PHY_PTAT 0x9c2c 2424 2425 /* 2426 * PHY Illegal TX rate register [5112+] 2427 */ 2428 #define AR5K_PHY_BAD_TX_RATE 0x9c30 2429 2430 /* 2431 * PHY SPUR Power register [5112+] 2432 */ 2433 #define AR5K_PHY_SPUR_PWR 0x9c34 /* Register Address */ 2434 #define AR5K_PHY_SPUR_PWR_I 0x00000001 /* SPUR Power estimate for I (field) */ 2435 #define AR5K_PHY_SPUR_PWR_Q 0x00000100 /* SPUR Power estimate for Q (field) */ 2436 #define AR5K_PHY_SPUR_PWR_FILT 0x00010000 /* Power with SPUR removed (field) */ 2437 2438 /* 2439 * PHY Channel status register [5112+] (?) 2440 */ 2441 #define AR5K_PHY_CHAN_STATUS 0x9c38 2442 #define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001 2443 #define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002 2444 #define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004 2445 #define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008 2446 2447 /* 2448 * Heavy clip enable register 2449 */ 2450 #define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0 2451 2452 /* 2453 * PHY clock sleep registers [5112+] 2454 */ 2455 #define AR5K_PHY_SCLOCK 0x99f0 2456 #define AR5K_PHY_SCLOCK_32MHZ 0x0000000c 2457 #define AR5K_PHY_SDELAY 0x99f4 2458 #define AR5K_PHY_SDELAY_32MHZ 0x000000ff 2459 #define AR5K_PHY_SPENDING 0x99f8 2460 2461 2462 /* 2463 * PHY PAPD I (power?) table (?) 2464 * (92! entries) 2465 */ 2466 #define AR5K_PHY_PAPD_I_BASE 0xa000 2467 #define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2)) 2468 2469 /* 2470 * PHY PCDAC TX power table 2471 */ 2472 #define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 2473 #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) 2474 2475 /* 2476 * PHY mode register [5111+] 2477 */ 2478 #define AR5K_PHY_MODE 0x0a200 /* Register Address */ 2479 #define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation bit */ 2480 #define AR5K_PHY_MODE_MOD_OFDM 0 2481 #define AR5K_PHY_MODE_MOD_CCK 1 2482 #define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode bit */ 2483 #define AR5K_PHY_MODE_FREQ_5GHZ 0 2484 #define AR5K_PHY_MODE_FREQ_2GHZ 2 2485 #define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Enable Dynamic OFDM/CCK mode [5112+] */ 2486 #define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */ 2487 #define AR5K_PHY_MODE_RAD_RF5111 0 2488 #define AR5K_PHY_MODE_RAD_RF5112 8 2489 #define AR5K_PHY_MODE_XR 0x00000010 /* Enable XR mode [5112+] */ 2490 #define AR5K_PHY_MODE_HALF_RATE 0x00000020 /* Enable Half rate (test) */ 2491 #define AR5K_PHY_MODE_QUARTER_RATE 0x00000040 /* Enable Quarter rat (test) */ 2492 2493 /* 2494 * PHY CCK transmit control register [5111+ (?)] 2495 */ 2496 #define AR5K_PHY_CCKTXCTL 0xa204 2497 #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 2498 #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 2499 #define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001 2500 #define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004 2501 2502 /* 2503 * PHY CCK Cross-correlator Barker RSSI threshold register [5212+] 2504 */ 2505 #define AR5K_PHY_CCK_CROSSCORR 0xa208 2506 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000003f 2507 #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0 2508 2509 /* Same address is used for antenna diversity activation */ 2510 #define AR5K_PHY_FAST_ANT_DIV 0xa208 2511 #define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000 2512 2513 /* 2514 * PHY 2GHz gain register [5111+] 2515 */ 2516 #define AR5K_PHY_GAIN_2GHZ 0xa20c 2517 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 2518 #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 2519 #define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c 2520 2521 #define AR5K_PHY_CCK_RX_CTL_4 0xa21c 2522 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000 2523 #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19 2524 2525 #define AR5K_PHY_DAG_CCK_CTL 0xa228 2526 #define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200 2527 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00 2528 #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10 2529 2530 #define AR5K_PHY_FAST_ADC 0xa24c 2531 2532 #define AR5K_PHY_BLUETOOTH 0xa254 2533 2534 /* 2535 * Transmit Power Control register 2536 * [2413+] 2537 */ 2538 #define AR5K_PHY_TPC_RG1 0xa258 2539 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000 2540 #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14 2541 #define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000 2542 #define AR5K_PHY_TPC_RG1_PDGAIN_1_S 16 2543 #define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000 2544 #define AR5K_PHY_TPC_RG1_PDGAIN_2_S 18 2545 #define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000 2546 #define AR5K_PHY_TPC_RG1_PDGAIN_3_S 20 2547 2548 #define AR5K_PHY_TPC_RG5 0xa26C 2549 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F 2550 #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0 2551 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0 2552 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4 2553 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00 2554 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10 2555 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000 2556 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16 2557 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000 2558 #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22 2559 2560 /* 2561 * PHY PDADC Tx power table 2562 */ 2563 #define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280 2564 #define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2)) 2565 2566 /* 2567 * Platform registers for WiSoC 2568 */ 2569 #define AR5K_AR5312_RESET 0xbc003020 2570 #define AR5K_AR5312_RESET_BB0_COLD 0x00000004 2571 #define AR5K_AR5312_RESET_BB1_COLD 0x00000200 2572 #define AR5K_AR5312_RESET_WMAC0 0x00002000 2573 #define AR5K_AR5312_RESET_BB0_WARM 0x00004000 2574 #define AR5K_AR5312_RESET_WMAC1 0x00020000 2575 #define AR5K_AR5312_RESET_BB1_WARM 0x00040000 2576 2577 #define AR5K_AR5312_ENABLE 0xbc003080 2578 #define AR5K_AR5312_ENABLE_WLAN0 0x00000001 2579 #define AR5K_AR5312_ENABLE_WLAN1 0x00000008 2580 2581 #define AR5K_AR2315_RESET 0xb1000004 2582 #define AR5K_AR2315_RESET_WMAC 0x00000001 2583 #define AR5K_AR2315_RESET_BB_WARM 0x00000002 2584 2585 #define AR5K_AR2315_AHB_ARB_CTL 0xb1000008 2586 #define AR5K_AR2315_AHB_ARB_CTL_WLAN 0x00000002 2587 2588 #define AR5K_AR2315_BYTESWAP 0xb100000c 2589 #define AR5K_AR2315_BYTESWAP_WMAC 0x00000002 2590