pcu.c (c9494727cf293ae2ec66af57547a3e79c724fec2) pcu.c (2111ac0d888767999c7dd6d1309dcc1fb8012022)
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8 *

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34/*******************\
35* Generic functions *
36\*******************/
37
38/**
39 * ath5k_hw_set_opmode - Set PCU operating mode
40 *
41 * @ah: The &struct ath5k_hw
1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8 *

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34/*******************\
35* Generic functions *
36\*******************/
37
38/**
39 * ath5k_hw_set_opmode - Set PCU operating mode
40 *
41 * @ah: The &struct ath5k_hw
42 * @op_mode: &enum nl80211_iftype operating mode
42 *
43 * Initialize PCU for the various operating modes (AP/STA etc)
43 *
44 * Initialize PCU for the various operating modes (AP/STA etc)
44 *
45 * NOTE: ah->ah_op_mode must be set before calling this.
46 */
45 */
47int ath5k_hw_set_opmode(struct ath5k_hw *ah)
46int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
48{
49 struct ath_common *common = ath5k_hw_common(ah);
50 u32 pcu_reg, beacon_reg, low_id, high_id;
51
47{
48 struct ath_common *common = ath5k_hw_common(ah);
49 u32 pcu_reg, beacon_reg, low_id, high_id;
50
51 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
52
53 /* Preserve rest settings */
54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
55 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
56 | AR5K_STA_ID1_KEYSRCH_MODE
57 | (ah->ah_version == AR5K_AR5210 ?
58 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
59
60 beacon_reg = 0;
61
62 ATH5K_TRACE(ah->ah_sc);
63
52
53 /* Preserve rest settings */
54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
55 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
56 | AR5K_STA_ID1_KEYSRCH_MODE
57 | (ah->ah_version == AR5K_AR5210 ?
58 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
59
60 beacon_reg = 0;
61
62 ATH5K_TRACE(ah->ah_sc);
63
64 switch (ah->ah_op_mode) {
64 switch (op_mode) {
65 case NL80211_IFTYPE_ADHOC:
66 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
67 beacon_reg |= AR5K_BCR_ADHOC;
68 if (ah->ah_version == AR5K_AR5210)
69 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
70 else
71 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
72 break;

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108 */
109 if (ah->ah_version == AR5K_AR5210)
110 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
111
112 return 0;
113}
114
115/**
65 case NL80211_IFTYPE_ADHOC:
66 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
67 beacon_reg |= AR5K_BCR_ADHOC;
68 if (ah->ah_version == AR5K_AR5210)
69 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
70 else
71 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
72 break;

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108 */
109 if (ah->ah_version == AR5K_AR5210)
110 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
111
112 return 0;
113}
114
115/**
116 * ath5k_hw_update - Update mib counters (mac layer statistics)
116 * ath5k_hw_update - Update MIB counters (mac layer statistics)
117 *
118 * @ah: The &struct ath5k_hw
117 *
118 * @ah: The &struct ath5k_hw
119 * @stats: The &struct ieee80211_low_level_stats we use to track
120 * statistics on the driver
121 *
119 *
122 * Reads MIB counters from PCU and updates sw statistics. Must be
123 * called after a MIB interrupt.
120 * Reads MIB counters from PCU and updates sw statistics. Is called after a
121 * MIB interrupt, because one of these counters might have reached their maximum
122 * and triggered the MIB interrupt, to let us read and clear the counter.
123 *
124 * Is called in interrupt context!
124 */
125 */
125void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
126 struct ieee80211_low_level_stats *stats)
126void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
127{
127{
128 ATH5K_TRACE(ah->ah_sc);
128 struct ath5k_statistics *stats = &ah->ah_sc->stats;
129
130 /* Read-And-Clear */
129
130 /* Read-And-Clear */
131 stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
132 stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
133 stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
134 stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
135
136 /* XXX: Should we use this to track beacon count ?
137 * -we read it anyway to clear the register */
138 ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
139
140 /* Reset profile count registers on 5212*/
141 if (ah->ah_version == AR5K_AR5212) {
142 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
143 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
144 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
145 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
146 }
147
148 /* TODO: Handle ANI stats */
131 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
132 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
133 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
134 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
135 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
149}
150
151/**
152 * ath5k_hw_set_ack_bitrate - set bitrate for ACKs
153 *
154 * @ah: The &struct ath5k_hw
155 * @high: Flag to determine if we want to use high transmition rate
156 * for ACKs or not

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174}
175
176
177/******************\
178* ACK/CTS Timeouts *
179\******************/
180
181/**
136}
137
138/**
139 * ath5k_hw_set_ack_bitrate - set bitrate for ACKs
140 *
141 * @ah: The &struct ath5k_hw
142 * @high: Flag to determine if we want to use high transmition rate
143 * for ACKs or not

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161}
162
163
164/******************\
165* ACK/CTS Timeouts *
166\******************/
167
168/**
182 * ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec
183 *
184 * @ah: The &struct ath5k_hw
185 */
186unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
187{
188 ATH5K_TRACE(ah->ah_sc);
189
190 return ath5k_hw_clocktoh(ah, AR5K_REG_MS(ath5k_hw_reg_read(ah,
191 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK));
192}
193
194/**
195 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
196 *
197 * @ah: The &struct ath5k_hw
198 * @timeout: Timeout in usec
199 */
169 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
170 *
171 * @ah: The &struct ath5k_hw
172 * @timeout: Timeout in usec
173 */
200int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
174static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
201{
202 ATH5K_TRACE(ah->ah_sc);
203 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
204 <= timeout)
205 return -EINVAL;
206
207 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
208 ath5k_hw_htoclock(ah, timeout));
209
210 return 0;
211}
212
213/**
175{
176 ATH5K_TRACE(ah->ah_sc);
177 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
178 <= timeout)
179 return -EINVAL;
180
181 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
182 ath5k_hw_htoclock(ah, timeout));
183
184 return 0;
185}
186
187/**
214 * ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec
215 *
216 * @ah: The &struct ath5k_hw
217 */
218unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
219{
220 ATH5K_TRACE(ah->ah_sc);
221 return ath5k_hw_clocktoh(ah, AR5K_REG_MS(ath5k_hw_reg_read(ah,
222 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS));
223}
224
225/**
226 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
227 *
228 * @ah: The &struct ath5k_hw
229 * @timeout: Timeout in usec
230 */
188 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
189 *
190 * @ah: The &struct ath5k_hw
191 * @timeout: Timeout in usec
192 */
231int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
193static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
232{
233 ATH5K_TRACE(ah->ah_sc);
234 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
235 <= timeout)
236 return -EINVAL;
237
238 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
239 ath5k_hw_htoclock(ah, timeout));

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285 return clock;
286}
287
288/**
289 * ath5k_hw_get_default_slottime - Get the default slot time for current mode
290 *
291 * @ah: The &struct ath5k_hw
292 */
194{
195 ATH5K_TRACE(ah->ah_sc);
196 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
197 <= timeout)
198 return -EINVAL;
199
200 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
201 ath5k_hw_htoclock(ah, timeout));

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247 return clock;
248}
249
250/**
251 * ath5k_hw_get_default_slottime - Get the default slot time for current mode
252 *
253 * @ah: The &struct ath5k_hw
254 */
293unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
255static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
294{
295 struct ieee80211_channel *channel = ah->ah_current_channel;
296
297 if (channel->hw_value & CHANNEL_TURBO)
298 return 6; /* both turbo modes */
299
300 if (channel->hw_value & CHANNEL_CCK)
301 return 20; /* 802.11b */
302
303 return 9; /* 802.11 a/g */
304}
305
306/**
307 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
308 *
309 * @ah: The &struct ath5k_hw
310 */
256{
257 struct ieee80211_channel *channel = ah->ah_current_channel;
258
259 if (channel->hw_value & CHANNEL_TURBO)
260 return 6; /* both turbo modes */
261
262 if (channel->hw_value & CHANNEL_CCK)
263 return 20; /* 802.11b */
264
265 return 9; /* 802.11 a/g */
266}
267
268/**
269 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
270 *
271 * @ah: The &struct ath5k_hw
272 */
311unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
273static unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
312{
313 struct ieee80211_channel *channel = ah->ah_current_channel;
314
315 if (channel->hw_value & CHANNEL_TURBO)
316 return 8; /* both turbo modes */
317
318 if (channel->hw_value & CHANNEL_5GHZ)
319 return 16; /* 802.11a */

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412 * ath5k_hw_start_rx_pcu - Start RX engine
413 *
414 * @ah: The &struct ath5k_hw
415 *
416 * Starts RX engine on PCU so that hw can process RXed frames
417 * (ACK etc).
418 *
419 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
274{
275 struct ieee80211_channel *channel = ah->ah_current_channel;
276
277 if (channel->hw_value & CHANNEL_TURBO)
278 return 8; /* both turbo modes */
279
280 if (channel->hw_value & CHANNEL_5GHZ)
281 return 16; /* 802.11a */

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374 * ath5k_hw_start_rx_pcu - Start RX engine
375 *
376 * @ah: The &struct ath5k_hw
377 *
378 * Starts RX engine on PCU so that hw can process RXed frames
379 * (ACK etc).
380 *
381 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
420 * TODO: Init ANI here
421 */
422void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
423{
424 ATH5K_TRACE(ah->ah_sc);
425 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
426}
427
428/**

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446void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
447{
448 ATH5K_TRACE(ah->ah_sc);
449 /* Set the multicat filter */
450 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
451 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
452}
453
382 */
383void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
384{
385 ATH5K_TRACE(ah->ah_sc);
386 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
387}
388
389/**

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407void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
408{
409 ATH5K_TRACE(ah->ah_sc);
410 /* Set the multicat filter */
411 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
412 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
413}
414
454/*
455 * Set multicast filter by index
456 */
457int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
458{
459
460 ATH5K_TRACE(ah->ah_sc);
461 if (index >= 64)
462 return -EINVAL;
463 else if (index >= 32)
464 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
465 (1 << (index - 32)));
466 else
467 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
468
469 return 0;
470}
471
472/*
473 * Clear Multicast filter by index
474 */
475int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
476{
477
478 ATH5K_TRACE(ah->ah_sc);
479 if (index >= 64)
480 return -EINVAL;
481 else if (index >= 32)
482 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
483 (1 << (index - 32)));
484 else
485 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
486
487 return 0;
488}
489
490/**
491 * ath5k_hw_get_rx_filter - Get current rx filter
492 *
493 * @ah: The &struct ath5k_hw
494 *
495 * Returns the RX filter by reading rx filter and
496 * phy error filter registers. RX filter is used
497 * to set the allowed frame types that PCU will accept

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567}
568
569
570/****************\
571* Beacon control *
572\****************/
573
574/**
415/**
416 * ath5k_hw_get_rx_filter - Get current rx filter
417 *
418 * @ah: The &struct ath5k_hw
419 *
420 * Returns the RX filter by reading rx filter and
421 * phy error filter registers. RX filter is used
422 * to set the allowed frame types that PCU will accept

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492}
493
494
495/****************\
496* Beacon control *
497\****************/
498
499/**
575 * ath5k_hw_get_tsf32 - Get a 32bit TSF
576 *
577 * @ah: The &struct ath5k_hw
578 *
579 * Returns lower 32 bits of current TSF
580 */
581u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
582{
583 ATH5K_TRACE(ah->ah_sc);
584 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
585}
586
587/**
588 * ath5k_hw_get_tsf64 - Get the full 64bit TSF
589 *
590 * @ah: The &struct ath5k_hw
591 *
592 * Returns the current TSF
593 */
594u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
595{

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646void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
647{
648 u32 timer1, timer2, timer3;
649
650 ATH5K_TRACE(ah->ah_sc);
651 /*
652 * Set the additional timers by mode
653 */
500 * ath5k_hw_get_tsf64 - Get the full 64bit TSF
501 *
502 * @ah: The &struct ath5k_hw
503 *
504 * Returns the current TSF
505 */
506u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
507{

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558void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
559{
560 u32 timer1, timer2, timer3;
561
562 ATH5K_TRACE(ah->ah_sc);
563 /*
564 * Set the additional timers by mode
565 */
654 switch (ah->ah_op_mode) {
566 switch (ah->ah_sc->opmode) {
655 case NL80211_IFTYPE_MONITOR:
656 case NL80211_IFTYPE_STATION:
657 /* In STA mode timer1 is used as next wakeup
658 * timer and timer2 as next CFP duration start
659 * timer. Both in 1/8TUs. */
660 /* TODO: PCF handling */
661 if (ah->ah_version == AR5K_AR5210) {
662 timer1 = 0xffffffff;

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683 * a zero length window is not allowed because
684 * we 'll get no beacons */
685 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
686
687 /*
688 * Set the beacon register and enable all timers.
689 */
690 /* When in AP or Mesh Point mode zero timer0 to start TSF */
567 case NL80211_IFTYPE_MONITOR:
568 case NL80211_IFTYPE_STATION:
569 /* In STA mode timer1 is used as next wakeup
570 * timer and timer2 as next CFP duration start
571 * timer. Both in 1/8TUs. */
572 /* TODO: PCF handling */
573 if (ah->ah_version == AR5K_AR5210) {
574 timer1 = 0xffffffff;

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595 * a zero length window is not allowed because
596 * we 'll get no beacons */
597 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
598
599 /*
600 * Set the beacon register and enable all timers.
601 */
602 /* When in AP or Mesh Point mode zero timer0 to start TSF */
691 if (ah->ah_op_mode == NL80211_IFTYPE_AP ||
692 ah->ah_op_mode == NL80211_IFTYPE_MESH_POINT)
603 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP ||
604 ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT)
693 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
694
695 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
696 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
697 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
698 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
699
700 /* Force a TSF reset if requested and enable beacons */

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717
718 /* TODO: Set enchanced sleep registers on AR5212
719 * based on vif->bss_conf params, until then
720 * disable power save reporting.*/
721 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
722
723}
724
605 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
606
607 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
608 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
609 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
610 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
611
612 /* Force a TSF reset if requested and enable beacons */

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629
630 /* TODO: Set enchanced sleep registers on AR5212
631 * based on vif->bss_conf params, until then
632 * disable power save reporting.*/
633 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
634
635}
636
725#if 0
726/*
727 * Set beacon timers
728 */
729int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
730 const struct ath5k_beacon_state *state)
731{
732 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
733
637
734 /*
735 * TODO: should be changed through *state
736 * review struct ath5k_beacon_state struct
737 *
738 * XXX: These are used for cfp period bellow, are they
739 * ok ? Is it O.K. for tsf here to be 0 or should we use
740 * get_tsf ?
741 */
742 u32 dtim_count = 0; /* XXX */
743 u32 cfp_count = 0; /* XXX */
744 u32 tsf = 0; /* XXX */
745
746 ATH5K_TRACE(ah->ah_sc);
747 /* Return on an invalid beacon state */
748 if (state->bs_interval < 1)
749 return -EINVAL;
750
751 interval = state->bs_interval;
752 dtim = state->bs_dtim_period;
753
754 /*
755 * PCF support?
756 */
757 if (state->bs_cfp_period > 0) {
758 /*
759 * Enable PCF mode and set the CFP
760 * (Contention Free Period) and timer registers
761 */
762 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
763 state->bs_interval;
764 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
765 state->bs_interval;
766
767 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
768 AR5K_STA_ID1_DEFAULT_ANTENNA |
769 AR5K_STA_ID1_PCF);
770 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
771 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
772 AR5K_CFP_DUR);
773 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
774 next_cfp)) << 3, AR5K_TIMER2);
775 } else {
776 /* Disable PCF mode */
777 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
778 AR5K_STA_ID1_DEFAULT_ANTENNA |
779 AR5K_STA_ID1_PCF);
780 }
781
782 /*
783 * Enable the beacon timer register
784 */
785 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
786
787 /*
788 * Start the beacon timers
789 */
790 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &
791 ~(AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
792 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
793 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
794 AR5K_BEACON_PERIOD), AR5K_BEACON);
795
796 /*
797 * Write new beacon miss threshold, if it appears to be valid
798 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
799 * and return if its not in range. We can test this by reading value and
800 * setting value to a largest value and seeing which values register.
801 */
802
803 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
804 state->bs_bmiss_threshold);
805
806 /*
807 * Set sleep control register
808 * XXX: Didn't find this in 5210 code but since this register
809 * exists also in ar5k's 5210 headers i leave it as common code.
810 */
811 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
812 (state->bs_sleep_duration - 3) << 3);
813
814 /*
815 * Set enhanced sleep registers on 5212
816 */
817 if (ah->ah_version == AR5K_AR5212) {
818 if (state->bs_sleep_duration > state->bs_interval &&
819 roundup(state->bs_sleep_duration, interval) ==
820 state->bs_sleep_duration)
821 interval = state->bs_sleep_duration;
822
823 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
824 roundup(state->bs_sleep_duration, dtim) ==
825 state->bs_sleep_duration))
826 dtim = state->bs_sleep_duration;
827
828 if (interval > dtim)
829 return -EINVAL;
830
831 next_beacon = interval == dtim ? state->bs_next_dtim :
832 state->bs_next_beacon;
833
834 ath5k_hw_reg_write(ah,
835 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
836 AR5K_SLEEP0_NEXT_DTIM) |
837 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
838 AR5K_SLEEP0_ENH_SLEEP_EN |
839 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
840
841 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
842 AR5K_SLEEP1_NEXT_TIM) |
843 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
844
845 ath5k_hw_reg_write(ah,
846 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
847 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
848 }
849
850 return 0;
851}
852
853/*
854 * Reset beacon timers
855 */
856void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
857{
858 ATH5K_TRACE(ah->ah_sc);
859 /*
860 * Disable beacon timer
861 */
862 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
863
864 /*
865 * Disable some beacon register values
866 */
867 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
868 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
869 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
870}
871
872/*
873 * Wait for beacon queue to finish
874 */
875int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
876{
877 unsigned int i;
878 int ret;
879
880 ATH5K_TRACE(ah->ah_sc);
881
882 /* 5210 doesn't have QCU*/
883 if (ah->ah_version == AR5K_AR5210) {
884 /*
885 * Wait for beaconn queue to finish by checking
886 * Control Register and Beacon Status Register.
887 */
888 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
889 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
890 ||
891 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
892 break;
893 udelay(10);
894 }
895
896 /* Timeout... */
897 if (i <= 0) {
898 /*
899 * Re-schedule the beacon queue
900 */
901 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
902 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
903 AR5K_BCR);
904
905 return -EIO;
906 }
907 ret = 0;
908 } else {
909 /*5211/5212*/
910 ret = ath5k_hw_register_timeout(ah,
911 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
912 AR5K_QCU_STS_FRMPENDCNT, 0, false);
913
914 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
915 return -EIO;
916 }
917
918 return ret;
919}
920#endif
921
922
923/*********************\
924* Key table functions *
925\*********************/
926
927/*
928 * Reset a key entry on the table
929 */
930int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)

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966 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
967 AR5K_KEYTABLE_TYPE(micentry));
968 }
969 }
970
971 return 0;
972}
973
638/*********************\
639* Key table functions *
640\*********************/
641
642/*
643 * Reset a key entry on the table
644 */
645int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)

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681 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
682 AR5K_KEYTABLE_TYPE(micentry));
683 }
684 }
685
686 return 0;
687}
688
974/*
975 * Check if a table entry is valid
976 */
977int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
978{
979 ATH5K_TRACE(ah->ah_sc);
980 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
981
982 /* Check the validation flag at the end of the entry */
983 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
984 AR5K_KEYTABLE_VALID;
985}
986
987static
988int ath5k_keycache_type(const struct ieee80211_key_conf *key)
989{
990 switch (key->alg) {
991 case ALG_TKIP:
992 return AR5K_KEYTABLE_TYPE_TKIP;
993 case ALG_CCMP:
994 return AR5K_KEYTABLE_TYPE_CCM;

--- 159 unchanged lines hidden --- 		689static
690int ath5k_keycache_type(const struct ieee80211_key_conf *key)
691{
692 switch (key->alg) {
693 case ALG_TKIP:
694 return AR5K_KEYTABLE_TYPE_TKIP;
695 case ALG_CCMP:
696 return AR5K_KEYTABLE_TYPE_CCM;

--- 159 unchanged lines hidden ---