1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org> 5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu> 6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> 7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 /*********************************\ 24 * Protocol Control Unit Functions * 25 \*********************************/ 26 27 #include <asm/unaligned.h> 28 29 #include "ath5k.h" 30 #include "reg.h" 31 #include "debug.h" 32 #include "base.h" 33 34 /*******************\ 35 * Generic functions * 36 \*******************/ 37 38 /** 39 * ath5k_hw_set_opmode - Set PCU operating mode 40 * 41 * @ah: The &struct ath5k_hw 42 * 43 * Initialize PCU for the various operating modes (AP/STA etc) 44 * 45 * NOTE: ah->ah_op_mode must be set before calling this. 46 */ 47 int ath5k_hw_set_opmode(struct ath5k_hw *ah) 48 { 49 struct ath_common *common = ath5k_hw_common(ah); 50 u32 pcu_reg, beacon_reg, low_id, high_id; 51 52 53 /* Preserve rest settings */ 54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 55 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP 56 | AR5K_STA_ID1_KEYSRCH_MODE 57 | (ah->ah_version == AR5K_AR5210 ? 58 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); 59 60 beacon_reg = 0; 61 62 ATH5K_TRACE(ah->ah_sc); 63 64 switch (ah->ah_op_mode) { 65 case NL80211_IFTYPE_ADHOC: 66 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; 67 beacon_reg |= AR5K_BCR_ADHOC; 68 if (ah->ah_version == AR5K_AR5210) 69 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 70 else 71 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 72 break; 73 74 case NL80211_IFTYPE_AP: 75 case NL80211_IFTYPE_MESH_POINT: 76 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; 77 beacon_reg |= AR5K_BCR_AP; 78 if (ah->ah_version == AR5K_AR5210) 79 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; 80 else 81 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); 82 break; 83 84 case NL80211_IFTYPE_STATION: 85 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 86 | (ah->ah_version == AR5K_AR5210 ? 87 AR5K_STA_ID1_PWR_SV : 0); 88 case NL80211_IFTYPE_MONITOR: 89 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 90 | (ah->ah_version == AR5K_AR5210 ? 91 AR5K_STA_ID1_NO_PSPOLL : 0); 92 break; 93 94 default: 95 return -EINVAL; 96 } 97 98 /* 99 * Set PCU registers 100 */ 101 low_id = get_unaligned_le32(common->macaddr); 102 high_id = get_unaligned_le16(common->macaddr + 4); 103 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 104 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 105 106 /* 107 * Set Beacon Control Register on 5210 108 */ 109 if (ah->ah_version == AR5K_AR5210) 110 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); 111 112 return 0; 113 } 114 115 /** 116 * ath5k_hw_update - Update mib counters (mac layer statistics) 117 * 118 * @ah: The &struct ath5k_hw 119 * @stats: The &struct ieee80211_low_level_stats we use to track 120 * statistics on the driver 121 * 122 * Reads MIB counters from PCU and updates sw statistics. Must be 123 * called after a MIB interrupt. 124 */ 125 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, 126 struct ieee80211_low_level_stats *stats) 127 { 128 ATH5K_TRACE(ah->ah_sc); 129 130 /* Read-And-Clear */ 131 stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 132 stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); 133 stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK); 134 stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); 135 136 /* XXX: Should we use this to track beacon count ? 137 * -we read it anyway to clear the register */ 138 ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); 139 140 /* Reset profile count registers on 5212*/ 141 if (ah->ah_version == AR5K_AR5212) { 142 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX); 143 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX); 144 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR); 145 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE); 146 } 147 148 /* TODO: Handle ANI stats */ 149 } 150 151 /** 152 * ath5k_hw_set_ack_bitrate - set bitrate for ACKs 153 * 154 * @ah: The &struct ath5k_hw 155 * @high: Flag to determine if we want to use high transmition rate 156 * for ACKs or not 157 * 158 * If high flag is set, we tell hw to use a set of control rates based on 159 * the current transmition rate (check out control_rates array inside reset.c). 160 * If not hw just uses the lowest rate available for the current modulation 161 * scheme being used (1Mbit for CCK and 6Mbits for OFDM). 162 */ 163 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high) 164 { 165 if (ah->ah_version != AR5K_AR5212) 166 return; 167 else { 168 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; 169 if (high) 170 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); 171 else 172 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); 173 } 174 } 175 176 177 /******************\ 178 * ACK/CTS Timeouts * 179 \******************/ 180 181 /** 182 * ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec 183 * 184 * @ah: The &struct ath5k_hw 185 */ 186 unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah) 187 { 188 ATH5K_TRACE(ah->ah_sc); 189 190 return ath5k_hw_clocktoh(ah, AR5K_REG_MS(ath5k_hw_reg_read(ah, 191 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK)); 192 } 193 194 /** 195 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU 196 * 197 * @ah: The &struct ath5k_hw 198 * @timeout: Timeout in usec 199 */ 200 int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) 201 { 202 ATH5K_TRACE(ah->ah_sc); 203 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) 204 <= timeout) 205 return -EINVAL; 206 207 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, 208 ath5k_hw_htoclock(ah, timeout)); 209 210 return 0; 211 } 212 213 /** 214 * ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec 215 * 216 * @ah: The &struct ath5k_hw 217 */ 218 unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah) 219 { 220 ATH5K_TRACE(ah->ah_sc); 221 return ath5k_hw_clocktoh(ah, AR5K_REG_MS(ath5k_hw_reg_read(ah, 222 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS)); 223 } 224 225 /** 226 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU 227 * 228 * @ah: The &struct ath5k_hw 229 * @timeout: Timeout in usec 230 */ 231 int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) 232 { 233 ATH5K_TRACE(ah->ah_sc); 234 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) 235 <= timeout) 236 return -EINVAL; 237 238 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, 239 ath5k_hw_htoclock(ah, timeout)); 240 241 return 0; 242 } 243 244 /** 245 * ath5k_hw_htoclock - Translate usec to hw clock units 246 * 247 * @ah: The &struct ath5k_hw 248 * @usec: value in microseconds 249 */ 250 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec) 251 { 252 return usec * ath5k_hw_get_clockrate(ah); 253 } 254 255 /** 256 * ath5k_hw_clocktoh - Translate hw clock units to usec 257 * @clock: value in hw clock units 258 */ 259 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock) 260 { 261 return clock / ath5k_hw_get_clockrate(ah); 262 } 263 264 /** 265 * ath5k_hw_get_clockrate - Get the clock rate for current mode 266 * 267 * @ah: The &struct ath5k_hw 268 */ 269 unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah) 270 { 271 struct ieee80211_channel *channel = ah->ah_current_channel; 272 int clock; 273 274 if (channel->hw_value & CHANNEL_5GHZ) 275 clock = 40; /* 802.11a */ 276 else if (channel->hw_value & CHANNEL_CCK) 277 clock = 22; /* 802.11b */ 278 else 279 clock = 44; /* 802.11g */ 280 281 /* Clock rate in turbo modes is twice the normal rate */ 282 if (channel->hw_value & CHANNEL_TURBO) 283 clock *= 2; 284 285 return clock; 286 } 287 288 /** 289 * ath5k_hw_get_default_slottime - Get the default slot time for current mode 290 * 291 * @ah: The &struct ath5k_hw 292 */ 293 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah) 294 { 295 struct ieee80211_channel *channel = ah->ah_current_channel; 296 297 if (channel->hw_value & CHANNEL_TURBO) 298 return 6; /* both turbo modes */ 299 300 if (channel->hw_value & CHANNEL_CCK) 301 return 20; /* 802.11b */ 302 303 return 9; /* 802.11 a/g */ 304 } 305 306 /** 307 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode 308 * 309 * @ah: The &struct ath5k_hw 310 */ 311 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah) 312 { 313 struct ieee80211_channel *channel = ah->ah_current_channel; 314 315 if (channel->hw_value & CHANNEL_TURBO) 316 return 8; /* both turbo modes */ 317 318 if (channel->hw_value & CHANNEL_5GHZ) 319 return 16; /* 802.11a */ 320 321 return 10; /* 802.11 b/g */ 322 } 323 324 /** 325 * ath5k_hw_set_lladdr - Set station id 326 * 327 * @ah: The &struct ath5k_hw 328 * @mac: The card's mac address 329 * 330 * Set station id on hw using the provided mac address 331 */ 332 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) 333 { 334 struct ath_common *common = ath5k_hw_common(ah); 335 u32 low_id, high_id; 336 u32 pcu_reg; 337 338 ATH5K_TRACE(ah->ah_sc); 339 /* Set new station ID */ 340 memcpy(common->macaddr, mac, ETH_ALEN); 341 342 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 343 344 low_id = get_unaligned_le32(mac); 345 high_id = get_unaligned_le16(mac + 4); 346 347 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 348 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 349 350 return 0; 351 } 352 353 /** 354 * ath5k_hw_set_associd - Set BSSID for association 355 * 356 * @ah: The &struct ath5k_hw 357 * @bssid: BSSID 358 * @assoc_id: Assoc id 359 * 360 * Sets the BSSID which trigers the "SME Join" operation 361 */ 362 void ath5k_hw_set_associd(struct ath5k_hw *ah) 363 { 364 struct ath_common *common = ath5k_hw_common(ah); 365 u16 tim_offset = 0; 366 367 /* 368 * Set simple BSSID mask on 5212 369 */ 370 if (ah->ah_version == AR5K_AR5212) 371 ath_hw_setbssidmask(common); 372 373 /* 374 * Set BSSID which triggers the "SME Join" operation 375 */ 376 ath5k_hw_reg_write(ah, 377 get_unaligned_le32(common->curbssid), 378 AR5K_BSS_ID0); 379 ath5k_hw_reg_write(ah, 380 get_unaligned_le16(common->curbssid + 4) | 381 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), 382 AR5K_BSS_ID1); 383 384 if (common->curaid == 0) { 385 ath5k_hw_disable_pspoll(ah); 386 return; 387 } 388 389 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, 390 tim_offset ? tim_offset + 4 : 0); 391 392 ath5k_hw_enable_pspoll(ah, NULL, 0); 393 } 394 395 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) 396 { 397 struct ath_common *common = ath5k_hw_common(ah); 398 ATH5K_TRACE(ah->ah_sc); 399 400 /* Cache bssid mask so that we can restore it 401 * on reset */ 402 memcpy(common->bssidmask, mask, ETH_ALEN); 403 if (ah->ah_version == AR5K_AR5212) 404 ath_hw_setbssidmask(common); 405 } 406 407 /************\ 408 * RX Control * 409 \************/ 410 411 /** 412 * ath5k_hw_start_rx_pcu - Start RX engine 413 * 414 * @ah: The &struct ath5k_hw 415 * 416 * Starts RX engine on PCU so that hw can process RXed frames 417 * (ACK etc). 418 * 419 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma 420 * TODO: Init ANI here 421 */ 422 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) 423 { 424 ATH5K_TRACE(ah->ah_sc); 425 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 426 } 427 428 /** 429 * at5k_hw_stop_rx_pcu - Stop RX engine 430 * 431 * @ah: The &struct ath5k_hw 432 * 433 * Stops RX engine on PCU 434 * 435 * TODO: Detach ANI here 436 */ 437 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) 438 { 439 ATH5K_TRACE(ah->ah_sc); 440 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 441 } 442 443 /* 444 * Set multicast filter 445 */ 446 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) 447 { 448 ATH5K_TRACE(ah->ah_sc); 449 /* Set the multicat filter */ 450 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); 451 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 452 } 453 454 /* 455 * Set multicast filter by index 456 */ 457 int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index) 458 { 459 460 ATH5K_TRACE(ah->ah_sc); 461 if (index >= 64) 462 return -EINVAL; 463 else if (index >= 32) 464 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1, 465 (1 << (index - 32))); 466 else 467 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index)); 468 469 return 0; 470 } 471 472 /* 473 * Clear Multicast filter by index 474 */ 475 int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index) 476 { 477 478 ATH5K_TRACE(ah->ah_sc); 479 if (index >= 64) 480 return -EINVAL; 481 else if (index >= 32) 482 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1, 483 (1 << (index - 32))); 484 else 485 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index)); 486 487 return 0; 488 } 489 490 /** 491 * ath5k_hw_get_rx_filter - Get current rx filter 492 * 493 * @ah: The &struct ath5k_hw 494 * 495 * Returns the RX filter by reading rx filter and 496 * phy error filter registers. RX filter is used 497 * to set the allowed frame types that PCU will accept 498 * and pass to the driver. For a list of frame types 499 * check out reg.h. 500 */ 501 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah) 502 { 503 u32 data, filter = 0; 504 505 ATH5K_TRACE(ah->ah_sc); 506 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); 507 508 /*Radar detection for 5212*/ 509 if (ah->ah_version == AR5K_AR5212) { 510 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); 511 512 if (data & AR5K_PHY_ERR_FIL_RADAR) 513 filter |= AR5K_RX_FILTER_RADARERR; 514 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) 515 filter |= AR5K_RX_FILTER_PHYERR; 516 } 517 518 return filter; 519 } 520 521 /** 522 * ath5k_hw_set_rx_filter - Set rx filter 523 * 524 * @ah: The &struct ath5k_hw 525 * @filter: RX filter mask (see reg.h) 526 * 527 * Sets RX filter register and also handles PHY error filter 528 * register on 5212 and newer chips so that we have proper PHY 529 * error reporting. 530 */ 531 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) 532 { 533 u32 data = 0; 534 535 ATH5K_TRACE(ah->ah_sc); 536 537 /* Set PHY error filter register on 5212*/ 538 if (ah->ah_version == AR5K_AR5212) { 539 if (filter & AR5K_RX_FILTER_RADARERR) 540 data |= AR5K_PHY_ERR_FIL_RADAR; 541 if (filter & AR5K_RX_FILTER_PHYERR) 542 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; 543 } 544 545 /* 546 * The AR5210 uses promiscous mode to detect radar activity 547 */ 548 if (ah->ah_version == AR5K_AR5210 && 549 (filter & AR5K_RX_FILTER_RADARERR)) { 550 filter &= ~AR5K_RX_FILTER_RADARERR; 551 filter |= AR5K_RX_FILTER_PROM; 552 } 553 554 /*Zero length DMA (phy error reporting) */ 555 if (data) 556 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 557 else 558 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 559 560 /*Write RX Filter register*/ 561 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); 562 563 /*Write PHY error filter register on 5212*/ 564 if (ah->ah_version == AR5K_AR5212) 565 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); 566 567 } 568 569 570 /****************\ 571 * Beacon control * 572 \****************/ 573 574 /** 575 * ath5k_hw_get_tsf32 - Get a 32bit TSF 576 * 577 * @ah: The &struct ath5k_hw 578 * 579 * Returns lower 32 bits of current TSF 580 */ 581 u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah) 582 { 583 ATH5K_TRACE(ah->ah_sc); 584 return ath5k_hw_reg_read(ah, AR5K_TSF_L32); 585 } 586 587 /** 588 * ath5k_hw_get_tsf64 - Get the full 64bit TSF 589 * 590 * @ah: The &struct ath5k_hw 591 * 592 * Returns the current TSF 593 */ 594 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah) 595 { 596 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32); 597 ATH5K_TRACE(ah->ah_sc); 598 599 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32); 600 } 601 602 /** 603 * ath5k_hw_set_tsf64 - Set a new 64bit TSF 604 * 605 * @ah: The &struct ath5k_hw 606 * @tsf64: The new 64bit TSF 607 * 608 * Sets the new TSF 609 */ 610 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) 611 { 612 ATH5K_TRACE(ah->ah_sc); 613 614 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); 615 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); 616 } 617 618 /** 619 * ath5k_hw_reset_tsf - Force a TSF reset 620 * 621 * @ah: The &struct ath5k_hw 622 * 623 * Forces a TSF reset on PCU 624 */ 625 void ath5k_hw_reset_tsf(struct ath5k_hw *ah) 626 { 627 u32 val; 628 629 ATH5K_TRACE(ah->ah_sc); 630 631 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; 632 633 /* 634 * Each write to the RESET_TSF bit toggles a hardware internal 635 * signal to reset TSF, but if left high it will cause a TSF reset 636 * on the next chip reset as well. Thus we always write the value 637 * twice to clear the signal. 638 */ 639 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 640 ath5k_hw_reg_write(ah, val, AR5K_BEACON); 641 } 642 643 /* 644 * Initialize beacon timers 645 */ 646 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval) 647 { 648 u32 timer1, timer2, timer3; 649 650 ATH5K_TRACE(ah->ah_sc); 651 /* 652 * Set the additional timers by mode 653 */ 654 switch (ah->ah_op_mode) { 655 case NL80211_IFTYPE_MONITOR: 656 case NL80211_IFTYPE_STATION: 657 /* In STA mode timer1 is used as next wakeup 658 * timer and timer2 as next CFP duration start 659 * timer. Both in 1/8TUs. */ 660 /* TODO: PCF handling */ 661 if (ah->ah_version == AR5K_AR5210) { 662 timer1 = 0xffffffff; 663 timer2 = 0xffffffff; 664 } else { 665 timer1 = 0x0000ffff; 666 timer2 = 0x0007ffff; 667 } 668 /* Mark associated AP as PCF incapable for now */ 669 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); 670 break; 671 case NL80211_IFTYPE_ADHOC: 672 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); 673 default: 674 /* On non-STA modes timer1 is used as next DMA 675 * beacon alert (DBA) timer and timer2 as next 676 * software beacon alert. Both in 1/8TUs. */ 677 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; 678 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; 679 break; 680 } 681 682 /* Timer3 marks the end of our ATIM window 683 * a zero length window is not allowed because 684 * we 'll get no beacons */ 685 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1); 686 687 /* 688 * Set the beacon register and enable all timers. 689 */ 690 /* When in AP or Mesh Point mode zero timer0 to start TSF */ 691 if (ah->ah_op_mode == NL80211_IFTYPE_AP || 692 ah->ah_op_mode == NL80211_IFTYPE_MESH_POINT) 693 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 694 695 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); 696 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); 697 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); 698 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); 699 700 /* Force a TSF reset if requested and enable beacons */ 701 if (interval & AR5K_BEACON_RESET_TSF) 702 ath5k_hw_reset_tsf(ah); 703 704 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | 705 AR5K_BEACON_ENABLE), 706 AR5K_BEACON); 707 708 /* Flush any pending BMISS interrupts on ISR by 709 * performing a clear-on-write operation on PISR 710 * register for the BMISS bit (writing a bit on 711 * ISR togles a reset for that bit and leaves 712 * the rest bits intact) */ 713 if (ah->ah_version == AR5K_AR5210) 714 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); 715 else 716 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); 717 718 /* TODO: Set enchanced sleep registers on AR5212 719 * based on vif->bss_conf params, until then 720 * disable power save reporting.*/ 721 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); 722 723 } 724 725 #if 0 726 /* 727 * Set beacon timers 728 */ 729 int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, 730 const struct ath5k_beacon_state *state) 731 { 732 u32 cfp_period, next_cfp, dtim, interval, next_beacon; 733 734 /* 735 * TODO: should be changed through *state 736 * review struct ath5k_beacon_state struct 737 * 738 * XXX: These are used for cfp period bellow, are they 739 * ok ? Is it O.K. for tsf here to be 0 or should we use 740 * get_tsf ? 741 */ 742 u32 dtim_count = 0; /* XXX */ 743 u32 cfp_count = 0; /* XXX */ 744 u32 tsf = 0; /* XXX */ 745 746 ATH5K_TRACE(ah->ah_sc); 747 /* Return on an invalid beacon state */ 748 if (state->bs_interval < 1) 749 return -EINVAL; 750 751 interval = state->bs_interval; 752 dtim = state->bs_dtim_period; 753 754 /* 755 * PCF support? 756 */ 757 if (state->bs_cfp_period > 0) { 758 /* 759 * Enable PCF mode and set the CFP 760 * (Contention Free Period) and timer registers 761 */ 762 cfp_period = state->bs_cfp_period * state->bs_dtim_period * 763 state->bs_interval; 764 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) * 765 state->bs_interval; 766 767 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, 768 AR5K_STA_ID1_DEFAULT_ANTENNA | 769 AR5K_STA_ID1_PCF); 770 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD); 771 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration, 772 AR5K_CFP_DUR); 773 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period : 774 next_cfp)) << 3, AR5K_TIMER2); 775 } else { 776 /* Disable PCF mode */ 777 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, 778 AR5K_STA_ID1_DEFAULT_ANTENNA | 779 AR5K_STA_ID1_PCF); 780 } 781 782 /* 783 * Enable the beacon timer register 784 */ 785 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0); 786 787 /* 788 * Start the beacon timers 789 */ 790 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) & 791 ~(AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) | 792 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0, 793 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval, 794 AR5K_BEACON_PERIOD), AR5K_BEACON); 795 796 /* 797 * Write new beacon miss threshold, if it appears to be valid 798 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max 799 * and return if its not in range. We can test this by reading value and 800 * setting value to a largest value and seeing which values register. 801 */ 802 803 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS, 804 state->bs_bmiss_threshold); 805 806 /* 807 * Set sleep control register 808 * XXX: Didn't find this in 5210 code but since this register 809 * exists also in ar5k's 5210 headers i leave it as common code. 810 */ 811 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR, 812 (state->bs_sleep_duration - 3) << 3); 813 814 /* 815 * Set enhanced sleep registers on 5212 816 */ 817 if (ah->ah_version == AR5K_AR5212) { 818 if (state->bs_sleep_duration > state->bs_interval && 819 roundup(state->bs_sleep_duration, interval) == 820 state->bs_sleep_duration) 821 interval = state->bs_sleep_duration; 822 823 if (state->bs_sleep_duration > dtim && (dtim == 0 || 824 roundup(state->bs_sleep_duration, dtim) == 825 state->bs_sleep_duration)) 826 dtim = state->bs_sleep_duration; 827 828 if (interval > dtim) 829 return -EINVAL; 830 831 next_beacon = interval == dtim ? state->bs_next_dtim : 832 state->bs_next_beacon; 833 834 ath5k_hw_reg_write(ah, 835 AR5K_REG_SM((state->bs_next_dtim - 3) << 3, 836 AR5K_SLEEP0_NEXT_DTIM) | 837 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) | 838 AR5K_SLEEP0_ENH_SLEEP_EN | 839 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0); 840 841 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3, 842 AR5K_SLEEP1_NEXT_TIM) | 843 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1); 844 845 ath5k_hw_reg_write(ah, 846 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) | 847 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2); 848 } 849 850 return 0; 851 } 852 853 /* 854 * Reset beacon timers 855 */ 856 void ath5k_hw_reset_beacon(struct ath5k_hw *ah) 857 { 858 ATH5K_TRACE(ah->ah_sc); 859 /* 860 * Disable beacon timer 861 */ 862 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 863 864 /* 865 * Disable some beacon register values 866 */ 867 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, 868 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF); 869 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON); 870 } 871 872 /* 873 * Wait for beacon queue to finish 874 */ 875 int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr) 876 { 877 unsigned int i; 878 int ret; 879 880 ATH5K_TRACE(ah->ah_sc); 881 882 /* 5210 doesn't have QCU*/ 883 if (ah->ah_version == AR5K_AR5210) { 884 /* 885 * Wait for beaconn queue to finish by checking 886 * Control Register and Beacon Status Register. 887 */ 888 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) { 889 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F) 890 || 891 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F)) 892 break; 893 udelay(10); 894 } 895 896 /* Timeout... */ 897 if (i <= 0) { 898 /* 899 * Re-schedule the beacon queue 900 */ 901 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1); 902 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, 903 AR5K_BCR); 904 905 return -EIO; 906 } 907 ret = 0; 908 } else { 909 /*5211/5212*/ 910 ret = ath5k_hw_register_timeout(ah, 911 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON), 912 AR5K_QCU_STS_FRMPENDCNT, 0, false); 913 914 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON)) 915 return -EIO; 916 } 917 918 return ret; 919 } 920 #endif 921 922 923 /*********************\ 924 * Key table functions * 925 \*********************/ 926 927 /* 928 * Reset a key entry on the table 929 */ 930 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry) 931 { 932 unsigned int i, type; 933 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET; 934 935 ATH5K_TRACE(ah->ah_sc); 936 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); 937 938 type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry)); 939 940 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) 941 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i)); 942 943 /* Reset associated MIC entry if TKIP 944 * is enabled located at offset (entry + 64) */ 945 if (type == AR5K_KEYTABLE_TYPE_TKIP) { 946 AR5K_ASSERT_ENTRY(micentry, AR5K_KEYTABLE_SIZE); 947 for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++) 948 ath5k_hw_reg_write(ah, 0, 949 AR5K_KEYTABLE_OFF(micentry, i)); 950 } 951 952 /* 953 * Set NULL encryption on AR5212+ 954 * 955 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5) 956 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007 957 * 958 * Note2: Windows driver (ndiswrapper) sets this to 959 * 0x00000714 instead of 0x00000007 960 */ 961 if (ah->ah_version >= AR5K_AR5211) { 962 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, 963 AR5K_KEYTABLE_TYPE(entry)); 964 965 if (type == AR5K_KEYTABLE_TYPE_TKIP) { 966 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, 967 AR5K_KEYTABLE_TYPE(micentry)); 968 } 969 } 970 971 return 0; 972 } 973 974 /* 975 * Check if a table entry is valid 976 */ 977 int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry) 978 { 979 ATH5K_TRACE(ah->ah_sc); 980 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); 981 982 /* Check the validation flag at the end of the entry */ 983 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) & 984 AR5K_KEYTABLE_VALID; 985 } 986 987 static 988 int ath5k_keycache_type(const struct ieee80211_key_conf *key) 989 { 990 switch (key->alg) { 991 case ALG_TKIP: 992 return AR5K_KEYTABLE_TYPE_TKIP; 993 case ALG_CCMP: 994 return AR5K_KEYTABLE_TYPE_CCM; 995 case ALG_WEP: 996 if (key->keylen == WLAN_KEY_LEN_WEP40) 997 return AR5K_KEYTABLE_TYPE_40; 998 else if (key->keylen == WLAN_KEY_LEN_WEP104) 999 return AR5K_KEYTABLE_TYPE_104; 1000 return -EINVAL; 1001 default: 1002 return -EINVAL; 1003 } 1004 return -EINVAL; 1005 } 1006 1007 /* 1008 * Set a key entry on the table 1009 */ 1010 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, 1011 const struct ieee80211_key_conf *key, const u8 *mac) 1012 { 1013 unsigned int i; 1014 int keylen; 1015 __le32 key_v[5] = {}; 1016 __le32 key0 = 0, key1 = 0; 1017 __le32 *rxmic, *txmic; 1018 int keytype; 1019 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET; 1020 bool is_tkip; 1021 const u8 *key_ptr; 1022 1023 ATH5K_TRACE(ah->ah_sc); 1024 1025 is_tkip = (key->alg == ALG_TKIP); 1026 1027 /* 1028 * key->keylen comes in from mac80211 in bytes. 1029 * TKIP is 128 bit + 128 bit mic 1030 */ 1031 keylen = (is_tkip) ? (128 / 8) : key->keylen; 1032 1033 if (entry > AR5K_KEYTABLE_SIZE || 1034 (is_tkip && micentry > AR5K_KEYTABLE_SIZE)) 1035 return -EOPNOTSUPP; 1036 1037 if (unlikely(keylen > 16)) 1038 return -EOPNOTSUPP; 1039 1040 keytype = ath5k_keycache_type(key); 1041 if (keytype < 0) 1042 return keytype; 1043 1044 /* 1045 * each key block is 6 bytes wide, written as pairs of 1046 * alternating 32 and 16 bit le values. 1047 */ 1048 key_ptr = key->key; 1049 for (i = 0; keylen >= 6; keylen -= 6) { 1050 memcpy(&key_v[i], key_ptr, 6); 1051 i += 2; 1052 key_ptr += 6; 1053 } 1054 if (keylen) 1055 memcpy(&key_v[i], key_ptr, keylen); 1056 1057 /* intentionally corrupt key until mic is installed */ 1058 if (is_tkip) { 1059 key0 = key_v[0] = ~key_v[0]; 1060 key1 = key_v[1] = ~key_v[1]; 1061 } 1062 1063 for (i = 0; i < ARRAY_SIZE(key_v); i++) 1064 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]), 1065 AR5K_KEYTABLE_OFF(entry, i)); 1066 1067 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry)); 1068 1069 if (is_tkip) { 1070 /* Install rx/tx MIC */ 1071 rxmic = (__le32 *) &key->key[16]; 1072 txmic = (__le32 *) &key->key[24]; 1073 1074 if (ah->ah_combined_mic) { 1075 key_v[0] = rxmic[0]; 1076 key_v[1] = cpu_to_le32(le32_to_cpu(txmic[0]) >> 16); 1077 key_v[2] = rxmic[1]; 1078 key_v[3] = cpu_to_le32(le32_to_cpu(txmic[0]) & 0xffff); 1079 key_v[4] = txmic[1]; 1080 } else { 1081 key_v[0] = rxmic[0]; 1082 key_v[1] = 0; 1083 key_v[2] = rxmic[1]; 1084 key_v[3] = 0; 1085 key_v[4] = 0; 1086 } 1087 for (i = 0; i < ARRAY_SIZE(key_v); i++) 1088 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]), 1089 AR5K_KEYTABLE_OFF(micentry, i)); 1090 1091 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, 1092 AR5K_KEYTABLE_TYPE(micentry)); 1093 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC0(micentry)); 1094 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC1(micentry)); 1095 1096 /* restore first 2 words of key */ 1097 ath5k_hw_reg_write(ah, le32_to_cpu(~key0), 1098 AR5K_KEYTABLE_OFF(entry, 0)); 1099 ath5k_hw_reg_write(ah, le32_to_cpu(~key1), 1100 AR5K_KEYTABLE_OFF(entry, 1)); 1101 } 1102 1103 return ath5k_hw_set_key_lladdr(ah, entry, mac); 1104 } 1105 1106 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac) 1107 { 1108 u32 low_id, high_id; 1109 1110 ATH5K_TRACE(ah->ah_sc); 1111 /* Invalid entry (key table overflow) */ 1112 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE); 1113 1114 /* 1115 * MAC may be NULL if it's a broadcast key. In this case no need to 1116 * to compute get_unaligned_le32 and get_unaligned_le16 as we 1117 * already know it. 1118 */ 1119 if (!mac) { 1120 low_id = 0xffffffff; 1121 high_id = 0xffff | AR5K_KEYTABLE_VALID; 1122 } else { 1123 low_id = get_unaligned_le32(mac); 1124 high_id = get_unaligned_le16(mac + 4) | AR5K_KEYTABLE_VALID; 1125 } 1126 1127 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry)); 1128 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry)); 1129 1130 return 0; 1131 } 1132 1133 /** 1134 * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class 1135 * 1136 * @ah: The &struct ath5k_hw 1137 * @coverage_class: IEEE 802.11 coverage class number 1138 * 1139 * Sets slot time, ACK timeout and CTS timeout for given coverage class. 1140 */ 1141 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) 1142 { 1143 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1144 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; 1145 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time; 1146 int cts_timeout = ack_timeout; 1147 1148 ath5k_hw_set_slot_time(ah, slot_time); 1149 ath5k_hw_set_ack_timeout(ah, ack_timeout); 1150 ath5k_hw_set_cts_timeout(ah, cts_timeout); 1151 1152 ah->ah_coverage_class = coverage_class; 1153 } 1154