pci.c (6c76dd3a91e33b5fac2c4f0d724b571d24b7533a) pci.c (94e8235c679db3e3b130a91d4c1d8f5023a5bb01)
1// SPDX-License-Identifier: BSD-3-Clause-Clear
2/*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
1// SPDX-License-Identifier: BSD-3-Clause-Clear
2/*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#include <linux/module.h>
8#include <linux/msi.h>
9#include <linux/pci.h>
10
11#include "pci.h"
12#include "core.h"

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34 * need to force wakeup.
35 * 4K - 32 = 0xFE0
36 */
37#define ACCESS_ALWAYS_OFF 0xFE0
38
39#define QCN9274_DEVICE_ID 0x1109
40#define WCN7850_DEVICE_ID 0x1107
41
5 */
6
7#include <linux/module.h>
8#include <linux/msi.h>
9#include <linux/pci.h>
10
11#include "pci.h"
12#include "core.h"

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34 * need to force wakeup.
35 * 4K - 32 = 0xFE0
36 */
37#define ACCESS_ALWAYS_OFF 0xFE0
38
39#define QCN9274_DEVICE_ID 0x1109
40#define WCN7850_DEVICE_ID 0x1107
41
42#define PCIE_LOCAL_REG_QRTR_NODE_ID 0x1E03164
43#define DOMAIN_NUMBER_MASK GENMASK(7, 4)
44#define BUS_NUMBER_MASK GENMASK(3, 0)
45
42static const struct pci_device_id ath12k_pci_id_table[] = {
43 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) },
44 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) },
45 {0}
46};
47
48MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table);
49

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677
678 return 0;
679}
680
681static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab)
682{
683 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
684
46static const struct pci_device_id ath12k_pci_id_table[] = {
47 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) },
48 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) },
49 {0}
50};
51
52MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table);
53

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681
682 return 0;
683}
684
685static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab)
686{
687 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
688
689 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
690 struct pci_bus *bus = ab_pci->pdev->bus;
691
685 cfg->tgt_ce = ab->hw_params->target_ce_config;
686 cfg->tgt_ce_len = ab->hw_params->target_ce_count;
687
688 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map;
689 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len;
690 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id;
692 cfg->tgt_ce = ab->hw_params->target_ce_config;
693 cfg->tgt_ce_len = ab->hw_params->target_ce_count;
694
695 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map;
696 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len;
697 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id;
698
699 if (test_bit(ATH12K_FW_FEATURE_MULTI_QRTR_ID, ab->fw.fw_features)) {
700 ab_pci->qmi_instance =
701 u32_encode_bits(pci_domain_nr(bus), DOMAIN_NUMBER_MASK) |
702 u32_encode_bits(bus->number, BUS_NUMBER_MASK);
703 ab->qmi.service_ins_id += ab_pci->qmi_instance;
704 }
691}
692
693static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab)
694{
695 int i;
696
697 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
698

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896
897 /* disable L0s and L1 */
898 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL,
899 PCI_EXP_LNKCTL_ASPMC);
900
901 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags);
902}
903
705}
706
707static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab)
708{
709 int i;
710
711 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags);
712

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910
911 /* disable L0s and L1 */
912 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL,
913 PCI_EXP_LNKCTL_ASPMC);
914
915 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags);
916}
917
918static void ath12k_pci_update_qrtr_node_id(struct ath12k_base *ab)
919{
920 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
921 u32 reg;
922
923 /* On platforms with two or more identical mhi devices, qmi service run
924 * with identical qrtr-node-id. Because of this identical ID qrtr-lookup
925 * cannot register more than one qmi service with identical node ID.
926 *
927 * This generates a unique instance ID from PCIe domain number and bus number,
928 * writes to the given register, it is available for firmware when the QMI service
929 * is spawned.
930 */
931 reg = PCIE_LOCAL_REG_QRTR_NODE_ID & WINDOW_RANGE_MASK;
932 ath12k_pci_write32(ab, reg, ab_pci->qmi_instance);
933
934 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci reg 0x%x instance 0x%x read val 0x%x\n",
935 reg, ab_pci->qmi_instance, ath12k_pci_read32(ab, reg));
936}
937
904static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci)
905{
906 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags))
907 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL,
908 PCI_EXP_LNKCTL_ASPMC,
909 ab_pci->link_ctl &
910 PCI_EXP_LNKCTL_ASPMC);
911}

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1214
1215 /* Disable ASPM during firmware download due to problems switching
1216 * to AMSS state.
1217 */
1218 ath12k_pci_aspm_disable(ab_pci);
1219
1220 ath12k_pci_msi_enable(ab_pci);
1221
938static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci)
939{
940 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags))
941 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL,
942 PCI_EXP_LNKCTL_ASPMC,
943 ab_pci->link_ctl &
944 PCI_EXP_LNKCTL_ASPMC);
945}

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1248
1249 /* Disable ASPM during firmware download due to problems switching
1250 * to AMSS state.
1251 */
1252 ath12k_pci_aspm_disable(ab_pci);
1253
1254 ath12k_pci_msi_enable(ab_pci);
1255
1256 if (test_bit(ATH12K_FW_FEATURE_MULTI_QRTR_ID, ab->fw.fw_features))
1257 ath12k_pci_update_qrtr_node_id(ab);
1258
1222 ret = ath12k_mhi_start(ab_pci);
1223 if (ret) {
1224 ath12k_err(ab, "failed to start mhi: %d\n", ret);
1225 return ret;
1226 }
1227
1228 if (ab->static_window_map)
1229 ath12k_pci_select_static_window(ab_pci);

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1259 ret = ath12k_mhi_start(ab_pci);
1260 if (ret) {
1261 ath12k_err(ab, "failed to start mhi: %d\n", ret);
1262 return ret;
1263 }
1264
1265 if (ab->static_window_map)
1266 ath12k_pci_select_static_window(ab_pci);

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