1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/msi.h> 9 #include <linux/pci.h> 10 11 #include "pci.h" 12 #include "core.h" 13 #include "hif.h" 14 #include "mhi.h" 15 #include "debug.h" 16 17 #define ATH12K_PCI_BAR_NUM 0 18 #define ATH12K_PCI_DMA_MASK 32 19 20 #define ATH12K_PCI_IRQ_CE0_OFFSET 3 21 22 #define WINDOW_ENABLE_BIT 0x40000000 23 #define WINDOW_REG_ADDRESS 0x310c 24 #define WINDOW_VALUE_MASK GENMASK(24, 19) 25 #define WINDOW_START 0x80000 26 #define WINDOW_RANGE_MASK GENMASK(18, 0) 27 #define WINDOW_STATIC_MASK GENMASK(31, 6) 28 29 #define TCSR_SOC_HW_VERSION 0x1B00000 30 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) 31 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4) 32 33 /* BAR0 + 4k is always accessible, and no 34 * need to force wakeup. 35 * 4K - 32 = 0xFE0 36 */ 37 #define ACCESS_ALWAYS_OFF 0xFE0 38 39 #define QCN9274_DEVICE_ID 0x1109 40 #define WCN7850_DEVICE_ID 0x1107 41 42 #define PCIE_LOCAL_REG_QRTR_NODE_ID 0x1E03164 43 #define DOMAIN_NUMBER_MASK GENMASK(7, 4) 44 #define BUS_NUMBER_MASK GENMASK(3, 0) 45 46 static const struct pci_device_id ath12k_pci_id_table[] = { 47 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) }, 48 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) }, 49 {0} 50 }; 51 52 MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table); 53 54 /* TODO: revisit IRQ mapping for new SRNG's */ 55 static const struct ath12k_msi_config ath12k_msi_config[] = { 56 { 57 .total_vectors = 16, 58 .total_users = 3, 59 .users = (struct ath12k_msi_user[]) { 60 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 61 { .name = "CE", .num_vectors = 5, .base_vector = 3 }, 62 { .name = "DP", .num_vectors = 8, .base_vector = 8 }, 63 }, 64 }, 65 }; 66 67 static const struct ath12k_msi_config msi_config_one_msi = { 68 .total_vectors = 1, 69 .total_users = 4, 70 .users = (struct ath12k_msi_user[]) { 71 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 72 { .name = "CE", .num_vectors = 1, .base_vector = 0 }, 73 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 }, 74 { .name = "DP", .num_vectors = 1, .base_vector = 0 }, 75 }, 76 }; 77 78 static const char *irq_name[ATH12K_IRQ_NUM_MAX] = { 79 "bhi", 80 "mhi-er0", 81 "mhi-er1", 82 "ce0", 83 "ce1", 84 "ce2", 85 "ce3", 86 "ce4", 87 "ce5", 88 "ce6", 89 "ce7", 90 "ce8", 91 "ce9", 92 "ce10", 93 "ce11", 94 "ce12", 95 "ce13", 96 "ce14", 97 "ce15", 98 "host2wbm-desc-feed", 99 "host2reo-re-injection", 100 "host2reo-command", 101 "host2rxdma-monitor-ring3", 102 "host2rxdma-monitor-ring2", 103 "host2rxdma-monitor-ring1", 104 "reo2ost-exception", 105 "wbm2host-rx-release", 106 "reo2host-status", 107 "reo2host-destination-ring4", 108 "reo2host-destination-ring3", 109 "reo2host-destination-ring2", 110 "reo2host-destination-ring1", 111 "rxdma2host-monitor-destination-mac3", 112 "rxdma2host-monitor-destination-mac2", 113 "rxdma2host-monitor-destination-mac1", 114 "ppdu-end-interrupts-mac3", 115 "ppdu-end-interrupts-mac2", 116 "ppdu-end-interrupts-mac1", 117 "rxdma2host-monitor-status-ring-mac3", 118 "rxdma2host-monitor-status-ring-mac2", 119 "rxdma2host-monitor-status-ring-mac1", 120 "host2rxdma-host-buf-ring-mac3", 121 "host2rxdma-host-buf-ring-mac2", 122 "host2rxdma-host-buf-ring-mac1", 123 "rxdma2host-destination-ring-mac3", 124 "rxdma2host-destination-ring-mac2", 125 "rxdma2host-destination-ring-mac1", 126 "host2tcl-input-ring4", 127 "host2tcl-input-ring3", 128 "host2tcl-input-ring2", 129 "host2tcl-input-ring1", 130 "wbm2host-tx-completions-ring4", 131 "wbm2host-tx-completions-ring3", 132 "wbm2host-tx-completions-ring2", 133 "wbm2host-tx-completions-ring1", 134 "tcl2host-status-ring", 135 }; 136 137 static int ath12k_pci_bus_wake_up(struct ath12k_base *ab) 138 { 139 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 140 141 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 142 } 143 144 static void ath12k_pci_bus_release(struct ath12k_base *ab) 145 { 146 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 147 148 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 149 } 150 151 static const struct ath12k_pci_ops ath12k_pci_ops_qcn9274 = { 152 .wakeup = NULL, 153 .release = NULL, 154 }; 155 156 static const struct ath12k_pci_ops ath12k_pci_ops_wcn7850 = { 157 .wakeup = ath12k_pci_bus_wake_up, 158 .release = ath12k_pci_bus_release, 159 }; 160 161 static void ath12k_pci_select_window(struct ath12k_pci *ab_pci, u32 offset) 162 { 163 struct ath12k_base *ab = ab_pci->ab; 164 165 u32 window = u32_get_bits(offset, WINDOW_VALUE_MASK); 166 u32 static_window; 167 168 lockdep_assert_held(&ab_pci->window_lock); 169 170 /* Preserve the static window configuration and reset only dynamic window */ 171 static_window = ab_pci->register_window & WINDOW_STATIC_MASK; 172 window |= static_window; 173 174 if (window != ab_pci->register_window) { 175 iowrite32(WINDOW_ENABLE_BIT | window, 176 ab->mem + WINDOW_REG_ADDRESS); 177 ioread32(ab->mem + WINDOW_REG_ADDRESS); 178 ab_pci->register_window = window; 179 } 180 } 181 182 static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci) 183 { 184 u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK); 185 u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK); 186 u32 window; 187 188 window = (umac_window << 12) | (ce_window << 6); 189 190 spin_lock_bh(&ab_pci->window_lock); 191 ab_pci->register_window = window; 192 spin_unlock_bh(&ab_pci->window_lock); 193 194 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); 195 } 196 197 static u32 ath12k_pci_get_window_start(struct ath12k_base *ab, 198 u32 offset) 199 { 200 u32 window_start; 201 202 /* If offset lies within DP register range, use 3rd window */ 203 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) 204 window_start = 3 * WINDOW_START; 205 /* If offset lies within CE register range, use 2nd window */ 206 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) 207 window_start = 2 * WINDOW_START; 208 /* If offset lies within PCI_BAR_WINDOW0_BASE and within PCI_SOC_PCI_REG_BASE 209 * use 0th window 210 */ 211 else if (((offset ^ PCI_BAR_WINDOW0_BASE) < WINDOW_RANGE_MASK) && 212 !((offset ^ PCI_SOC_PCI_REG_BASE) < PCI_SOC_RANGE_MASK)) 213 window_start = 0; 214 else 215 window_start = WINDOW_START; 216 217 return window_start; 218 } 219 220 static void ath12k_pci_soc_global_reset(struct ath12k_base *ab) 221 { 222 u32 val, delay; 223 224 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 225 226 val |= PCIE_SOC_GLOBAL_RESET_V; 227 228 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 229 230 /* TODO: exact time to sleep is uncertain */ 231 delay = 10; 232 mdelay(delay); 233 234 /* Need to toggle V bit back otherwise stuck in reset status */ 235 val &= ~PCIE_SOC_GLOBAL_RESET_V; 236 237 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 238 239 mdelay(delay); 240 241 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 242 if (val == 0xffffffff) 243 ath12k_warn(ab, "link down error during global reset\n"); 244 } 245 246 static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab) 247 { 248 u32 val; 249 250 /* read cookie */ 251 val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 252 ath12k_dbg(ab, ATH12K_DBG_PCI, "cookie:0x%x\n", val); 253 254 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 255 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 256 257 /* TODO: exact time to sleep is uncertain */ 258 mdelay(10); 259 260 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 261 * continuing warm path and entering dead loop. 262 */ 263 ath12k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 264 mdelay(10); 265 266 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 267 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 268 269 /* A read clear register. clear the register to prevent 270 * Q6 from entering wrong code path. 271 */ 272 val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 273 ath12k_dbg(ab, ATH12K_DBG_PCI, "soc reset cause:%d\n", val); 274 } 275 276 static void ath12k_pci_enable_ltssm(struct ath12k_base *ab) 277 { 278 u32 val; 279 int i; 280 281 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 282 283 /* PCIE link seems very unstable after the Hot Reset*/ 284 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 285 if (val == 0xffffffff) 286 mdelay(5); 287 288 ath12k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 289 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 290 } 291 292 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val); 293 294 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 295 val |= GCC_GCC_PCIE_HOT_RST_VAL; 296 ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val); 297 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 298 299 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val); 300 301 mdelay(5); 302 } 303 304 static void ath12k_pci_clear_all_intrs(struct ath12k_base *ab) 305 { 306 /* This is a WAR for PCIE Hotreset. 307 * When target receive Hotreset, but will set the interrupt. 308 * So when download SBL again, SBL will open Interrupt and 309 * receive it, and crash immediately. 310 */ 311 ath12k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 312 } 313 314 static void ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base *ab) 315 { 316 u32 val; 317 318 val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 319 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 320 ath12k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 321 } 322 323 static void ath12k_pci_force_wake(struct ath12k_base *ab) 324 { 325 ath12k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 326 mdelay(5); 327 } 328 329 static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on) 330 { 331 if (power_on) { 332 ath12k_pci_enable_ltssm(ab); 333 ath12k_pci_clear_all_intrs(ab); 334 ath12k_pci_set_wlaon_pwr_ctrl(ab); 335 } 336 337 ath12k_mhi_clear_vector(ab); 338 ath12k_pci_clear_dbg_registers(ab); 339 ath12k_pci_soc_global_reset(ab); 340 ath12k_mhi_set_mhictrl_reset(ab); 341 } 342 343 static void ath12k_pci_free_ext_irq(struct ath12k_base *ab) 344 { 345 int i, j; 346 347 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 348 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 349 350 for (j = 0; j < irq_grp->num_irq; j++) 351 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 352 353 netif_napi_del(&irq_grp->napi); 354 } 355 } 356 357 static void ath12k_pci_free_irq(struct ath12k_base *ab) 358 { 359 int i, irq_idx; 360 361 for (i = 0; i < ab->hw_params->ce_count; i++) { 362 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 363 continue; 364 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 365 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 366 } 367 368 ath12k_pci_free_ext_irq(ab); 369 } 370 371 static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id) 372 { 373 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 374 u32 irq_idx; 375 376 /* In case of one MSI vector, we handle irq enable/disable in a 377 * uniform way since we only have one irq 378 */ 379 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 380 return; 381 382 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; 383 enable_irq(ab->irq_num[irq_idx]); 384 } 385 386 static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id) 387 { 388 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 389 u32 irq_idx; 390 391 /* In case of one MSI vector, we handle irq enable/disable in a 392 * uniform way since we only have one irq 393 */ 394 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 395 return; 396 397 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; 398 disable_irq_nosync(ab->irq_num[irq_idx]); 399 } 400 401 static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab) 402 { 403 int i; 404 405 clear_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); 406 407 for (i = 0; i < ab->hw_params->ce_count; i++) { 408 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 409 continue; 410 ath12k_pci_ce_irq_disable(ab, i); 411 } 412 } 413 414 static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab) 415 { 416 int i; 417 int irq_idx; 418 419 for (i = 0; i < ab->hw_params->ce_count; i++) { 420 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 421 continue; 422 423 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 424 synchronize_irq(ab->irq_num[irq_idx]); 425 } 426 } 427 428 static void ath12k_pci_ce_tasklet(struct tasklet_struct *t) 429 { 430 struct ath12k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq); 431 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; 432 433 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 434 435 enable_irq(ce_pipe->ab->irq_num[irq_idx]); 436 } 437 438 static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg) 439 { 440 struct ath12k_ce_pipe *ce_pipe = arg; 441 struct ath12k_base *ab = ce_pipe->ab; 442 int irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; 443 444 if (!test_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags)) 445 return IRQ_HANDLED; 446 447 /* last interrupt received for this CE */ 448 ce_pipe->timestamp = jiffies; 449 450 disable_irq_nosync(ab->irq_num[irq_idx]); 451 452 tasklet_schedule(&ce_pipe->intr_tq); 453 454 return IRQ_HANDLED; 455 } 456 457 static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp) 458 { 459 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab); 460 int i; 461 462 /* In case of one MSI vector, we handle irq enable/disable 463 * in a uniform way since we only have one irq 464 */ 465 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 466 return; 467 468 for (i = 0; i < irq_grp->num_irq; i++) 469 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 470 } 471 472 static void __ath12k_pci_ext_irq_disable(struct ath12k_base *ab) 473 { 474 int i; 475 476 clear_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); 477 478 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 479 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 480 481 ath12k_pci_ext_grp_disable(irq_grp); 482 483 napi_synchronize(&irq_grp->napi); 484 napi_disable(&irq_grp->napi); 485 } 486 } 487 488 static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp) 489 { 490 struct ath12k_pci *ab_pci = ath12k_pci_priv(irq_grp->ab); 491 int i; 492 493 /* In case of one MSI vector, we handle irq enable/disable in a 494 * uniform way since we only have one irq 495 */ 496 if (!test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 497 return; 498 499 for (i = 0; i < irq_grp->num_irq; i++) 500 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 501 } 502 503 static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab) 504 { 505 int i, j, irq_idx; 506 507 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 508 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 509 510 for (j = 0; j < irq_grp->num_irq; j++) { 511 irq_idx = irq_grp->irqs[j]; 512 synchronize_irq(ab->irq_num[irq_idx]); 513 } 514 } 515 } 516 517 static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) 518 { 519 struct ath12k_ext_irq_grp *irq_grp = container_of(napi, 520 struct ath12k_ext_irq_grp, 521 napi); 522 struct ath12k_base *ab = irq_grp->ab; 523 int work_done; 524 int i; 525 526 work_done = ath12k_dp_service_srng(ab, irq_grp, budget); 527 if (work_done < budget) { 528 napi_complete_done(napi, work_done); 529 for (i = 0; i < irq_grp->num_irq; i++) 530 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 531 } 532 533 if (work_done > budget) 534 work_done = budget; 535 536 return work_done; 537 } 538 539 static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg) 540 { 541 struct ath12k_ext_irq_grp *irq_grp = arg; 542 struct ath12k_base *ab = irq_grp->ab; 543 int i; 544 545 if (!test_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) 546 return IRQ_HANDLED; 547 548 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq); 549 550 /* last interrupt received for this group */ 551 irq_grp->timestamp = jiffies; 552 553 for (i = 0; i < irq_grp->num_irq; i++) 554 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 555 556 napi_schedule(&irq_grp->napi); 557 558 return IRQ_HANDLED; 559 } 560 561 static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) 562 { 563 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 564 int i, j, ret, num_vectors = 0; 565 u32 user_base_data = 0, base_vector = 0, base_idx; 566 567 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; 568 ret = ath12k_pci_get_user_msi_assignment(ab, "DP", 569 &num_vectors, 570 &user_base_data, 571 &base_vector); 572 if (ret < 0) 573 return ret; 574 575 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 576 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 577 u32 num_irq = 0; 578 579 irq_grp->ab = ab; 580 irq_grp->grp_id = i; 581 init_dummy_netdev(&irq_grp->napi_ndev); 582 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, 583 ath12k_pci_ext_grp_napi_poll); 584 585 if (ab->hw_params->ring_mask->tx[i] || 586 ab->hw_params->ring_mask->rx[i] || 587 ab->hw_params->ring_mask->rx_err[i] || 588 ab->hw_params->ring_mask->rx_wbm_rel[i] || 589 ab->hw_params->ring_mask->reo_status[i] || 590 ab->hw_params->ring_mask->host2rxdma[i] || 591 ab->hw_params->ring_mask->rx_mon_dest[i]) { 592 num_irq = 1; 593 } 594 595 irq_grp->num_irq = num_irq; 596 irq_grp->irqs[0] = base_idx + i; 597 598 for (j = 0; j < irq_grp->num_irq; j++) { 599 int irq_idx = irq_grp->irqs[j]; 600 int vector = (i % num_vectors) + base_vector; 601 int irq = ath12k_pci_get_msi_irq(ab->dev, vector); 602 603 ab->irq_num[irq_idx] = irq; 604 605 ath12k_dbg(ab, ATH12K_DBG_PCI, 606 "irq:%d group:%d\n", irq, i); 607 608 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 609 ret = request_irq(irq, ath12k_pci_ext_interrupt_handler, 610 ab_pci->irq_flags, 611 "DP_EXT_IRQ", irq_grp); 612 if (ret) { 613 ath12k_err(ab, "failed request irq %d: %d\n", 614 vector, ret); 615 return ret; 616 } 617 } 618 ath12k_pci_ext_grp_disable(irq_grp); 619 } 620 621 return 0; 622 } 623 624 static int ath12k_pci_set_irq_affinity_hint(struct ath12k_pci *ab_pci, 625 const struct cpumask *m) 626 { 627 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 628 return 0; 629 630 return irq_set_affinity_hint(ab_pci->pdev->irq, m); 631 } 632 633 static int ath12k_pci_config_irq(struct ath12k_base *ab) 634 { 635 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 636 struct ath12k_ce_pipe *ce_pipe; 637 u32 msi_data_start; 638 u32 msi_data_count, msi_data_idx; 639 u32 msi_irq_start; 640 unsigned int msi_data; 641 int irq, i, ret, irq_idx; 642 643 ret = ath12k_pci_get_user_msi_assignment(ab, 644 "CE", &msi_data_count, 645 &msi_data_start, &msi_irq_start); 646 if (ret) 647 return ret; 648 649 /* Configure CE irqs */ 650 651 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { 652 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 653 continue; 654 655 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start; 656 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data); 657 ce_pipe = &ab->ce.ce_pipe[i]; 658 659 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 660 661 tasklet_setup(&ce_pipe->intr_tq, ath12k_pci_ce_tasklet); 662 663 ret = request_irq(irq, ath12k_pci_ce_interrupt_handler, 664 ab_pci->irq_flags, irq_name[irq_idx], 665 ce_pipe); 666 if (ret) { 667 ath12k_err(ab, "failed to request irq %d: %d\n", 668 irq_idx, ret); 669 return ret; 670 } 671 672 ab->irq_num[irq_idx] = irq; 673 msi_data_idx++; 674 675 ath12k_pci_ce_irq_disable(ab, i); 676 } 677 678 ret = ath12k_pci_ext_irq_config(ab); 679 if (ret) 680 return ret; 681 682 return 0; 683 } 684 685 static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab) 686 { 687 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 688 689 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 690 struct pci_bus *bus = ab_pci->pdev->bus; 691 692 cfg->tgt_ce = ab->hw_params->target_ce_config; 693 cfg->tgt_ce_len = ab->hw_params->target_ce_count; 694 695 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map; 696 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len; 697 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id; 698 699 if (test_bit(ATH12K_FW_FEATURE_MULTI_QRTR_ID, ab->fw.fw_features)) { 700 ab_pci->qmi_instance = 701 u32_encode_bits(pci_domain_nr(bus), DOMAIN_NUMBER_MASK) | 702 u32_encode_bits(bus->number, BUS_NUMBER_MASK); 703 ab->qmi.service_ins_id += ab_pci->qmi_instance; 704 } 705 } 706 707 static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab) 708 { 709 int i; 710 711 set_bit(ATH12K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); 712 713 for (i = 0; i < ab->hw_params->ce_count; i++) { 714 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 715 continue; 716 ath12k_pci_ce_irq_enable(ab, i); 717 } 718 } 719 720 static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable) 721 { 722 struct pci_dev *dev = ab_pci->pdev; 723 u16 control; 724 725 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 726 727 if (enable) 728 control |= PCI_MSI_FLAGS_ENABLE; 729 else 730 control &= ~PCI_MSI_FLAGS_ENABLE; 731 732 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 733 } 734 735 static void ath12k_pci_msi_enable(struct ath12k_pci *ab_pci) 736 { 737 ath12k_pci_msi_config(ab_pci, true); 738 } 739 740 static void ath12k_pci_msi_disable(struct ath12k_pci *ab_pci) 741 { 742 ath12k_pci_msi_config(ab_pci, false); 743 } 744 745 static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci) 746 { 747 struct ath12k_base *ab = ab_pci->ab; 748 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; 749 struct msi_desc *msi_desc; 750 int num_vectors; 751 int ret; 752 753 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 754 msi_config->total_vectors, 755 msi_config->total_vectors, 756 PCI_IRQ_MSI); 757 758 if (num_vectors == msi_config->total_vectors) { 759 set_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); 760 ab_pci->irq_flags = IRQF_SHARED; 761 } else { 762 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 763 1, 764 1, 765 PCI_IRQ_MSI); 766 if (num_vectors < 0) { 767 ret = -EINVAL; 768 goto reset_msi_config; 769 } 770 clear_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags); 771 ab_pci->msi_config = &msi_config_one_msi; 772 ab_pci->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 773 ath12k_dbg(ab, ATH12K_DBG_PCI, "request MSI one vector\n"); 774 } 775 776 ath12k_info(ab, "MSI vectors: %d\n", num_vectors); 777 778 ath12k_pci_msi_disable(ab_pci); 779 780 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 781 if (!msi_desc) { 782 ath12k_err(ab, "msi_desc is NULL!\n"); 783 ret = -EINVAL; 784 goto free_msi_vector; 785 } 786 787 ab_pci->msi_ep_base_data = msi_desc->msg.data; 788 if (msi_desc->pci.msi_attrib.is_64) 789 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); 790 791 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); 792 793 return 0; 794 795 free_msi_vector: 796 pci_free_irq_vectors(ab_pci->pdev); 797 798 reset_msi_config: 799 return ret; 800 } 801 802 static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci) 803 { 804 pci_free_irq_vectors(ab_pci->pdev); 805 } 806 807 static int ath12k_pci_config_msi_data(struct ath12k_pci *ab_pci) 808 { 809 struct msi_desc *msi_desc; 810 811 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 812 if (!msi_desc) { 813 ath12k_err(ab_pci->ab, "msi_desc is NULL!\n"); 814 pci_free_irq_vectors(ab_pci->pdev); 815 return -EINVAL; 816 } 817 818 ab_pci->msi_ep_base_data = msi_desc->msg.data; 819 820 ath12k_dbg(ab_pci->ab, ATH12K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n", 821 ab_pci->msi_ep_base_data); 822 823 return 0; 824 } 825 826 static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev) 827 { 828 struct ath12k_base *ab = ab_pci->ab; 829 u16 device_id; 830 int ret = 0; 831 832 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 833 if (device_id != ab_pci->dev_id) { 834 ath12k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 835 device_id, ab_pci->dev_id); 836 ret = -EIO; 837 goto out; 838 } 839 840 ret = pci_assign_resource(pdev, ATH12K_PCI_BAR_NUM); 841 if (ret) { 842 ath12k_err(ab, "failed to assign pci resource: %d\n", ret); 843 goto out; 844 } 845 846 ret = pci_enable_device(pdev); 847 if (ret) { 848 ath12k_err(ab, "failed to enable pci device: %d\n", ret); 849 goto out; 850 } 851 852 ret = pci_request_region(pdev, ATH12K_PCI_BAR_NUM, "ath12k_pci"); 853 if (ret) { 854 ath12k_err(ab, "failed to request pci region: %d\n", ret); 855 goto disable_device; 856 } 857 858 ret = dma_set_mask_and_coherent(&pdev->dev, 859 DMA_BIT_MASK(ATH12K_PCI_DMA_MASK)); 860 if (ret) { 861 ath12k_err(ab, "failed to set pci dma mask to %d: %d\n", 862 ATH12K_PCI_DMA_MASK, ret); 863 goto release_region; 864 } 865 866 pci_set_master(pdev); 867 868 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM); 869 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0); 870 if (!ab->mem) { 871 ath12k_err(ab, "failed to map pci bar %d\n", ATH12K_PCI_BAR_NUM); 872 ret = -EIO; 873 goto release_region; 874 } 875 876 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); 877 return 0; 878 879 release_region: 880 pci_release_region(pdev, ATH12K_PCI_BAR_NUM); 881 disable_device: 882 pci_disable_device(pdev); 883 out: 884 return ret; 885 } 886 887 static void ath12k_pci_free_region(struct ath12k_pci *ab_pci) 888 { 889 struct ath12k_base *ab = ab_pci->ab; 890 struct pci_dev *pci_dev = ab_pci->pdev; 891 892 pci_iounmap(pci_dev, ab->mem); 893 ab->mem = NULL; 894 pci_release_region(pci_dev, ATH12K_PCI_BAR_NUM); 895 if (pci_is_enabled(pci_dev)) 896 pci_disable_device(pci_dev); 897 } 898 899 static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci) 900 { 901 struct ath12k_base *ab = ab_pci->ab; 902 903 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 904 &ab_pci->link_ctl); 905 906 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", 907 ab_pci->link_ctl, 908 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 909 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 910 911 /* disable L0s and L1 */ 912 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, 913 PCI_EXP_LNKCTL_ASPMC); 914 915 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags); 916 } 917 918 static void ath12k_pci_update_qrtr_node_id(struct ath12k_base *ab) 919 { 920 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 921 u32 reg; 922 923 /* On platforms with two or more identical mhi devices, qmi service run 924 * with identical qrtr-node-id. Because of this identical ID qrtr-lookup 925 * cannot register more than one qmi service with identical node ID. 926 * 927 * This generates a unique instance ID from PCIe domain number and bus number, 928 * writes to the given register, it is available for firmware when the QMI service 929 * is spawned. 930 */ 931 reg = PCIE_LOCAL_REG_QRTR_NODE_ID & WINDOW_RANGE_MASK; 932 ath12k_pci_write32(ab, reg, ab_pci->qmi_instance); 933 934 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci reg 0x%x instance 0x%x read val 0x%x\n", 935 reg, ab_pci->qmi_instance, ath12k_pci_read32(ab, reg)); 936 } 937 938 static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci) 939 { 940 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) 941 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, 942 PCI_EXP_LNKCTL_ASPMC, 943 ab_pci->link_ctl & 944 PCI_EXP_LNKCTL_ASPMC); 945 } 946 947 static void ath12k_pci_kill_tasklets(struct ath12k_base *ab) 948 { 949 int i; 950 951 for (i = 0; i < ab->hw_params->ce_count; i++) { 952 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 953 954 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 955 continue; 956 957 tasklet_kill(&ce_pipe->intr_tq); 958 } 959 } 960 961 static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab) 962 { 963 ath12k_pci_ce_irqs_disable(ab); 964 ath12k_pci_sync_ce_irqs(ab); 965 ath12k_pci_kill_tasklets(ab); 966 } 967 968 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, 969 u8 *ul_pipe, u8 *dl_pipe) 970 { 971 const struct service_to_pipe *entry; 972 bool ul_set = false, dl_set = false; 973 int i; 974 975 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) { 976 entry = &ab->hw_params->svc_to_ce_map[i]; 977 978 if (__le32_to_cpu(entry->service_id) != service_id) 979 continue; 980 981 switch (__le32_to_cpu(entry->pipedir)) { 982 case PIPEDIR_NONE: 983 break; 984 case PIPEDIR_IN: 985 WARN_ON(dl_set); 986 *dl_pipe = __le32_to_cpu(entry->pipenum); 987 dl_set = true; 988 break; 989 case PIPEDIR_OUT: 990 WARN_ON(ul_set); 991 *ul_pipe = __le32_to_cpu(entry->pipenum); 992 ul_set = true; 993 break; 994 case PIPEDIR_INOUT: 995 WARN_ON(dl_set); 996 WARN_ON(ul_set); 997 *dl_pipe = __le32_to_cpu(entry->pipenum); 998 *ul_pipe = __le32_to_cpu(entry->pipenum); 999 dl_set = true; 1000 ul_set = true; 1001 break; 1002 } 1003 } 1004 1005 if (WARN_ON(!ul_set || !dl_set)) 1006 return -ENOENT; 1007 1008 return 0; 1009 } 1010 1011 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector) 1012 { 1013 struct pci_dev *pci_dev = to_pci_dev(dev); 1014 1015 return pci_irq_vector(pci_dev, vector); 1016 } 1017 1018 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, 1019 int *num_vectors, u32 *user_base_data, 1020 u32 *base_vector) 1021 { 1022 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1023 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; 1024 int idx; 1025 1026 for (idx = 0; idx < msi_config->total_users; idx++) { 1027 if (strcmp(user_name, msi_config->users[idx].name) == 0) { 1028 *num_vectors = msi_config->users[idx].num_vectors; 1029 *base_vector = msi_config->users[idx].base_vector; 1030 *user_base_data = *base_vector + ab_pci->msi_ep_base_data; 1031 1032 ath12k_dbg(ab, ATH12K_DBG_PCI, 1033 "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", 1034 user_name, *num_vectors, *user_base_data, 1035 *base_vector); 1036 1037 return 0; 1038 } 1039 } 1040 1041 ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); 1042 1043 return -EINVAL; 1044 } 1045 1046 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo, 1047 u32 *msi_addr_hi) 1048 { 1049 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1050 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 1051 1052 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 1053 msi_addr_lo); 1054 1055 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { 1056 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 1057 msi_addr_hi); 1058 } else { 1059 *msi_addr_hi = 0; 1060 } 1061 } 1062 1063 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id, 1064 u32 *msi_idx) 1065 { 1066 u32 i, msi_data_idx; 1067 1068 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { 1069 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 1070 continue; 1071 1072 if (ce_id == i) 1073 break; 1074 1075 msi_data_idx++; 1076 } 1077 *msi_idx = msi_data_idx; 1078 } 1079 1080 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab) 1081 { 1082 ath12k_pci_ce_irqs_enable(ab); 1083 } 1084 1085 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab) 1086 { 1087 ath12k_pci_ce_irq_disable_sync(ab); 1088 } 1089 1090 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab) 1091 { 1092 int i; 1093 1094 set_bit(ATH12K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); 1095 1096 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 1097 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 1098 1099 napi_enable(&irq_grp->napi); 1100 ath12k_pci_ext_grp_enable(irq_grp); 1101 } 1102 } 1103 1104 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab) 1105 { 1106 __ath12k_pci_ext_irq_disable(ab); 1107 ath12k_pci_sync_ext_irqs(ab); 1108 } 1109 1110 int ath12k_pci_hif_suspend(struct ath12k_base *ab) 1111 { 1112 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab); 1113 1114 ath12k_mhi_suspend(ar_pci); 1115 1116 return 0; 1117 } 1118 1119 int ath12k_pci_hif_resume(struct ath12k_base *ab) 1120 { 1121 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab); 1122 1123 ath12k_mhi_resume(ar_pci); 1124 1125 return 0; 1126 } 1127 1128 void ath12k_pci_stop(struct ath12k_base *ab) 1129 { 1130 ath12k_pci_ce_irq_disable_sync(ab); 1131 ath12k_ce_cleanup_pipes(ab); 1132 } 1133 1134 int ath12k_pci_start(struct ath12k_base *ab) 1135 { 1136 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1137 1138 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1139 1140 if (test_bit(ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 1141 ath12k_pci_aspm_restore(ab_pci); 1142 else 1143 ath12k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n"); 1144 1145 ath12k_pci_ce_irqs_enable(ab); 1146 ath12k_ce_rx_post_buf(ab); 1147 1148 return 0; 1149 } 1150 1151 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset) 1152 { 1153 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1154 u32 val, window_start; 1155 int ret = 0; 1156 1157 /* for offset beyond BAR + 4K - 32, may 1158 * need to wakeup MHI to access. 1159 */ 1160 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1161 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) 1162 ret = ab_pci->pci_ops->wakeup(ab); 1163 1164 if (offset < WINDOW_START) { 1165 val = ioread32(ab->mem + offset); 1166 } else { 1167 if (ab->static_window_map) 1168 window_start = ath12k_pci_get_window_start(ab, offset); 1169 else 1170 window_start = WINDOW_START; 1171 1172 if (window_start == WINDOW_START) { 1173 spin_lock_bh(&ab_pci->window_lock); 1174 ath12k_pci_select_window(ab_pci, offset); 1175 val = ioread32(ab->mem + window_start + 1176 (offset & WINDOW_RANGE_MASK)); 1177 spin_unlock_bh(&ab_pci->window_lock); 1178 } else { 1179 if ((!window_start) && 1180 (offset >= PCI_MHIREGLEN_REG && 1181 offset <= PCI_MHI_REGION_END)) 1182 offset = offset - PCI_MHIREGLEN_REG; 1183 1184 val = ioread32(ab->mem + window_start + 1185 (offset & WINDOW_RANGE_MASK)); 1186 } 1187 } 1188 1189 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1190 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && 1191 !ret) 1192 ab_pci->pci_ops->release(ab); 1193 return val; 1194 } 1195 1196 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value) 1197 { 1198 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1199 u32 window_start; 1200 int ret = 0; 1201 1202 /* for offset beyond BAR + 4K - 32, may 1203 * need to wakeup MHI to access. 1204 */ 1205 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1206 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) 1207 ret = ab_pci->pci_ops->wakeup(ab); 1208 1209 if (offset < WINDOW_START) { 1210 iowrite32(value, ab->mem + offset); 1211 } else { 1212 if (ab->static_window_map) 1213 window_start = ath12k_pci_get_window_start(ab, offset); 1214 else 1215 window_start = WINDOW_START; 1216 1217 if (window_start == WINDOW_START) { 1218 spin_lock_bh(&ab_pci->window_lock); 1219 ath12k_pci_select_window(ab_pci, offset); 1220 iowrite32(value, ab->mem + window_start + 1221 (offset & WINDOW_RANGE_MASK)); 1222 spin_unlock_bh(&ab_pci->window_lock); 1223 } else { 1224 if ((!window_start) && 1225 (offset >= PCI_MHIREGLEN_REG && 1226 offset <= PCI_MHI_REGION_END)) 1227 offset = offset - PCI_MHIREGLEN_REG; 1228 1229 iowrite32(value, ab->mem + window_start + 1230 (offset & WINDOW_RANGE_MASK)); 1231 } 1232 } 1233 1234 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1235 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && 1236 !ret) 1237 ab_pci->pci_ops->release(ab); 1238 } 1239 1240 int ath12k_pci_power_up(struct ath12k_base *ab) 1241 { 1242 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1243 int ret; 1244 1245 ab_pci->register_window = 0; 1246 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1247 ath12k_pci_sw_reset(ab_pci->ab, true); 1248 1249 /* Disable ASPM during firmware download due to problems switching 1250 * to AMSS state. 1251 */ 1252 ath12k_pci_aspm_disable(ab_pci); 1253 1254 ath12k_pci_msi_enable(ab_pci); 1255 1256 if (test_bit(ATH12K_FW_FEATURE_MULTI_QRTR_ID, ab->fw.fw_features)) 1257 ath12k_pci_update_qrtr_node_id(ab); 1258 1259 ret = ath12k_mhi_start(ab_pci); 1260 if (ret) { 1261 ath12k_err(ab, "failed to start mhi: %d\n", ret); 1262 return ret; 1263 } 1264 1265 if (ab->static_window_map) 1266 ath12k_pci_select_static_window(ab_pci); 1267 1268 return 0; 1269 } 1270 1271 void ath12k_pci_power_down(struct ath12k_base *ab) 1272 { 1273 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1274 1275 /* restore aspm in case firmware bootup fails */ 1276 ath12k_pci_aspm_restore(ab_pci); 1277 1278 ath12k_pci_force_wake(ab_pci->ab); 1279 ath12k_pci_msi_disable(ab_pci); 1280 ath12k_mhi_stop(ab_pci); 1281 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1282 ath12k_pci_sw_reset(ab_pci->ab, false); 1283 } 1284 1285 static const struct ath12k_hif_ops ath12k_pci_hif_ops = { 1286 .start = ath12k_pci_start, 1287 .stop = ath12k_pci_stop, 1288 .read32 = ath12k_pci_read32, 1289 .write32 = ath12k_pci_write32, 1290 .power_down = ath12k_pci_power_down, 1291 .power_up = ath12k_pci_power_up, 1292 .suspend = ath12k_pci_hif_suspend, 1293 .resume = ath12k_pci_hif_resume, 1294 .irq_enable = ath12k_pci_ext_irq_enable, 1295 .irq_disable = ath12k_pci_ext_irq_disable, 1296 .get_msi_address = ath12k_pci_get_msi_address, 1297 .get_user_msi_vector = ath12k_pci_get_user_msi_assignment, 1298 .map_service_to_pipe = ath12k_pci_map_service_to_pipe, 1299 .ce_irq_enable = ath12k_pci_hif_ce_irq_enable, 1300 .ce_irq_disable = ath12k_pci_hif_ce_irq_disable, 1301 .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx, 1302 }; 1303 1304 static 1305 void ath12k_pci_read_hw_version(struct ath12k_base *ab, u32 *major, u32 *minor) 1306 { 1307 u32 soc_hw_version; 1308 1309 soc_hw_version = ath12k_pci_read32(ab, TCSR_SOC_HW_VERSION); 1310 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 1311 soc_hw_version); 1312 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 1313 soc_hw_version); 1314 1315 ath12k_dbg(ab, ATH12K_DBG_PCI, 1316 "pci tcsr_soc_hw_version major %d minor %d\n", 1317 *major, *minor); 1318 } 1319 1320 static int ath12k_pci_probe(struct pci_dev *pdev, 1321 const struct pci_device_id *pci_dev) 1322 { 1323 struct ath12k_base *ab; 1324 struct ath12k_pci *ab_pci; 1325 u32 soc_hw_version_major, soc_hw_version_minor; 1326 int ret; 1327 1328 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI); 1329 if (!ab) { 1330 dev_err(&pdev->dev, "failed to allocate ath12k base\n"); 1331 return -ENOMEM; 1332 } 1333 1334 ab->dev = &pdev->dev; 1335 pci_set_drvdata(pdev, ab); 1336 ab_pci = ath12k_pci_priv(ab); 1337 ab_pci->dev_id = pci_dev->device; 1338 ab_pci->ab = ab; 1339 ab_pci->pdev = pdev; 1340 ab->hif.ops = &ath12k_pci_hif_ops; 1341 pci_set_drvdata(pdev, ab); 1342 spin_lock_init(&ab_pci->window_lock); 1343 1344 ret = ath12k_pci_claim(ab_pci, pdev); 1345 if (ret) { 1346 ath12k_err(ab, "failed to claim device: %d\n", ret); 1347 goto err_free_core; 1348 } 1349 1350 ath12k_dbg(ab, ATH12K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 1351 pdev->vendor, pdev->device, 1352 pdev->subsystem_vendor, pdev->subsystem_device); 1353 1354 ab->id.vendor = pdev->vendor; 1355 ab->id.device = pdev->device; 1356 ab->id.subsystem_vendor = pdev->subsystem_vendor; 1357 ab->id.subsystem_device = pdev->subsystem_device; 1358 1359 switch (pci_dev->device) { 1360 case QCN9274_DEVICE_ID: 1361 ab_pci->msi_config = &ath12k_msi_config[0]; 1362 ab->static_window_map = true; 1363 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274; 1364 ath12k_pci_read_hw_version(ab, &soc_hw_version_major, 1365 &soc_hw_version_minor); 1366 switch (soc_hw_version_major) { 1367 case ATH12K_PCI_SOC_HW_VERSION_2: 1368 ab->hw_rev = ATH12K_HW_QCN9274_HW20; 1369 break; 1370 case ATH12K_PCI_SOC_HW_VERSION_1: 1371 ab->hw_rev = ATH12K_HW_QCN9274_HW10; 1372 break; 1373 default: 1374 dev_err(&pdev->dev, 1375 "Unknown hardware version found for QCN9274: 0x%x\n", 1376 soc_hw_version_major); 1377 ret = -EOPNOTSUPP; 1378 goto err_pci_free_region; 1379 } 1380 break; 1381 case WCN7850_DEVICE_ID: 1382 ab->id.bdf_search = ATH12K_BDF_SEARCH_BUS_AND_BOARD; 1383 ab_pci->msi_config = &ath12k_msi_config[0]; 1384 ab->static_window_map = false; 1385 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850; 1386 ath12k_pci_read_hw_version(ab, &soc_hw_version_major, 1387 &soc_hw_version_minor); 1388 switch (soc_hw_version_major) { 1389 case ATH12K_PCI_SOC_HW_VERSION_2: 1390 ab->hw_rev = ATH12K_HW_WCN7850_HW20; 1391 break; 1392 default: 1393 dev_err(&pdev->dev, 1394 "Unknown hardware version found for WCN7850: 0x%x\n", 1395 soc_hw_version_major); 1396 ret = -EOPNOTSUPP; 1397 goto err_pci_free_region; 1398 } 1399 break; 1400 1401 default: 1402 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 1403 pci_dev->device); 1404 ret = -EOPNOTSUPP; 1405 goto err_pci_free_region; 1406 } 1407 1408 ret = ath12k_pci_msi_alloc(ab_pci); 1409 if (ret) { 1410 ath12k_err(ab, "failed to alloc msi: %d\n", ret); 1411 goto err_pci_free_region; 1412 } 1413 1414 ret = ath12k_core_pre_init(ab); 1415 if (ret) 1416 goto err_pci_msi_free; 1417 1418 ret = ath12k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); 1419 if (ret) { 1420 ath12k_err(ab, "failed to set irq affinity %d\n", ret); 1421 goto err_pci_msi_free; 1422 } 1423 1424 ret = ath12k_mhi_register(ab_pci); 1425 if (ret) { 1426 ath12k_err(ab, "failed to register mhi: %d\n", ret); 1427 goto err_irq_affinity_cleanup; 1428 } 1429 1430 ret = ath12k_hal_srng_init(ab); 1431 if (ret) 1432 goto err_mhi_unregister; 1433 1434 ret = ath12k_ce_alloc_pipes(ab); 1435 if (ret) { 1436 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret); 1437 goto err_hal_srng_deinit; 1438 } 1439 1440 ath12k_pci_init_qmi_ce_config(ab); 1441 1442 ret = ath12k_pci_config_irq(ab); 1443 if (ret) { 1444 ath12k_err(ab, "failed to config irq: %d\n", ret); 1445 goto err_ce_free; 1446 } 1447 1448 /* kernel may allocate a dummy vector before request_irq and 1449 * then allocate a real vector when request_irq is called. 1450 * So get msi_data here again to avoid spurious interrupt 1451 * as msi_data will configured to srngs. 1452 */ 1453 ret = ath12k_pci_config_msi_data(ab_pci); 1454 if (ret) { 1455 ath12k_err(ab, "failed to config msi_data: %d\n", ret); 1456 goto err_free_irq; 1457 } 1458 1459 ret = ath12k_core_init(ab); 1460 if (ret) { 1461 ath12k_err(ab, "failed to init core: %d\n", ret); 1462 goto err_free_irq; 1463 } 1464 return 0; 1465 1466 err_free_irq: 1467 ath12k_pci_free_irq(ab); 1468 1469 err_ce_free: 1470 ath12k_ce_free_pipes(ab); 1471 1472 err_hal_srng_deinit: 1473 ath12k_hal_srng_deinit(ab); 1474 1475 err_mhi_unregister: 1476 ath12k_mhi_unregister(ab_pci); 1477 1478 err_pci_msi_free: 1479 ath12k_pci_msi_free(ab_pci); 1480 1481 err_irq_affinity_cleanup: 1482 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1483 1484 err_pci_free_region: 1485 ath12k_pci_free_region(ab_pci); 1486 1487 err_free_core: 1488 ath12k_core_free(ab); 1489 1490 return ret; 1491 } 1492 1493 static void ath12k_pci_remove(struct pci_dev *pdev) 1494 { 1495 struct ath12k_base *ab = pci_get_drvdata(pdev); 1496 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1497 1498 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1499 1500 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1501 ath12k_pci_power_down(ab); 1502 ath12k_qmi_deinit_service(ab); 1503 goto qmi_fail; 1504 } 1505 1506 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags); 1507 1508 cancel_work_sync(&ab->reset_work); 1509 ath12k_core_deinit(ab); 1510 1511 qmi_fail: 1512 ath12k_mhi_unregister(ab_pci); 1513 1514 ath12k_pci_free_irq(ab); 1515 ath12k_pci_msi_free(ab_pci); 1516 ath12k_pci_free_region(ab_pci); 1517 1518 ath12k_hal_srng_deinit(ab); 1519 ath12k_ce_free_pipes(ab); 1520 ath12k_core_free(ab); 1521 } 1522 1523 static void ath12k_pci_shutdown(struct pci_dev *pdev) 1524 { 1525 struct ath12k_base *ab = pci_get_drvdata(pdev); 1526 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1527 1528 ath12k_pci_set_irq_affinity_hint(ab_pci, NULL); 1529 ath12k_pci_power_down(ab); 1530 } 1531 1532 static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev) 1533 { 1534 struct ath12k_base *ab = dev_get_drvdata(dev); 1535 int ret; 1536 1537 ret = ath12k_core_suspend(ab); 1538 if (ret) 1539 ath12k_warn(ab, "failed to suspend core: %d\n", ret); 1540 1541 return ret; 1542 } 1543 1544 static __maybe_unused int ath12k_pci_pm_resume(struct device *dev) 1545 { 1546 struct ath12k_base *ab = dev_get_drvdata(dev); 1547 int ret; 1548 1549 ret = ath12k_core_resume(ab); 1550 if (ret) 1551 ath12k_warn(ab, "failed to resume core: %d\n", ret); 1552 1553 return ret; 1554 } 1555 1556 static SIMPLE_DEV_PM_OPS(ath12k_pci_pm_ops, 1557 ath12k_pci_pm_suspend, 1558 ath12k_pci_pm_resume); 1559 1560 static struct pci_driver ath12k_pci_driver = { 1561 .name = "ath12k_pci", 1562 .id_table = ath12k_pci_id_table, 1563 .probe = ath12k_pci_probe, 1564 .remove = ath12k_pci_remove, 1565 .shutdown = ath12k_pci_shutdown, 1566 .driver.pm = &ath12k_pci_pm_ops, 1567 }; 1568 1569 static int ath12k_pci_init(void) 1570 { 1571 int ret; 1572 1573 ret = pci_register_driver(&ath12k_pci_driver); 1574 if (ret) { 1575 pr_err("failed to register ath12k pci driver: %d\n", 1576 ret); 1577 return ret; 1578 } 1579 1580 return 0; 1581 } 1582 module_init(ath12k_pci_init); 1583 1584 static void ath12k_pci_exit(void) 1585 { 1586 pci_unregister_driver(&ath12k_pci_driver); 1587 } 1588 1589 module_exit(ath12k_pci_exit); 1590 1591 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11be WLAN devices"); 1592 MODULE_LICENSE("Dual BSD/GPL"); 1593