ixp4xx_hss.c (d2ca24ee9fd83666538c189330a07b90bbcf58b3) ixp4xx_hss.c (09aa9aabdcc4966270b031816a16d4641fb45dfa)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
4 *
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/platform_data/wan_ixp4xx_hss.h>
21#include <linux/poll.h>
22#include <linux/slab.h>
23#include <linux/soc/ixp4xx/npe.h>
24#include <linux/soc/ixp4xx/qmgr.h>
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
4 *
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/platform_data/wan_ixp4xx_hss.h>
21#include <linux/poll.h>
22#include <linux/slab.h>
23#include <linux/soc/ixp4xx/npe.h>
24#include <linux/soc/ixp4xx/qmgr.h>
25#include <linux/soc/ixp4xx/cpu.h>
25
26#define DEBUG_DESC 0
27#define DEBUG_RX 0
28#define DEBUG_TX 0
29#define DEBUG_PKT_BYTES 0
30#define DEBUG_CLOSE 0
31
32#define DRV_NAME "ixp4xx_hss"

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78#define NPE_PKT_MODE_56KMODE 2
79#define NPE_PKT_MODE_56KENDIAN_MSB 4
80
81/* PKT_PIPE_HDLC_CFG_WRITE flags */
82#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
83#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
84#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
85
26
27#define DEBUG_DESC 0
28#define DEBUG_RX 0
29#define DEBUG_TX 0
30#define DEBUG_PKT_BYTES 0
31#define DEBUG_CLOSE 0
32
33#define DRV_NAME "ixp4xx_hss"

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79#define NPE_PKT_MODE_56KMODE 2
80#define NPE_PKT_MODE_56KENDIAN_MSB 4
81
82/* PKT_PIPE_HDLC_CFG_WRITE flags */
83#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
84#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
85#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
86
87
86/* hss_config, PCRs */
87/* Frame sync sampling, default = active low */
88#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
89#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
90#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
91
92/* Frame sync pin: input (default) or output generated off a given clk edge */
93#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000

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144#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
145
146/* default = no loopback */
147#define CCR_LOOPBACK 0x02000000
148
149/* HSS number, default = 0 (first) */
150#define CCR_SECOND_HSS 0x01000000
151
88/* hss_config, PCRs */
89/* Frame sync sampling, default = active low */
90#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
91#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
92#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
93
94/* Frame sync pin: input (default) or output generated off a given clk edge */
95#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000

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146#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
147
148/* default = no loopback */
149#define CCR_LOOPBACK 0x02000000
150
151/* HSS number, default = 0 (first) */
152#define CCR_SECOND_HSS 0x01000000
153
154
152/* hss_config, clkCR: main:10, num:10, denom:12 */
155/* hss_config, clkCR: main:10, num:10, denom:12 */
153#define CLK42X_SPEED_EXP ((0x3FF << 22) | (2 << 12) | 15) /*65 KHz*/
156#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
154
157
155#define CLK42X_SPEED_512KHZ ((130 << 22) | (2 << 12) | 15)
156#define CLK42X_SPEED_1536KHZ ((43 << 22) | (18 << 12) | 47)
157#define CLK42X_SPEED_1544KHZ ((43 << 22) | (33 << 12) | 192)
158#define CLK42X_SPEED_2048KHZ ((32 << 22) | (34 << 12) | 63)
159#define CLK42X_SPEED_4096KHZ ((16 << 22) | (34 << 12) | 127)
160#define CLK42X_SPEED_8192KHZ ((8 << 22) | (34 << 12) | 255)
158#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
159#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
160#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
161#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
162#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
163#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
161
164
162#define CLK46X_SPEED_512KHZ ((130 << 22) | (24 << 12) | 127)
163#define CLK46X_SPEED_1536KHZ ((43 << 22) | (152 << 12) | 383)
164#define CLK46X_SPEED_1544KHZ ((43 << 22) | (66 << 12) | 385)
165#define CLK46X_SPEED_2048KHZ ((32 << 22) | (280 << 12) | 511)
166#define CLK46X_SPEED_4096KHZ ((16 << 22) | (280 << 12) | 1023)
167#define CLK46X_SPEED_8192KHZ ((8 << 22) | (280 << 12) | 2047)
165#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
166#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
167#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
168#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
169#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
170#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
168
171
169/* HSS_CONFIG_CLOCK_CR register consists of 3 parts:
172/*
173 * HSS_CONFIG_CLOCK_CR register consists of 3 parts:
170 * A (10 bits), B (10 bits) and C (12 bits).
171 * IXP42x HSS clock generator operation (verified with an oscilloscope):
172 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
173 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
174 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
175 * (A + 1) bits wide.
176 *
177 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:

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200#define HSS_CONFIG_RX_PCR 0x04
201#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
202#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
203#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
204#define HSS_CONFIG_RX_FCR 0x14
205#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
206#define HSS_CONFIG_RX_LUT 0x38
207
174 * A (10 bits), B (10 bits) and C (12 bits).
175 * IXP42x HSS clock generator operation (verified with an oscilloscope):
176 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
177 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
178 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
179 * (A + 1) bits wide.
180 *
181 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:

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204#define HSS_CONFIG_RX_PCR 0x04
205#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
206#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
207#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
208#define HSS_CONFIG_RX_FCR 0x14
209#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
210#define HSS_CONFIG_RX_LUT 0x38
211
212
208/* NPE command codes */
209/* writes the ConfigWord value to the location specified by offset */
210#define PORT_CONFIG_WRITE 0x40
211
212/* triggers the NPE to load the contents of the configuration table */
213#define PORT_CONFIG_LOAD 0x41
214
215/* triggers the NPE to return an HssErrorReadResponse message */
216#define PORT_ERROR_READ 0x42
217
218/* triggers the NPE to reset internal status and enable the HssPacketized
213/* NPE command codes */
214/* writes the ConfigWord value to the location specified by offset */
215#define PORT_CONFIG_WRITE 0x40
216
217/* triggers the NPE to load the contents of the configuration table */
218#define PORT_CONFIG_LOAD 0x41
219
220/* triggers the NPE to return an HssErrorReadResponse message */
221#define PORT_ERROR_READ 0x42
222
223/* triggers the NPE to reset internal status and enable the HssPacketized
219 * operation for the flow specified by pPipe
220 */
224 operation for the flow specified by pPipe */
221#define PKT_PIPE_FLOW_ENABLE 0x50
222#define PKT_PIPE_FLOW_DISABLE 0x51
223#define PKT_NUM_PIPES_WRITE 0x52
224#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
225#define PKT_PIPE_HDLC_CFG_WRITE 0x54
226#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
227#define PKT_PIPE_RX_SIZE_WRITE 0x56
228#define PKT_PIPE_MODE_WRITE 0x57
229
230/* HDLC packet status values - desc->status */
231#define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */
232#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
233#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
234#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
225#define PKT_PIPE_FLOW_ENABLE 0x50
226#define PKT_PIPE_FLOW_DISABLE 0x51
227#define PKT_NUM_PIPES_WRITE 0x52
228#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
229#define PKT_PIPE_HDLC_CFG_WRITE 0x54
230#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
231#define PKT_PIPE_RX_SIZE_WRITE 0x56
232#define PKT_PIPE_MODE_WRITE 0x57
233
234/* HDLC packet status values - desc->status */
235#define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */
236#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
237#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
238#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
235 * this packet (if buf_len < pkt_len)
236 */
239 this packet (if buf_len < pkt_len) */
237#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
238#define ERR_HDLC_ABORT 6 /* abort sequence received */
239#define ERR_DISCONNECTING 7 /* disconnect is in progress */
240
240#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
241#define ERR_HDLC_ABORT 6 /* abort sequence received */
242#define ERR_DISCONNECTING 7 /* disconnect is in progress */
243
244
241#ifdef __ARMEB__
242typedef struct sk_buff buffer_t;
243#define free_buffer dev_kfree_skb
244#define free_buffer_irq dev_consume_skb_irq
245#else
246typedef void buffer_t;
247#define free_buffer kfree
248#define free_buffer_irq kfree

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300 u32 data; /* pointer to data buffer in RAM */
301 u16 __reserved;
302 u8 error_count;
303 u8 status;
304#endif
305 u32 __reserved1[4];
306};
307
245#ifdef __ARMEB__
246typedef struct sk_buff buffer_t;
247#define free_buffer dev_kfree_skb
248#define free_buffer_irq dev_consume_skb_irq
249#else
250typedef void buffer_t;
251#define free_buffer kfree
252#define free_buffer_irq kfree

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304 u32 data; /* pointer to data buffer in RAM */
305 u16 __reserved;
306 u8 error_count;
307 u8 status;
308#endif
309 u32 __reserved1[4];
310};
311
312
308#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
309 (n) * sizeof(struct desc))
310#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
311
312#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
313 ((n) + RX_DESCS) * sizeof(struct desc))
314#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
315
316/*****************************************************************************
317 * global variables
318 ****************************************************************************/
319
320static int ports_open;
321static struct dma_pool *dma_pool;
322static DEFINE_SPINLOCK(npe_lock);
323
324static const struct {
325 int tx, txdone, rx, rxfree;
313#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
314 (n) * sizeof(struct desc))
315#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
316
317#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
318 ((n) + RX_DESCS) * sizeof(struct desc))
319#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
320
321/*****************************************************************************
322 * global variables
323 ****************************************************************************/
324
325static int ports_open;
326static struct dma_pool *dma_pool;
327static DEFINE_SPINLOCK(npe_lock);
328
329static const struct {
330 int tx, txdone, rx, rxfree;
326} queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
331}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
327 HSS0_PKT_RXFREE0_QUEUE},
328 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
329 HSS1_PKT_RXFREE0_QUEUE},
330};
331
332/*****************************************************************************
333 * utility functions
334 ****************************************************************************/
335
332 HSS0_PKT_RXFREE0_QUEUE},
333 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
334 HSS1_PKT_RXFREE0_QUEUE},
335};
336
337/*****************************************************************************
338 * utility functions
339 ****************************************************************************/
340
336static inline struct port *dev_to_port(struct net_device *dev)
341static inline struct port* dev_to_port(struct net_device *dev)
337{
338 return dev_to_hdlc(dev)->priv;
339}
340
341#ifndef __ARMEB__
342static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
343{
344 int i;
342{
343 return dev_to_hdlc(dev)->priv;
344}
345
346#ifndef __ARMEB__
347static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
348{
349 int i;
345
346 for (i = 0; i < cnt; i++)
347 dest[i] = swab32(src[i]);
348}
349#endif
350
351/*****************************************************************************
352 * HSS access
353 ****************************************************************************/
354
350 for (i = 0; i < cnt; i++)
351 dest[i] = swab32(src[i]);
352}
353#endif
354
355/*****************************************************************************
356 * HSS access
357 ****************************************************************************/
358
355static void hss_npe_send(struct port *port, struct msg *msg, const char *what)
359static void hss_npe_send(struct port *port, struct msg *msg, const char* what)
356{
360{
357 u32 *val = (u32 *)msg;
358
361 u32 *val = (u32*)msg;
359 if (npe_send_message(port->npe, msg, what)) {
360 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
361 port->id, val[0], val[1], npe_name(port->npe));
362 BUG();
363 }
364}
365
366static void hss_config_set_lut(struct port *port)

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506static int hss_load_firmware(struct port *port)
507{
508 struct msg msg;
509 int err;
510
511 if (port->initialized)
512 return 0;
513
362 if (npe_send_message(port->npe, msg, what)) {
363 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
364 port->id, val[0], val[1], npe_name(port->npe));
365 BUG();
366 }
367}
368
369static void hss_config_set_lut(struct port *port)

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509static int hss_load_firmware(struct port *port)
510{
511 struct msg msg;
512 int err;
513
514 if (port->initialized)
515 return 0;
516
514 if (!npe_running(port->npe)) {
515 err = npe_load_firmware(port->npe, npe_name(port->npe),
516 port->dev);
517 if (err)
518 return err;
519 }
517 if (!npe_running(port->npe) &&
518 (err = npe_load_firmware(port->npe, npe_name(port->npe),
519 port->dev)))
520 return err;
520
521 /* HDLC mode configuration */
522 memset(&msg, 0, sizeof(msg));
523 msg.cmd = PKT_NUM_PIPES_WRITE;
524 msg.hss_port = port->id;
525 msg.data8a = PKT_NUM_PIPES;
526 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
527

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562 if (i >= DEBUG_PKT_BYTES)
563 break;
564 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
565 }
566 printk("\n");
567#endif
568}
569
521
522 /* HDLC mode configuration */
523 memset(&msg, 0, sizeof(msg));
524 msg.cmd = PKT_NUM_PIPES_WRITE;
525 msg.hss_port = port->id;
526 msg.data8a = PKT_NUM_PIPES;
527 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
528

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563 if (i >= DEBUG_PKT_BYTES)
564 break;
565 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
566 }
567 printk("\n");
568#endif
569}
570
571
570static inline void debug_desc(u32 phys, struct desc *desc)
571{
572#if DEBUG_DESC
573 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
574 phys, desc->next, desc->buf_len, desc->pkt_len,
575 desc->data, desc->status, desc->error_count);
576#endif
577}
578
579static inline int queue_get_desc(unsigned int queue, struct port *port,
580 int is_tx)
581{
582 u32 phys, tab_phys, n_desc;
583 struct desc *tab;
584
572static inline void debug_desc(u32 phys, struct desc *desc)
573{
574#if DEBUG_DESC
575 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
576 phys, desc->next, desc->buf_len, desc->pkt_len,
577 desc->data, desc->status, desc->error_count);
578#endif
579}
580
581static inline int queue_get_desc(unsigned int queue, struct port *port,
582 int is_tx)
583{
584 u32 phys, tab_phys, n_desc;
585 struct desc *tab;
586
585 phys = qmgr_get_entry(queue);
586 if (!phys)
587 if (!(phys = qmgr_get_entry(queue)))
587 return -1;
588
589 BUG_ON(phys & 0x1F);
590 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
591 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
592 n_desc = (phys - tab_phys) / sizeof(struct desc);
593 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
594 debug_desc(phys, &tab[n_desc]);
595 BUG_ON(tab[n_desc].next);
596 return n_desc;
597}
598
599static inline void queue_put_desc(unsigned int queue, u32 phys,
600 struct desc *desc)
601{
602 debug_desc(phys, desc);
603 BUG_ON(phys & 0x1F);
604 qmgr_put_entry(queue, phys);
605 /* Don't check for queue overflow here, we've allocated sufficient
588 return -1;
589
590 BUG_ON(phys & 0x1F);
591 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
592 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
593 n_desc = (phys - tab_phys) / sizeof(struct desc);
594 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
595 debug_desc(phys, &tab[n_desc]);
596 BUG_ON(tab[n_desc].next);
597 return n_desc;
598}
599
600static inline void queue_put_desc(unsigned int queue, u32 phys,
601 struct desc *desc)
602{
603 debug_desc(phys, desc);
604 BUG_ON(phys & 0x1F);
605 qmgr_put_entry(queue, phys);
606 /* Don't check for queue overflow here, we've allocated sufficient
606 * length and queues >= 32 don't support this check anyway.
607 */
607 length and queues >= 32 don't support this check anyway. */
608}
609
608}
609
610
610static inline void dma_unmap_tx(struct port *port, struct desc *desc)
611{
612#ifdef __ARMEB__
613 dma_unmap_single(&port->netdev->dev, desc->data,
614 desc->buf_len, DMA_TO_DEVICE);
615#else
616 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
617 ALIGN((desc->data & 3) + desc->buf_len, 4),
618 DMA_TO_DEVICE);
619#endif
620}
621
611static inline void dma_unmap_tx(struct port *port, struct desc *desc)
612{
613#ifdef __ARMEB__
614 dma_unmap_single(&port->netdev->dev, desc->data,
615 desc->buf_len, DMA_TO_DEVICE);
616#else
617 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
618 ALIGN((desc->data & 3) + desc->buf_len, 4),
619 DMA_TO_DEVICE);
620#endif
621}
622
623
622static void hss_hdlc_set_carrier(void *pdev, int carrier)
623{
624 struct net_device *netdev = pdev;
625 struct port *port = dev_to_port(netdev);
626 unsigned long flags;
627
628 spin_lock_irqsave(&npe_lock, flags);
629 port->carrier = carrier;

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664 struct sk_buff *skb;
665 struct desc *desc;
666 int n;
667#ifdef __ARMEB__
668 struct sk_buff *temp;
669 u32 phys;
670#endif
671
624static void hss_hdlc_set_carrier(void *pdev, int carrier)
625{
626 struct net_device *netdev = pdev;
627 struct port *port = dev_to_port(netdev);
628 unsigned long flags;
629
630 spin_lock_irqsave(&npe_lock, flags);
631 port->carrier = carrier;

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666 struct sk_buff *skb;
667 struct desc *desc;
668 int n;
669#ifdef __ARMEB__
670 struct sk_buff *temp;
671 u32 phys;
672#endif
673
672 n = queue_get_desc(rxq, port, 0);
673 if (n < 0) {
674 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
674#if DEBUG_RX
675 printk(KERN_DEBUG "%s: hss_hdlc_poll"
676 " napi_complete\n", dev->name);
677#endif
678 napi_complete(napi);
679 qmgr_enable_irq(rxq);
680 if (!qmgr_stat_empty(rxq) &&
681 napi_reschedule(napi)) {

--- 18 unchanged lines hidden (view full) ---

700 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
701 " errors %u\n", dev->name, desc->status,
702 desc->error_count);
703#endif
704 skb = NULL;
705 switch (desc->status) {
706 case 0:
707#ifdef __ARMEB__
675#if DEBUG_RX
676 printk(KERN_DEBUG "%s: hss_hdlc_poll"
677 " napi_complete\n", dev->name);
678#endif
679 napi_complete(napi);
680 qmgr_enable_irq(rxq);
681 if (!qmgr_stat_empty(rxq) &&
682 napi_reschedule(napi)) {

--- 18 unchanged lines hidden (view full) ---

701 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
702 " errors %u\n", dev->name, desc->status,
703 desc->error_count);
704#endif
705 skb = NULL;
706 switch (desc->status) {
707 case 0:
708#ifdef __ARMEB__
708 skb = netdev_alloc_skb(dev, RX_SIZE);
709 if (skb) {
709 if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
710 phys = dma_map_single(&dev->dev, skb->data,
711 RX_SIZE,
712 DMA_FROM_DEVICE);
713 if (dma_mapping_error(&dev->dev, phys)) {
714 dev_kfree_skb(skb);
715 skb = NULL;
716 }
717 }

--- 62 unchanged lines hidden (view full) ---

780 received++;
781 }
782#if DEBUG_RX
783 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
784#endif
785 return received; /* not all work done */
786}
787
710 phys = dma_map_single(&dev->dev, skb->data,
711 RX_SIZE,
712 DMA_FROM_DEVICE);
713 if (dma_mapping_error(&dev->dev, phys)) {
714 dev_kfree_skb(skb);
715 skb = NULL;
716 }
717 }

--- 62 unchanged lines hidden (view full) ---

780 received++;
781 }
782#if DEBUG_RX
783 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
784#endif
785 return received; /* not all work done */
786}
787
788
788static void hss_hdlc_txdone_irq(void *pdev)
789{
790 struct net_device *dev = pdev;
791 struct port *port = dev_to_port(dev);
792 int n_desc;
793
794#if DEBUG_TX
795 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");

--- 53 unchanged lines hidden (view full) ---

849 len = skb->len;
850#ifdef __ARMEB__
851 offset = 0; /* no need to keep alignment */
852 bytes = len;
853 mem = skb->data;
854#else
855 offset = (int)skb->data & 3; /* keep 32-bit alignment */
856 bytes = ALIGN(offset + len, 4);
789static void hss_hdlc_txdone_irq(void *pdev)
790{
791 struct net_device *dev = pdev;
792 struct port *port = dev_to_port(dev);
793 int n_desc;
794
795#if DEBUG_TX
796 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");

--- 53 unchanged lines hidden (view full) ---

850 len = skb->len;
851#ifdef __ARMEB__
852 offset = 0; /* no need to keep alignment */
853 bytes = len;
854 mem = skb->data;
855#else
856 offset = (int)skb->data & 3; /* keep 32-bit alignment */
857 bytes = ALIGN(offset + len, 4);
857 mem = kmalloc(bytes, GFP_ATOMIC);
858 if (!mem) {
858 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
859 dev_kfree_skb(skb);
860 dev->stats.tx_dropped++;
861 return NETDEV_TX_OK;
862 }
863 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
864 dev_kfree_skb(skb);
865#endif
866

--- 39 unchanged lines hidden (view full) ---

906 }
907
908#if DEBUG_TX
909 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
910#endif
911 return NETDEV_TX_OK;
912}
913
859 dev_kfree_skb(skb);
860 dev->stats.tx_dropped++;
861 return NETDEV_TX_OK;
862 }
863 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
864 dev_kfree_skb(skb);
865#endif
866

--- 39 unchanged lines hidden (view full) ---

906 }
907
908#if DEBUG_TX
909 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
910#endif
911 return NETDEV_TX_OK;
912}
913
914
914static int request_hdlc_queues(struct port *port)
915{
916 int err;
917
918 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
919 "%s:RX-free", port->netdev->name);
920 if (err)
921 return err;

--- 47 unchanged lines hidden (view full) ---

969
970 if (!ports_open) {
971 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
972 POOL_ALLOC_SIZE, 32, 0);
973 if (!dma_pool)
974 return -ENOMEM;
975 }
976
915static int request_hdlc_queues(struct port *port)
916{
917 int err;
918
919 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
920 "%s:RX-free", port->netdev->name);
921 if (err)
922 return err;

--- 47 unchanged lines hidden (view full) ---

970
971 if (!ports_open) {
972 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
973 POOL_ALLOC_SIZE, 32, 0);
974 if (!dma_pool)
975 return -ENOMEM;
976 }
977
977 port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
978 &port->desc_tab_phys);
979 if (!port->desc_tab)
978 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
979 &port->desc_tab_phys)))
980 return -ENOMEM;
981 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
982 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
983 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
984
985 /* Setup RX buffers */
986 for (i = 0; i < RX_DESCS; i++) {
987 struct desc *desc = rx_desc_ptr(port, i);
988 buffer_t *buff;
989 void *data;
990#ifdef __ARMEB__
980 return -ENOMEM;
981 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
982 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
983 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
984
985 /* Setup RX buffers */
986 for (i = 0; i < RX_DESCS; i++) {
987 struct desc *desc = rx_desc_ptr(port, i);
988 buffer_t *buff;
989 void *data;
990#ifdef __ARMEB__
991 buff = netdev_alloc_skb(port->netdev, RX_SIZE);
992 if (!buff)
991 if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
993 return -ENOMEM;
994 data = buff->data;
995#else
992 return -ENOMEM;
993 data = buff->data;
994#else
996 buff = kmalloc(RX_SIZE, GFP_KERNEL);
997 if (!buff)
995 if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
998 return -ENOMEM;
999 data = buff;
1000#endif
1001 desc->buf_len = RX_SIZE;
1002 desc->data = dma_map_single(&port->netdev->dev, data,
1003 RX_SIZE, DMA_FROM_DEVICE);
1004 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1005 free_buffer(buff);

--- 8 unchanged lines hidden (view full) ---

1014static void destroy_hdlc_queues(struct port *port)
1015{
1016 int i;
1017
1018 if (port->desc_tab) {
1019 for (i = 0; i < RX_DESCS; i++) {
1020 struct desc *desc = rx_desc_ptr(port, i);
1021 buffer_t *buff = port->rx_buff_tab[i];
996 return -ENOMEM;
997 data = buff;
998#endif
999 desc->buf_len = RX_SIZE;
1000 desc->data = dma_map_single(&port->netdev->dev, data,
1001 RX_SIZE, DMA_FROM_DEVICE);
1002 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1003 free_buffer(buff);

--- 8 unchanged lines hidden (view full) ---

1012static void destroy_hdlc_queues(struct port *port)
1013{
1014 int i;
1015
1016 if (port->desc_tab) {
1017 for (i = 0; i < RX_DESCS; i++) {
1018 struct desc *desc = rx_desc_ptr(port, i);
1019 buffer_t *buff = port->rx_buff_tab[i];
1022
1023 if (buff) {
1024 dma_unmap_single(&port->netdev->dev,
1025 desc->data, RX_SIZE,
1026 DMA_FROM_DEVICE);
1027 free_buffer(buff);
1028 }
1029 }
1030 for (i = 0; i < TX_DESCS; i++) {
1031 struct desc *desc = tx_desc_ptr(port, i);
1032 buffer_t *buff = port->tx_buff_tab[i];
1020 if (buff) {
1021 dma_unmap_single(&port->netdev->dev,
1022 desc->data, RX_SIZE,
1023 DMA_FROM_DEVICE);
1024 free_buffer(buff);
1025 }
1026 }
1027 for (i = 0; i < TX_DESCS; i++) {
1028 struct desc *desc = tx_desc_ptr(port, i);
1029 buffer_t *buff = port->tx_buff_tab[i];
1033
1034 if (buff) {
1035 dma_unmap_tx(port, desc);
1036 free_buffer(buff);
1037 }
1038 }
1039 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1040 port->desc_tab = NULL;
1041 }

--- 5 unchanged lines hidden (view full) ---

1047}
1048
1049static int hss_hdlc_open(struct net_device *dev)
1050{
1051 struct port *port = dev_to_port(dev);
1052 unsigned long flags;
1053 int i, err = 0;
1054
1030 if (buff) {
1031 dma_unmap_tx(port, desc);
1032 free_buffer(buff);
1033 }
1034 }
1035 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1036 port->desc_tab = NULL;
1037 }

--- 5 unchanged lines hidden (view full) ---

1043}
1044
1045static int hss_hdlc_open(struct net_device *dev)
1046{
1047 struct port *port = dev_to_port(dev);
1048 unsigned long flags;
1049 int i, err = 0;
1050
1055 err = hdlc_open(dev);
1056 if (err)
1051 if ((err = hdlc_open(dev)))
1057 return err;
1058
1052 return err;
1053
1059 err = hss_load_firmware(port);
1060 if (err)
1054 if ((err = hss_load_firmware(port)))
1061 goto err_hdlc_close;
1062
1055 goto err_hdlc_close;
1056
1063 err = request_hdlc_queues(port);
1064 if (err)
1057 if ((err = request_hdlc_queues(port)))
1065 goto err_hdlc_close;
1066
1058 goto err_hdlc_close;
1059
1067 err = init_hdlc_queues(port);
1068 if (err)
1060 if ((err = init_hdlc_queues(port)))
1069 goto err_destroy_queues;
1070
1071 spin_lock_irqsave(&npe_lock, flags);
1061 goto err_destroy_queues;
1062
1063 spin_lock_irqsave(&npe_lock, flags);
1072 if (port->plat->open) {
1073 err = port->plat->open(port->id, dev, hss_hdlc_set_carrier);
1074 if (err)
1064 if (port->plat->open)
1065 if ((err = port->plat->open(port->id, dev,
1066 hss_hdlc_set_carrier)))
1075 goto err_unlock;
1067 goto err_unlock;
1076 }
1077
1078 spin_unlock_irqrestore(&npe_lock, flags);
1079
1080 /* Populate queues with buffers, no failure after this point */
1081 for (i = 0; i < TX_DESCS; i++)
1082 queue_put_desc(port->plat->txreadyq,
1083 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1084
1085 for (i = 0; i < RX_DESCS; i++)

--- 80 unchanged lines hidden (view full) ---

1166 spin_unlock_irqrestore(&npe_lock, flags);
1167
1168 destroy_hdlc_queues(port);
1169 release_hdlc_queues(port);
1170 hdlc_close(dev);
1171 return 0;
1172}
1173
1068 spin_unlock_irqrestore(&npe_lock, flags);
1069
1070 /* Populate queues with buffers, no failure after this point */
1071 for (i = 0; i < TX_DESCS; i++)
1072 queue_put_desc(port->plat->txreadyq,
1073 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1074
1075 for (i = 0; i < RX_DESCS; i++)

--- 80 unchanged lines hidden (view full) ---

1156 spin_unlock_irqrestore(&npe_lock, flags);
1157
1158 destroy_hdlc_queues(port);
1159 release_hdlc_queues(port);
1160 hdlc_close(dev);
1161 return 0;
1162}
1163
1164
1174static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1175 unsigned short parity)
1176{
1177 struct port *port = dev_to_port(dev);
1178
1179 if (encoding != ENCODING_NRZ)
1180 return -EINVAL;
1181
1165static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1166 unsigned short parity)
1167{
1168 struct port *port = dev_to_port(dev);
1169
1170 if (encoding != ENCODING_NRZ)
1171 return -EINVAL;
1172
1182 switch (parity) {
1173 switch(parity) {
1183 case PARITY_CRC16_PR1_CCITT:
1184 port->hdlc_cfg = 0;
1185 return 0;
1186
1187 case PARITY_CRC32_PR1_CCITT:
1188 port->hdlc_cfg = PKT_HDLC_CRC_32;
1189 return 0;
1190

--- 38 unchanged lines hidden (view full) ---

1229
1230 if (rate * a == timer_freq) { /* don't divide by 0 later */
1231 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1232 return;
1233 }
1234
1235 for (b = 0; b < 0x400; b++) {
1236 u64 c = (b + 1) * (u64)rate;
1174 case PARITY_CRC16_PR1_CCITT:
1175 port->hdlc_cfg = 0;
1176 return 0;
1177
1178 case PARITY_CRC32_PR1_CCITT:
1179 port->hdlc_cfg = PKT_HDLC_CRC_32;
1180 return 0;
1181

--- 38 unchanged lines hidden (view full) ---

1220
1221 if (rate * a == timer_freq) { /* don't divide by 0 later */
1222 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1223 return;
1224 }
1225
1226 for (b = 0; b < 0x400; b++) {
1227 u64 c = (b + 1) * (u64)rate;
1237
1238 do_div(c, timer_freq - rate * a);
1239 c--;
1240 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1241 if (b == 0 && /* also try a bit higher rate */
1242 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1243 &diff, reg))
1244 return;
1245 check_clock(timer_freq, rate, a, b, 0xFFF, best,

--- 15 unchanged lines hidden (view full) ---

1261 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1262 struct port *port = dev_to_port(dev);
1263 unsigned long flags;
1264 int clk;
1265
1266 if (cmd != SIOCWANDEV)
1267 return hdlc_ioctl(dev, ifr, cmd);
1268
1228 do_div(c, timer_freq - rate * a);
1229 c--;
1230 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1231 if (b == 0 && /* also try a bit higher rate */
1232 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1233 &diff, reg))
1234 return;
1235 check_clock(timer_freq, rate, a, b, 0xFFF, best,

--- 15 unchanged lines hidden (view full) ---

1251 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1252 struct port *port = dev_to_port(dev);
1253 unsigned long flags;
1254 int clk;
1255
1256 if (cmd != SIOCWANDEV)
1257 return hdlc_ioctl(dev, ifr, cmd);
1258
1269 switch (ifr->ifr_settings.type) {
1259 switch(ifr->ifr_settings.type) {
1270 case IF_GET_IFACE:
1271 ifr->ifr_settings.type = IF_IFACE_V35;
1272 if (ifr->ifr_settings.size < size) {
1273 ifr->ifr_settings.size = size; /* data size wanted */
1274 return -ENOBUFS;
1275 }
1276 memset(&new_line, 0, sizeof(new_line));
1277 new_line.clock_type = port->clock_type;
1278 new_line.clock_rate = port->clock_rate;
1279 new_line.loopback = port->loopback;
1280 if (copy_to_user(line, &new_line, size))
1281 return -EFAULT;
1282 return 0;
1283
1284 case IF_IFACE_SYNC_SERIAL:
1285 case IF_IFACE_V35:
1260 case IF_GET_IFACE:
1261 ifr->ifr_settings.type = IF_IFACE_V35;
1262 if (ifr->ifr_settings.size < size) {
1263 ifr->ifr_settings.size = size; /* data size wanted */
1264 return -ENOBUFS;
1265 }
1266 memset(&new_line, 0, sizeof(new_line));
1267 new_line.clock_type = port->clock_type;
1268 new_line.clock_rate = port->clock_rate;
1269 new_line.loopback = port->loopback;
1270 if (copy_to_user(line, &new_line, size))
1271 return -EFAULT;
1272 return 0;
1273
1274 case IF_IFACE_SYNC_SERIAL:
1275 case IF_IFACE_V35:
1286 if (!capable(CAP_NET_ADMIN))
1276 if(!capable(CAP_NET_ADMIN))
1287 return -EPERM;
1288 if (copy_from_user(&new_line, line, size))
1289 return -EFAULT;
1290
1291 clk = new_line.clock_type;
1292 if (port->plat->set_clock)
1293 clk = port->plat->set_clock(port->id, clk);
1294
1295 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1296 return -EINVAL; /* No such clock setting */
1297
1298 if (new_line.loopback != 0 && new_line.loopback != 1)
1299 return -EINVAL;
1300
1301 port->clock_type = clk; /* Update settings */
1277 return -EPERM;
1278 if (copy_from_user(&new_line, line, size))
1279 return -EFAULT;
1280
1281 clk = new_line.clock_type;
1282 if (port->plat->set_clock)
1283 clk = port->plat->set_clock(port->id, clk);
1284
1285 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1286 return -EINVAL; /* No such clock setting */
1287
1288 if (new_line.loopback != 0 && new_line.loopback != 1)
1289 return -EINVAL;
1290
1291 port->clock_type = clk; /* Update settings */
1302 if (clk == CLOCK_INT) {
1292 if (clk == CLOCK_INT)
1303 find_best_clock(port->plat->timer_freq,
1304 new_line.clock_rate,
1305 &port->clock_rate, &port->clock_reg);
1293 find_best_clock(port->plat->timer_freq,
1294 new_line.clock_rate,
1295 &port->clock_rate, &port->clock_reg);
1306 } else {
1296 else {
1307 port->clock_rate = 0;
1308 port->clock_reg = CLK42X_SPEED_2048KHZ;
1309 }
1310 port->loopback = new_line.loopback;
1311
1312 spin_lock_irqsave(&npe_lock, flags);
1313
1314 if (dev->flags & IFF_UP)

--- 25 unchanged lines hidden (view full) ---

1340
1341static int hss_init_one(struct platform_device *pdev)
1342{
1343 struct port *port;
1344 struct net_device *dev;
1345 hdlc_device *hdlc;
1346 int err;
1347
1297 port->clock_rate = 0;
1298 port->clock_reg = CLK42X_SPEED_2048KHZ;
1299 }
1300 port->loopback = new_line.loopback;
1301
1302 spin_lock_irqsave(&npe_lock, flags);
1303
1304 if (dev->flags & IFF_UP)

--- 25 unchanged lines hidden (view full) ---

1330
1331static int hss_init_one(struct platform_device *pdev)
1332{
1333 struct port *port;
1334 struct net_device *dev;
1335 hdlc_device *hdlc;
1336 int err;
1337
1348 port = kzalloc(sizeof(*port), GFP_KERNEL);
1349 if (!port)
1338 if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
1350 return -ENOMEM;
1351
1339 return -ENOMEM;
1340
1352 port->npe = npe_request(0);
1353 if (!port->npe) {
1341 if ((port->npe = npe_request(0)) == NULL) {
1354 err = -ENODEV;
1355 goto err_free;
1356 }
1357
1342 err = -ENODEV;
1343 goto err_free;
1344 }
1345
1358 dev = alloc_hdlcdev(port);
1359 port->netdev = alloc_hdlcdev(port);
1360 if (!port->netdev) {
1346 if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
1361 err = -ENOMEM;
1362 goto err_plat;
1363 }
1364
1365 SET_NETDEV_DEV(dev, &pdev->dev);
1366 hdlc = dev_to_hdlc(dev);
1367 hdlc->attach = hss_hdlc_attach;
1368 hdlc->xmit = hss_hdlc_xmit;
1369 dev->netdev_ops = &hss_hdlc_ops;
1370 dev->tx_queue_len = 100;
1371 port->clock_type = CLOCK_EXT;
1372 port->clock_rate = 0;
1373 port->clock_reg = CLK42X_SPEED_2048KHZ;
1374 port->id = pdev->id;
1375 port->dev = &pdev->dev;
1376 port->plat = pdev->dev.platform_data;
1377 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1378
1347 err = -ENOMEM;
1348 goto err_plat;
1349 }
1350
1351 SET_NETDEV_DEV(dev, &pdev->dev);
1352 hdlc = dev_to_hdlc(dev);
1353 hdlc->attach = hss_hdlc_attach;
1354 hdlc->xmit = hss_hdlc_xmit;
1355 dev->netdev_ops = &hss_hdlc_ops;
1356 dev->tx_queue_len = 100;
1357 port->clock_type = CLOCK_EXT;
1358 port->clock_rate = 0;
1359 port->clock_reg = CLK42X_SPEED_2048KHZ;
1360 port->id = pdev->id;
1361 port->dev = &pdev->dev;
1362 port->plat = pdev->dev.platform_data;
1363 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1364
1379 err = register_hdlc_device(dev);
1380 if (err)
1365 if ((err = register_hdlc_device(dev)))
1381 goto err_free_netdev;
1382
1383 platform_set_drvdata(pdev, port);
1384
1385 netdev_info(dev, "initialized\n");
1386 return 0;
1387
1388err_free_netdev:

--- 46 unchanged lines hidden --- 		1366 goto err_free_netdev;
1367
1368 platform_set_drvdata(pdev, port);
1369
1370 netdev_info(dev, "initialized\n");
1371 return 0;
1372
1373err_free_netdev:

--- 46 unchanged lines hidden ---