1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux 4 * 5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl> 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/module.h> 11 #include <linux/bitops.h> 12 #include <linux/cdev.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/dmapool.h> 15 #include <linux/fs.h> 16 #include <linux/hdlc.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/platform_device.h> 20 #include <linux/platform_data/wan_ixp4xx_hss.h> 21 #include <linux/poll.h> 22 #include <linux/slab.h> 23 #include <linux/soc/ixp4xx/npe.h> 24 #include <linux/soc/ixp4xx/qmgr.h> 25 26 #define DEBUG_DESC 0 27 #define DEBUG_RX 0 28 #define DEBUG_TX 0 29 #define DEBUG_PKT_BYTES 0 30 #define DEBUG_CLOSE 0 31 32 #define DRV_NAME "ixp4xx_hss" 33 34 #define PKT_EXTRA_FLAGS 0 /* orig 1 */ 35 #define PKT_NUM_PIPES 1 /* 1, 2 or 4 */ 36 #define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */ 37 38 #define RX_DESCS 16 /* also length of all RX queues */ 39 #define TX_DESCS 16 /* also length of all TX queues */ 40 41 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) 42 #define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */ 43 #define MAX_CLOSE_WAIT 1000 /* microseconds */ 44 #define HSS_COUNT 2 45 #define FRAME_SIZE 256 /* doesn't matter at this point */ 46 #define FRAME_OFFSET 0 47 #define MAX_CHANNELS (FRAME_SIZE / 8) 48 49 #define NAPI_WEIGHT 16 50 51 /* Queue IDs */ 52 #define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */ 53 #define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */ 54 #define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */ 55 #define HSS0_PKT_TX1_QUEUE 15 56 #define HSS0_PKT_TX2_QUEUE 16 57 #define HSS0_PKT_TX3_QUEUE 17 58 #define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */ 59 #define HSS0_PKT_RXFREE1_QUEUE 19 60 #define HSS0_PKT_RXFREE2_QUEUE 20 61 #define HSS0_PKT_RXFREE3_QUEUE 21 62 #define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */ 63 64 #define HSS1_CHL_RXTRIG_QUEUE 10 65 #define HSS1_PKT_RX_QUEUE 0 66 #define HSS1_PKT_TX0_QUEUE 5 67 #define HSS1_PKT_TX1_QUEUE 6 68 #define HSS1_PKT_TX2_QUEUE 7 69 #define HSS1_PKT_TX3_QUEUE 8 70 #define HSS1_PKT_RXFREE0_QUEUE 1 71 #define HSS1_PKT_RXFREE1_QUEUE 2 72 #define HSS1_PKT_RXFREE2_QUEUE 3 73 #define HSS1_PKT_RXFREE3_QUEUE 4 74 #define HSS1_PKT_TXDONE_QUEUE 9 75 76 #define NPE_PKT_MODE_HDLC 0 77 #define NPE_PKT_MODE_RAW 1 78 #define NPE_PKT_MODE_56KMODE 2 79 #define NPE_PKT_MODE_56KENDIAN_MSB 4 80 81 /* PKT_PIPE_HDLC_CFG_WRITE flags */ 82 #define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */ 83 #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */ 84 #define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */ 85 86 /* hss_config, PCRs */ 87 /* Frame sync sampling, default = active low */ 88 #define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000 89 #define PCR_FRM_SYNC_FALLINGEDGE 0x80000000 90 #define PCR_FRM_SYNC_RISINGEDGE 0xC0000000 91 92 /* Frame sync pin: input (default) or output generated off a given clk edge */ 93 #define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000 94 #define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000 95 96 /* Frame and data clock sampling on edge, default = falling */ 97 #define PCR_FCLK_EDGE_RISING 0x08000000 98 #define PCR_DCLK_EDGE_RISING 0x04000000 99 100 /* Clock direction, default = input */ 101 #define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000 102 103 /* Generate/Receive frame pulses, default = enabled */ 104 #define PCR_FRM_PULSE_DISABLED 0x01000000 105 106 /* Data rate is full (default) or half the configured clk speed */ 107 #define PCR_HALF_CLK_RATE 0x00200000 108 109 /* Invert data between NPE and HSS FIFOs? (default = no) */ 110 #define PCR_DATA_POLARITY_INVERT 0x00100000 111 112 /* TX/RX endianness, default = LSB */ 113 #define PCR_MSB_ENDIAN 0x00080000 114 115 /* Normal (default) / open drain mode (TX only) */ 116 #define PCR_TX_PINS_OPEN_DRAIN 0x00040000 117 118 /* No framing bit transmitted and expected on RX? (default = framing bit) */ 119 #define PCR_SOF_NO_FBIT 0x00020000 120 121 /* Drive data pins? */ 122 #define PCR_TX_DATA_ENABLE 0x00010000 123 124 /* Voice 56k type: drive the data pins low (default), high, high Z */ 125 #define PCR_TX_V56K_HIGH 0x00002000 126 #define PCR_TX_V56K_HIGH_IMP 0x00004000 127 128 /* Unassigned type: drive the data pins low (default), high, high Z */ 129 #define PCR_TX_UNASS_HIGH 0x00000800 130 #define PCR_TX_UNASS_HIGH_IMP 0x00001000 131 132 /* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */ 133 #define PCR_TX_FB_HIGH_IMP 0x00000400 134 135 /* 56k data endiannes - which bit unused: high (default) or low */ 136 #define PCR_TX_56KE_BIT_0_UNUSED 0x00000200 137 138 /* 56k data transmission type: 32/8 bit data (default) or 56K data */ 139 #define PCR_TX_56KS_56K_DATA 0x00000100 140 141 /* hss_config, cCR */ 142 /* Number of packetized clients, default = 1 */ 143 #define CCR_NPE_HFIFO_2_HDLC 0x04000000 144 #define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000 145 146 /* default = no loopback */ 147 #define CCR_LOOPBACK 0x02000000 148 149 /* HSS number, default = 0 (first) */ 150 #define CCR_SECOND_HSS 0x01000000 151 152 /* hss_config, clkCR: main:10, num:10, denom:12 */ 153 #define CLK42X_SPEED_EXP ((0x3FF << 22) | (2 << 12) | 15) /*65 KHz*/ 154 155 #define CLK42X_SPEED_512KHZ ((130 << 22) | (2 << 12) | 15) 156 #define CLK42X_SPEED_1536KHZ ((43 << 22) | (18 << 12) | 47) 157 #define CLK42X_SPEED_1544KHZ ((43 << 22) | (33 << 12) | 192) 158 #define CLK42X_SPEED_2048KHZ ((32 << 22) | (34 << 12) | 63) 159 #define CLK42X_SPEED_4096KHZ ((16 << 22) | (34 << 12) | 127) 160 #define CLK42X_SPEED_8192KHZ ((8 << 22) | (34 << 12) | 255) 161 162 #define CLK46X_SPEED_512KHZ ((130 << 22) | (24 << 12) | 127) 163 #define CLK46X_SPEED_1536KHZ ((43 << 22) | (152 << 12) | 383) 164 #define CLK46X_SPEED_1544KHZ ((43 << 22) | (66 << 12) | 385) 165 #define CLK46X_SPEED_2048KHZ ((32 << 22) | (280 << 12) | 511) 166 #define CLK46X_SPEED_4096KHZ ((16 << 22) | (280 << 12) | 1023) 167 #define CLK46X_SPEED_8192KHZ ((8 << 22) | (280 << 12) | 2047) 168 169 /* HSS_CONFIG_CLOCK_CR register consists of 3 parts: 170 * A (10 bits), B (10 bits) and C (12 bits). 171 * IXP42x HSS clock generator operation (verified with an oscilloscope): 172 * Each clock bit takes 7.5 ns (1 / 133.xx MHz). 173 * The clock sequence consists of (C - B) states of 0s and 1s, each state is 174 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is 175 * (A + 1) bits wide. 176 * 177 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is: 178 * freq = 66.666 MHz / (A + (B + 1) / (C + 1)) 179 * minimum freq = 66.666 MHz / (A + 1) 180 * maximum freq = 66.666 MHz / A 181 * 182 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7 183 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s). 184 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples). 185 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits 186 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats). 187 * The sequence consists of 4 complete clock periods, thus the average 188 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s). 189 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s). 190 */ 191 192 /* hss_config, LUT entries */ 193 #define TDMMAP_UNASSIGNED 0 194 #define TDMMAP_HDLC 1 /* HDLC - packetized */ 195 #define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */ 196 #define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */ 197 198 /* offsets into HSS config */ 199 #define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */ 200 #define HSS_CONFIG_RX_PCR 0x04 201 #define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */ 202 #define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */ 203 #define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */ 204 #define HSS_CONFIG_RX_FCR 0x14 205 #define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */ 206 #define HSS_CONFIG_RX_LUT 0x38 207 208 /* NPE command codes */ 209 /* writes the ConfigWord value to the location specified by offset */ 210 #define PORT_CONFIG_WRITE 0x40 211 212 /* triggers the NPE to load the contents of the configuration table */ 213 #define PORT_CONFIG_LOAD 0x41 214 215 /* triggers the NPE to return an HssErrorReadResponse message */ 216 #define PORT_ERROR_READ 0x42 217 218 /* triggers the NPE to reset internal status and enable the HssPacketized 219 * operation for the flow specified by pPipe 220 */ 221 #define PKT_PIPE_FLOW_ENABLE 0x50 222 #define PKT_PIPE_FLOW_DISABLE 0x51 223 #define PKT_NUM_PIPES_WRITE 0x52 224 #define PKT_PIPE_FIFO_SIZEW_WRITE 0x53 225 #define PKT_PIPE_HDLC_CFG_WRITE 0x54 226 #define PKT_PIPE_IDLE_PATTERN_WRITE 0x55 227 #define PKT_PIPE_RX_SIZE_WRITE 0x56 228 #define PKT_PIPE_MODE_WRITE 0x57 229 230 /* HDLC packet status values - desc->status */ 231 #define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */ 232 #define ERR_HDLC_ALIGN 2 /* HDLC alignment error */ 233 #define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */ 234 #define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving 235 * this packet (if buf_len < pkt_len) 236 */ 237 #define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */ 238 #define ERR_HDLC_ABORT 6 /* abort sequence received */ 239 #define ERR_DISCONNECTING 7 /* disconnect is in progress */ 240 241 #ifdef __ARMEB__ 242 typedef struct sk_buff buffer_t; 243 #define free_buffer dev_kfree_skb 244 #define free_buffer_irq dev_consume_skb_irq 245 #else 246 typedef void buffer_t; 247 #define free_buffer kfree 248 #define free_buffer_irq kfree 249 #endif 250 251 struct port { 252 struct device *dev; 253 struct npe *npe; 254 struct net_device *netdev; 255 struct napi_struct napi; 256 struct hss_plat_info *plat; 257 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; 258 struct desc *desc_tab; /* coherent */ 259 dma_addr_t desc_tab_phys; 260 unsigned int id; 261 unsigned int clock_type, clock_rate, loopback; 262 unsigned int initialized, carrier; 263 u8 hdlc_cfg; 264 u32 clock_reg; 265 }; 266 267 /* NPE message structure */ 268 struct msg { 269 #ifdef __ARMEB__ 270 u8 cmd, unused, hss_port, index; 271 union { 272 struct { u8 data8a, data8b, data8c, data8d; }; 273 struct { u16 data16a, data16b; }; 274 struct { u32 data32; }; 275 }; 276 #else 277 u8 index, hss_port, unused, cmd; 278 union { 279 struct { u8 data8d, data8c, data8b, data8a; }; 280 struct { u16 data16b, data16a; }; 281 struct { u32 data32; }; 282 }; 283 #endif 284 }; 285 286 /* HDLC packet descriptor */ 287 struct desc { 288 u32 next; /* pointer to next buffer, unused */ 289 290 #ifdef __ARMEB__ 291 u16 buf_len; /* buffer length */ 292 u16 pkt_len; /* packet length */ 293 u32 data; /* pointer to data buffer in RAM */ 294 u8 status; 295 u8 error_count; 296 u16 __reserved; 297 #else 298 u16 pkt_len; /* packet length */ 299 u16 buf_len; /* buffer length */ 300 u32 data; /* pointer to data buffer in RAM */ 301 u16 __reserved; 302 u8 error_count; 303 u8 status; 304 #endif 305 u32 __reserved1[4]; 306 }; 307 308 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ 309 (n) * sizeof(struct desc)) 310 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) 311 312 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ 313 ((n) + RX_DESCS) * sizeof(struct desc)) 314 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) 315 316 /***************************************************************************** 317 * global variables 318 ****************************************************************************/ 319 320 static int ports_open; 321 static struct dma_pool *dma_pool; 322 static DEFINE_SPINLOCK(npe_lock); 323 324 static const struct { 325 int tx, txdone, rx, rxfree; 326 } queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE, 327 HSS0_PKT_RXFREE0_QUEUE}, 328 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE, 329 HSS1_PKT_RXFREE0_QUEUE}, 330 }; 331 332 /***************************************************************************** 333 * utility functions 334 ****************************************************************************/ 335 336 static inline struct port *dev_to_port(struct net_device *dev) 337 { 338 return dev_to_hdlc(dev)->priv; 339 } 340 341 #ifndef __ARMEB__ 342 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) 343 { 344 int i; 345 346 for (i = 0; i < cnt; i++) 347 dest[i] = swab32(src[i]); 348 } 349 #endif 350 351 /***************************************************************************** 352 * HSS access 353 ****************************************************************************/ 354 355 static void hss_npe_send(struct port *port, struct msg *msg, const char *what) 356 { 357 u32 *val = (u32 *)msg; 358 359 if (npe_send_message(port->npe, msg, what)) { 360 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n", 361 port->id, val[0], val[1], npe_name(port->npe)); 362 BUG(); 363 } 364 } 365 366 static void hss_config_set_lut(struct port *port) 367 { 368 struct msg msg; 369 int ch; 370 371 memset(&msg, 0, sizeof(msg)); 372 msg.cmd = PORT_CONFIG_WRITE; 373 msg.hss_port = port->id; 374 375 for (ch = 0; ch < MAX_CHANNELS; ch++) { 376 msg.data32 >>= 2; 377 msg.data32 |= TDMMAP_HDLC << 30; 378 379 if (ch % 16 == 15) { 380 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3); 381 hss_npe_send(port, &msg, "HSS_SET_TX_LUT"); 382 383 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT; 384 hss_npe_send(port, &msg, "HSS_SET_RX_LUT"); 385 } 386 } 387 } 388 389 static void hss_config(struct port *port) 390 { 391 struct msg msg; 392 393 memset(&msg, 0, sizeof(msg)); 394 msg.cmd = PORT_CONFIG_WRITE; 395 msg.hss_port = port->id; 396 msg.index = HSS_CONFIG_TX_PCR; 397 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN | 398 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT; 399 if (port->clock_type == CLOCK_INT) 400 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT; 401 hss_npe_send(port, &msg, "HSS_SET_TX_PCR"); 402 403 msg.index = HSS_CONFIG_RX_PCR; 404 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING; 405 hss_npe_send(port, &msg, "HSS_SET_RX_PCR"); 406 407 memset(&msg, 0, sizeof(msg)); 408 msg.cmd = PORT_CONFIG_WRITE; 409 msg.hss_port = port->id; 410 msg.index = HSS_CONFIG_CORE_CR; 411 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) | 412 (port->id ? CCR_SECOND_HSS : 0); 413 hss_npe_send(port, &msg, "HSS_SET_CORE_CR"); 414 415 memset(&msg, 0, sizeof(msg)); 416 msg.cmd = PORT_CONFIG_WRITE; 417 msg.hss_port = port->id; 418 msg.index = HSS_CONFIG_CLOCK_CR; 419 msg.data32 = port->clock_reg; 420 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR"); 421 422 memset(&msg, 0, sizeof(msg)); 423 msg.cmd = PORT_CONFIG_WRITE; 424 msg.hss_port = port->id; 425 msg.index = HSS_CONFIG_TX_FCR; 426 msg.data16a = FRAME_OFFSET; 427 msg.data16b = FRAME_SIZE - 1; 428 hss_npe_send(port, &msg, "HSS_SET_TX_FCR"); 429 430 memset(&msg, 0, sizeof(msg)); 431 msg.cmd = PORT_CONFIG_WRITE; 432 msg.hss_port = port->id; 433 msg.index = HSS_CONFIG_RX_FCR; 434 msg.data16a = FRAME_OFFSET; 435 msg.data16b = FRAME_SIZE - 1; 436 hss_npe_send(port, &msg, "HSS_SET_RX_FCR"); 437 438 hss_config_set_lut(port); 439 440 memset(&msg, 0, sizeof(msg)); 441 msg.cmd = PORT_CONFIG_LOAD; 442 msg.hss_port = port->id; 443 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG"); 444 445 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") || 446 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */ 447 msg.cmd != PORT_CONFIG_LOAD || msg.data32) { 448 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id); 449 BUG(); 450 } 451 452 /* HDLC may stop working without this - check FIXME */ 453 npe_recv_message(port->npe, &msg, "FLUSH_IT"); 454 } 455 456 static void hss_set_hdlc_cfg(struct port *port) 457 { 458 struct msg msg; 459 460 memset(&msg, 0, sizeof(msg)); 461 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE; 462 msg.hss_port = port->id; 463 msg.data8a = port->hdlc_cfg; /* rx_cfg */ 464 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */ 465 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG"); 466 } 467 468 static u32 hss_get_status(struct port *port) 469 { 470 struct msg msg; 471 472 memset(&msg, 0, sizeof(msg)); 473 msg.cmd = PORT_ERROR_READ; 474 msg.hss_port = port->id; 475 hss_npe_send(port, &msg, "PORT_ERROR_READ"); 476 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) { 477 pr_crit("HSS-%i: unable to read HSS status\n", port->id); 478 BUG(); 479 } 480 481 return msg.data32; 482 } 483 484 static void hss_start_hdlc(struct port *port) 485 { 486 struct msg msg; 487 488 memset(&msg, 0, sizeof(msg)); 489 msg.cmd = PKT_PIPE_FLOW_ENABLE; 490 msg.hss_port = port->id; 491 msg.data32 = 0; 492 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE"); 493 } 494 495 static void hss_stop_hdlc(struct port *port) 496 { 497 struct msg msg; 498 499 memset(&msg, 0, sizeof(msg)); 500 msg.cmd = PKT_PIPE_FLOW_DISABLE; 501 msg.hss_port = port->id; 502 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE"); 503 hss_get_status(port); /* make sure it's halted */ 504 } 505 506 static int hss_load_firmware(struct port *port) 507 { 508 struct msg msg; 509 int err; 510 511 if (port->initialized) 512 return 0; 513 514 if (!npe_running(port->npe)) { 515 err = npe_load_firmware(port->npe, npe_name(port->npe), 516 port->dev); 517 if (err) 518 return err; 519 } 520 521 /* HDLC mode configuration */ 522 memset(&msg, 0, sizeof(msg)); 523 msg.cmd = PKT_NUM_PIPES_WRITE; 524 msg.hss_port = port->id; 525 msg.data8a = PKT_NUM_PIPES; 526 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES"); 527 528 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE; 529 msg.data8a = PKT_PIPE_FIFO_SIZEW; 530 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO"); 531 532 msg.cmd = PKT_PIPE_MODE_WRITE; 533 msg.data8a = NPE_PKT_MODE_HDLC; 534 /* msg.data8b = inv_mask */ 535 /* msg.data8c = or_mask */ 536 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE"); 537 538 msg.cmd = PKT_PIPE_RX_SIZE_WRITE; 539 msg.data16a = HDLC_MAX_MRU; /* including CRC */ 540 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE"); 541 542 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE; 543 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */ 544 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE"); 545 546 port->initialized = 1; 547 return 0; 548 } 549 550 /***************************************************************************** 551 * packetized (HDLC) operation 552 ****************************************************************************/ 553 554 static inline void debug_pkt(struct net_device *dev, const char *func, 555 u8 *data, int len) 556 { 557 #if DEBUG_PKT_BYTES 558 int i; 559 560 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len); 561 for (i = 0; i < len; i++) { 562 if (i >= DEBUG_PKT_BYTES) 563 break; 564 printk("%s%02X", !(i % 4) ? " " : "", data[i]); 565 } 566 printk("\n"); 567 #endif 568 } 569 570 static inline void debug_desc(u32 phys, struct desc *desc) 571 { 572 #if DEBUG_DESC 573 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n", 574 phys, desc->next, desc->buf_len, desc->pkt_len, 575 desc->data, desc->status, desc->error_count); 576 #endif 577 } 578 579 static inline int queue_get_desc(unsigned int queue, struct port *port, 580 int is_tx) 581 { 582 u32 phys, tab_phys, n_desc; 583 struct desc *tab; 584 585 phys = qmgr_get_entry(queue); 586 if (!phys) 587 return -1; 588 589 BUG_ON(phys & 0x1F); 590 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); 591 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); 592 n_desc = (phys - tab_phys) / sizeof(struct desc); 593 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); 594 debug_desc(phys, &tab[n_desc]); 595 BUG_ON(tab[n_desc].next); 596 return n_desc; 597 } 598 599 static inline void queue_put_desc(unsigned int queue, u32 phys, 600 struct desc *desc) 601 { 602 debug_desc(phys, desc); 603 BUG_ON(phys & 0x1F); 604 qmgr_put_entry(queue, phys); 605 /* Don't check for queue overflow here, we've allocated sufficient 606 * length and queues >= 32 don't support this check anyway. 607 */ 608 } 609 610 static inline void dma_unmap_tx(struct port *port, struct desc *desc) 611 { 612 #ifdef __ARMEB__ 613 dma_unmap_single(&port->netdev->dev, desc->data, 614 desc->buf_len, DMA_TO_DEVICE); 615 #else 616 dma_unmap_single(&port->netdev->dev, desc->data & ~3, 617 ALIGN((desc->data & 3) + desc->buf_len, 4), 618 DMA_TO_DEVICE); 619 #endif 620 } 621 622 static void hss_hdlc_set_carrier(void *pdev, int carrier) 623 { 624 struct net_device *netdev = pdev; 625 struct port *port = dev_to_port(netdev); 626 unsigned long flags; 627 628 spin_lock_irqsave(&npe_lock, flags); 629 port->carrier = carrier; 630 if (!port->loopback) { 631 if (carrier) 632 netif_carrier_on(netdev); 633 else 634 netif_carrier_off(netdev); 635 } 636 spin_unlock_irqrestore(&npe_lock, flags); 637 } 638 639 static void hss_hdlc_rx_irq(void *pdev) 640 { 641 struct net_device *dev = pdev; 642 struct port *port = dev_to_port(dev); 643 644 #if DEBUG_RX 645 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name); 646 #endif 647 qmgr_disable_irq(queue_ids[port->id].rx); 648 napi_schedule(&port->napi); 649 } 650 651 static int hss_hdlc_poll(struct napi_struct *napi, int budget) 652 { 653 struct port *port = container_of(napi, struct port, napi); 654 struct net_device *dev = port->netdev; 655 unsigned int rxq = queue_ids[port->id].rx; 656 unsigned int rxfreeq = queue_ids[port->id].rxfree; 657 int received = 0; 658 659 #if DEBUG_RX 660 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name); 661 #endif 662 663 while (received < budget) { 664 struct sk_buff *skb; 665 struct desc *desc; 666 int n; 667 #ifdef __ARMEB__ 668 struct sk_buff *temp; 669 u32 phys; 670 #endif 671 672 n = queue_get_desc(rxq, port, 0); 673 if (n < 0) { 674 #if DEBUG_RX 675 printk(KERN_DEBUG "%s: hss_hdlc_poll" 676 " napi_complete\n", dev->name); 677 #endif 678 napi_complete(napi); 679 qmgr_enable_irq(rxq); 680 if (!qmgr_stat_empty(rxq) && 681 napi_reschedule(napi)) { 682 #if DEBUG_RX 683 printk(KERN_DEBUG "%s: hss_hdlc_poll" 684 " napi_reschedule succeeded\n", 685 dev->name); 686 #endif 687 qmgr_disable_irq(rxq); 688 continue; 689 } 690 #if DEBUG_RX 691 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n", 692 dev->name); 693 #endif 694 return received; /* all work done */ 695 } 696 697 desc = rx_desc_ptr(port, n); 698 #if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */ 699 if (desc->error_count) 700 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X" 701 " errors %u\n", dev->name, desc->status, 702 desc->error_count); 703 #endif 704 skb = NULL; 705 switch (desc->status) { 706 case 0: 707 #ifdef __ARMEB__ 708 skb = netdev_alloc_skb(dev, RX_SIZE); 709 if (skb) { 710 phys = dma_map_single(&dev->dev, skb->data, 711 RX_SIZE, 712 DMA_FROM_DEVICE); 713 if (dma_mapping_error(&dev->dev, phys)) { 714 dev_kfree_skb(skb); 715 skb = NULL; 716 } 717 } 718 #else 719 skb = netdev_alloc_skb(dev, desc->pkt_len); 720 #endif 721 if (!skb) 722 dev->stats.rx_dropped++; 723 break; 724 case ERR_HDLC_ALIGN: 725 case ERR_HDLC_ABORT: 726 dev->stats.rx_frame_errors++; 727 dev->stats.rx_errors++; 728 break; 729 case ERR_HDLC_FCS: 730 dev->stats.rx_crc_errors++; 731 dev->stats.rx_errors++; 732 break; 733 case ERR_HDLC_TOO_LONG: 734 dev->stats.rx_length_errors++; 735 dev->stats.rx_errors++; 736 break; 737 default: /* FIXME - remove printk */ 738 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n", 739 desc->status, desc->error_count); 740 dev->stats.rx_errors++; 741 } 742 743 if (!skb) { 744 /* put the desc back on RX-ready queue */ 745 desc->buf_len = RX_SIZE; 746 desc->pkt_len = desc->status = 0; 747 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 748 continue; 749 } 750 751 /* process received frame */ 752 #ifdef __ARMEB__ 753 temp = skb; 754 skb = port->rx_buff_tab[n]; 755 dma_unmap_single(&dev->dev, desc->data, 756 RX_SIZE, DMA_FROM_DEVICE); 757 #else 758 dma_sync_single_for_cpu(&dev->dev, desc->data, 759 RX_SIZE, DMA_FROM_DEVICE); 760 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], 761 ALIGN(desc->pkt_len, 4) / 4); 762 #endif 763 skb_put(skb, desc->pkt_len); 764 765 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len); 766 767 skb->protocol = hdlc_type_trans(skb, dev); 768 dev->stats.rx_packets++; 769 dev->stats.rx_bytes += skb->len; 770 netif_receive_skb(skb); 771 772 /* put the new buffer on RX-free queue */ 773 #ifdef __ARMEB__ 774 port->rx_buff_tab[n] = temp; 775 desc->data = phys; 776 #endif 777 desc->buf_len = RX_SIZE; 778 desc->pkt_len = 0; 779 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 780 received++; 781 } 782 #if DEBUG_RX 783 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n"); 784 #endif 785 return received; /* not all work done */ 786 } 787 788 static void hss_hdlc_txdone_irq(void *pdev) 789 { 790 struct net_device *dev = pdev; 791 struct port *port = dev_to_port(dev); 792 int n_desc; 793 794 #if DEBUG_TX 795 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n"); 796 #endif 797 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone, 798 port, 1)) >= 0) { 799 struct desc *desc; 800 int start; 801 802 desc = tx_desc_ptr(port, n_desc); 803 804 dev->stats.tx_packets++; 805 dev->stats.tx_bytes += desc->pkt_len; 806 807 dma_unmap_tx(port, desc); 808 #if DEBUG_TX 809 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n", 810 dev->name, port->tx_buff_tab[n_desc]); 811 #endif 812 free_buffer_irq(port->tx_buff_tab[n_desc]); 813 port->tx_buff_tab[n_desc] = NULL; 814 815 start = qmgr_stat_below_low_watermark(port->plat->txreadyq); 816 queue_put_desc(port->plat->txreadyq, 817 tx_desc_phys(port, n_desc), desc); 818 if (start) { /* TX-ready queue was empty */ 819 #if DEBUG_TX 820 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit" 821 " ready\n", dev->name); 822 #endif 823 netif_wake_queue(dev); 824 } 825 } 826 } 827 828 static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev) 829 { 830 struct port *port = dev_to_port(dev); 831 unsigned int txreadyq = port->plat->txreadyq; 832 int len, offset, bytes, n; 833 void *mem; 834 u32 phys; 835 struct desc *desc; 836 837 #if DEBUG_TX 838 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name); 839 #endif 840 841 if (unlikely(skb->len > HDLC_MAX_MRU)) { 842 dev_kfree_skb(skb); 843 dev->stats.tx_errors++; 844 return NETDEV_TX_OK; 845 } 846 847 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len); 848 849 len = skb->len; 850 #ifdef __ARMEB__ 851 offset = 0; /* no need to keep alignment */ 852 bytes = len; 853 mem = skb->data; 854 #else 855 offset = (int)skb->data & 3; /* keep 32-bit alignment */ 856 bytes = ALIGN(offset + len, 4); 857 mem = kmalloc(bytes, GFP_ATOMIC); 858 if (!mem) { 859 dev_kfree_skb(skb); 860 dev->stats.tx_dropped++; 861 return NETDEV_TX_OK; 862 } 863 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4); 864 dev_kfree_skb(skb); 865 #endif 866 867 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); 868 if (dma_mapping_error(&dev->dev, phys)) { 869 #ifdef __ARMEB__ 870 dev_kfree_skb(skb); 871 #else 872 kfree(mem); 873 #endif 874 dev->stats.tx_dropped++; 875 return NETDEV_TX_OK; 876 } 877 878 n = queue_get_desc(txreadyq, port, 1); 879 BUG_ON(n < 0); 880 desc = tx_desc_ptr(port, n); 881 882 #ifdef __ARMEB__ 883 port->tx_buff_tab[n] = skb; 884 #else 885 port->tx_buff_tab[n] = mem; 886 #endif 887 desc->data = phys + offset; 888 desc->buf_len = desc->pkt_len = len; 889 890 wmb(); 891 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc); 892 893 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ 894 #if DEBUG_TX 895 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name); 896 #endif 897 netif_stop_queue(dev); 898 /* we could miss TX ready interrupt */ 899 if (!qmgr_stat_below_low_watermark(txreadyq)) { 900 #if DEBUG_TX 901 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n", 902 dev->name); 903 #endif 904 netif_wake_queue(dev); 905 } 906 } 907 908 #if DEBUG_TX 909 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name); 910 #endif 911 return NETDEV_TX_OK; 912 } 913 914 static int request_hdlc_queues(struct port *port) 915 { 916 int err; 917 918 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0, 919 "%s:RX-free", port->netdev->name); 920 if (err) 921 return err; 922 923 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0, 924 "%s:RX", port->netdev->name); 925 if (err) 926 goto rel_rxfree; 927 928 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0, 929 "%s:TX", port->netdev->name); 930 if (err) 931 goto rel_rx; 932 933 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0, 934 "%s:TX-ready", port->netdev->name); 935 if (err) 936 goto rel_tx; 937 938 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0, 939 "%s:TX-done", port->netdev->name); 940 if (err) 941 goto rel_txready; 942 return 0; 943 944 rel_txready: 945 qmgr_release_queue(port->plat->txreadyq); 946 rel_tx: 947 qmgr_release_queue(queue_ids[port->id].tx); 948 rel_rx: 949 qmgr_release_queue(queue_ids[port->id].rx); 950 rel_rxfree: 951 qmgr_release_queue(queue_ids[port->id].rxfree); 952 printk(KERN_DEBUG "%s: unable to request hardware queues\n", 953 port->netdev->name); 954 return err; 955 } 956 957 static void release_hdlc_queues(struct port *port) 958 { 959 qmgr_release_queue(queue_ids[port->id].rxfree); 960 qmgr_release_queue(queue_ids[port->id].rx); 961 qmgr_release_queue(queue_ids[port->id].txdone); 962 qmgr_release_queue(queue_ids[port->id].tx); 963 qmgr_release_queue(port->plat->txreadyq); 964 } 965 966 static int init_hdlc_queues(struct port *port) 967 { 968 int i; 969 970 if (!ports_open) { 971 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, 972 POOL_ALLOC_SIZE, 32, 0); 973 if (!dma_pool) 974 return -ENOMEM; 975 } 976 977 port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, 978 &port->desc_tab_phys); 979 if (!port->desc_tab) 980 return -ENOMEM; 981 memset(port->desc_tab, 0, POOL_ALLOC_SIZE); 982 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ 983 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); 984 985 /* Setup RX buffers */ 986 for (i = 0; i < RX_DESCS; i++) { 987 struct desc *desc = rx_desc_ptr(port, i); 988 buffer_t *buff; 989 void *data; 990 #ifdef __ARMEB__ 991 buff = netdev_alloc_skb(port->netdev, RX_SIZE); 992 if (!buff) 993 return -ENOMEM; 994 data = buff->data; 995 #else 996 buff = kmalloc(RX_SIZE, GFP_KERNEL); 997 if (!buff) 998 return -ENOMEM; 999 data = buff; 1000 #endif 1001 desc->buf_len = RX_SIZE; 1002 desc->data = dma_map_single(&port->netdev->dev, data, 1003 RX_SIZE, DMA_FROM_DEVICE); 1004 if (dma_mapping_error(&port->netdev->dev, desc->data)) { 1005 free_buffer(buff); 1006 return -EIO; 1007 } 1008 port->rx_buff_tab[i] = buff; 1009 } 1010 1011 return 0; 1012 } 1013 1014 static void destroy_hdlc_queues(struct port *port) 1015 { 1016 int i; 1017 1018 if (port->desc_tab) { 1019 for (i = 0; i < RX_DESCS; i++) { 1020 struct desc *desc = rx_desc_ptr(port, i); 1021 buffer_t *buff = port->rx_buff_tab[i]; 1022 1023 if (buff) { 1024 dma_unmap_single(&port->netdev->dev, 1025 desc->data, RX_SIZE, 1026 DMA_FROM_DEVICE); 1027 free_buffer(buff); 1028 } 1029 } 1030 for (i = 0; i < TX_DESCS; i++) { 1031 struct desc *desc = tx_desc_ptr(port, i); 1032 buffer_t *buff = port->tx_buff_tab[i]; 1033 1034 if (buff) { 1035 dma_unmap_tx(port, desc); 1036 free_buffer(buff); 1037 } 1038 } 1039 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); 1040 port->desc_tab = NULL; 1041 } 1042 1043 if (!ports_open && dma_pool) { 1044 dma_pool_destroy(dma_pool); 1045 dma_pool = NULL; 1046 } 1047 } 1048 1049 static int hss_hdlc_open(struct net_device *dev) 1050 { 1051 struct port *port = dev_to_port(dev); 1052 unsigned long flags; 1053 int i, err = 0; 1054 1055 err = hdlc_open(dev); 1056 if (err) 1057 return err; 1058 1059 err = hss_load_firmware(port); 1060 if (err) 1061 goto err_hdlc_close; 1062 1063 err = request_hdlc_queues(port); 1064 if (err) 1065 goto err_hdlc_close; 1066 1067 err = init_hdlc_queues(port); 1068 if (err) 1069 goto err_destroy_queues; 1070 1071 spin_lock_irqsave(&npe_lock, flags); 1072 if (port->plat->open) { 1073 err = port->plat->open(port->id, dev, hss_hdlc_set_carrier); 1074 if (err) 1075 goto err_unlock; 1076 } 1077 1078 spin_unlock_irqrestore(&npe_lock, flags); 1079 1080 /* Populate queues with buffers, no failure after this point */ 1081 for (i = 0; i < TX_DESCS; i++) 1082 queue_put_desc(port->plat->txreadyq, 1083 tx_desc_phys(port, i), tx_desc_ptr(port, i)); 1084 1085 for (i = 0; i < RX_DESCS; i++) 1086 queue_put_desc(queue_ids[port->id].rxfree, 1087 rx_desc_phys(port, i), rx_desc_ptr(port, i)); 1088 1089 napi_enable(&port->napi); 1090 netif_start_queue(dev); 1091 1092 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY, 1093 hss_hdlc_rx_irq, dev); 1094 1095 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY, 1096 hss_hdlc_txdone_irq, dev); 1097 qmgr_enable_irq(queue_ids[port->id].txdone); 1098 1099 ports_open++; 1100 1101 hss_set_hdlc_cfg(port); 1102 hss_config(port); 1103 1104 hss_start_hdlc(port); 1105 1106 /* we may already have RX data, enables IRQ */ 1107 napi_schedule(&port->napi); 1108 return 0; 1109 1110 err_unlock: 1111 spin_unlock_irqrestore(&npe_lock, flags); 1112 err_destroy_queues: 1113 destroy_hdlc_queues(port); 1114 release_hdlc_queues(port); 1115 err_hdlc_close: 1116 hdlc_close(dev); 1117 return err; 1118 } 1119 1120 static int hss_hdlc_close(struct net_device *dev) 1121 { 1122 struct port *port = dev_to_port(dev); 1123 unsigned long flags; 1124 int i, buffs = RX_DESCS; /* allocated RX buffers */ 1125 1126 spin_lock_irqsave(&npe_lock, flags); 1127 ports_open--; 1128 qmgr_disable_irq(queue_ids[port->id].rx); 1129 netif_stop_queue(dev); 1130 napi_disable(&port->napi); 1131 1132 hss_stop_hdlc(port); 1133 1134 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0) 1135 buffs--; 1136 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0) 1137 buffs--; 1138 1139 if (buffs) 1140 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n", 1141 buffs); 1142 1143 buffs = TX_DESCS; 1144 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0) 1145 buffs--; /* cancel TX */ 1146 1147 i = 0; 1148 do { 1149 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) 1150 buffs--; 1151 if (!buffs) 1152 break; 1153 } while (++i < MAX_CLOSE_WAIT); 1154 1155 if (buffs) 1156 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n", 1157 buffs); 1158 #if DEBUG_CLOSE 1159 if (!buffs) 1160 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); 1161 #endif 1162 qmgr_disable_irq(queue_ids[port->id].txdone); 1163 1164 if (port->plat->close) 1165 port->plat->close(port->id, dev); 1166 spin_unlock_irqrestore(&npe_lock, flags); 1167 1168 destroy_hdlc_queues(port); 1169 release_hdlc_queues(port); 1170 hdlc_close(dev); 1171 return 0; 1172 } 1173 1174 static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding, 1175 unsigned short parity) 1176 { 1177 struct port *port = dev_to_port(dev); 1178 1179 if (encoding != ENCODING_NRZ) 1180 return -EINVAL; 1181 1182 switch (parity) { 1183 case PARITY_CRC16_PR1_CCITT: 1184 port->hdlc_cfg = 0; 1185 return 0; 1186 1187 case PARITY_CRC32_PR1_CCITT: 1188 port->hdlc_cfg = PKT_HDLC_CRC_32; 1189 return 0; 1190 1191 default: 1192 return -EINVAL; 1193 } 1194 } 1195 1196 static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c, 1197 u32 *best, u32 *best_diff, u32 *reg) 1198 { 1199 /* a is 10-bit, b is 10-bit, c is 12-bit */ 1200 u64 new_rate; 1201 u32 new_diff; 1202 1203 new_rate = timer_freq * (u64)(c + 1); 1204 do_div(new_rate, a * (c + 1) + b + 1); 1205 new_diff = abs((u32)new_rate - rate); 1206 1207 if (new_diff < *best_diff) { 1208 *best = new_rate; 1209 *best_diff = new_diff; 1210 *reg = (a << 22) | (b << 12) | c; 1211 } 1212 return new_diff; 1213 } 1214 1215 static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg) 1216 { 1217 u32 a, b, diff = 0xFFFFFFFF; 1218 1219 a = timer_freq / rate; 1220 1221 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */ 1222 check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg); 1223 return; 1224 } 1225 if (a == 0) { /* > 66.666 MHz */ 1226 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */ 1227 rate = timer_freq; 1228 } 1229 1230 if (rate * a == timer_freq) { /* don't divide by 0 later */ 1231 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg); 1232 return; 1233 } 1234 1235 for (b = 0; b < 0x400; b++) { 1236 u64 c = (b + 1) * (u64)rate; 1237 1238 do_div(c, timer_freq - rate * a); 1239 c--; 1240 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */ 1241 if (b == 0 && /* also try a bit higher rate */ 1242 !check_clock(timer_freq, rate, a - 1, 1, 1, best, 1243 &diff, reg)) 1244 return; 1245 check_clock(timer_freq, rate, a, b, 0xFFF, best, 1246 &diff, reg); 1247 return; 1248 } 1249 if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg)) 1250 return; 1251 if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff, 1252 reg)) 1253 return; 1254 } 1255 } 1256 1257 static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1258 { 1259 const size_t size = sizeof(sync_serial_settings); 1260 sync_serial_settings new_line; 1261 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 1262 struct port *port = dev_to_port(dev); 1263 unsigned long flags; 1264 int clk; 1265 1266 if (cmd != SIOCWANDEV) 1267 return hdlc_ioctl(dev, ifr, cmd); 1268 1269 switch (ifr->ifr_settings.type) { 1270 case IF_GET_IFACE: 1271 ifr->ifr_settings.type = IF_IFACE_V35; 1272 if (ifr->ifr_settings.size < size) { 1273 ifr->ifr_settings.size = size; /* data size wanted */ 1274 return -ENOBUFS; 1275 } 1276 memset(&new_line, 0, sizeof(new_line)); 1277 new_line.clock_type = port->clock_type; 1278 new_line.clock_rate = port->clock_rate; 1279 new_line.loopback = port->loopback; 1280 if (copy_to_user(line, &new_line, size)) 1281 return -EFAULT; 1282 return 0; 1283 1284 case IF_IFACE_SYNC_SERIAL: 1285 case IF_IFACE_V35: 1286 if (!capable(CAP_NET_ADMIN)) 1287 return -EPERM; 1288 if (copy_from_user(&new_line, line, size)) 1289 return -EFAULT; 1290 1291 clk = new_line.clock_type; 1292 if (port->plat->set_clock) 1293 clk = port->plat->set_clock(port->id, clk); 1294 1295 if (clk != CLOCK_EXT && clk != CLOCK_INT) 1296 return -EINVAL; /* No such clock setting */ 1297 1298 if (new_line.loopback != 0 && new_line.loopback != 1) 1299 return -EINVAL; 1300 1301 port->clock_type = clk; /* Update settings */ 1302 if (clk == CLOCK_INT) { 1303 find_best_clock(port->plat->timer_freq, 1304 new_line.clock_rate, 1305 &port->clock_rate, &port->clock_reg); 1306 } else { 1307 port->clock_rate = 0; 1308 port->clock_reg = CLK42X_SPEED_2048KHZ; 1309 } 1310 port->loopback = new_line.loopback; 1311 1312 spin_lock_irqsave(&npe_lock, flags); 1313 1314 if (dev->flags & IFF_UP) 1315 hss_config(port); 1316 1317 if (port->loopback || port->carrier) 1318 netif_carrier_on(port->netdev); 1319 else 1320 netif_carrier_off(port->netdev); 1321 spin_unlock_irqrestore(&npe_lock, flags); 1322 1323 return 0; 1324 1325 default: 1326 return hdlc_ioctl(dev, ifr, cmd); 1327 } 1328 } 1329 1330 /***************************************************************************** 1331 * initialization 1332 ****************************************************************************/ 1333 1334 static const struct net_device_ops hss_hdlc_ops = { 1335 .ndo_open = hss_hdlc_open, 1336 .ndo_stop = hss_hdlc_close, 1337 .ndo_start_xmit = hdlc_start_xmit, 1338 .ndo_do_ioctl = hss_hdlc_ioctl, 1339 }; 1340 1341 static int hss_init_one(struct platform_device *pdev) 1342 { 1343 struct port *port; 1344 struct net_device *dev; 1345 hdlc_device *hdlc; 1346 int err; 1347 1348 port = kzalloc(sizeof(*port), GFP_KERNEL); 1349 if (!port) 1350 return -ENOMEM; 1351 1352 port->npe = npe_request(0); 1353 if (!port->npe) { 1354 err = -ENODEV; 1355 goto err_free; 1356 } 1357 1358 dev = alloc_hdlcdev(port); 1359 port->netdev = alloc_hdlcdev(port); 1360 if (!port->netdev) { 1361 err = -ENOMEM; 1362 goto err_plat; 1363 } 1364 1365 SET_NETDEV_DEV(dev, &pdev->dev); 1366 hdlc = dev_to_hdlc(dev); 1367 hdlc->attach = hss_hdlc_attach; 1368 hdlc->xmit = hss_hdlc_xmit; 1369 dev->netdev_ops = &hss_hdlc_ops; 1370 dev->tx_queue_len = 100; 1371 port->clock_type = CLOCK_EXT; 1372 port->clock_rate = 0; 1373 port->clock_reg = CLK42X_SPEED_2048KHZ; 1374 port->id = pdev->id; 1375 port->dev = &pdev->dev; 1376 port->plat = pdev->dev.platform_data; 1377 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT); 1378 1379 err = register_hdlc_device(dev); 1380 if (err) 1381 goto err_free_netdev; 1382 1383 platform_set_drvdata(pdev, port); 1384 1385 netdev_info(dev, "initialized\n"); 1386 return 0; 1387 1388 err_free_netdev: 1389 free_netdev(dev); 1390 err_plat: 1391 npe_release(port->npe); 1392 err_free: 1393 kfree(port); 1394 return err; 1395 } 1396 1397 static int hss_remove_one(struct platform_device *pdev) 1398 { 1399 struct port *port = platform_get_drvdata(pdev); 1400 1401 unregister_hdlc_device(port->netdev); 1402 free_netdev(port->netdev); 1403 npe_release(port->npe); 1404 kfree(port); 1405 return 0; 1406 } 1407 1408 static struct platform_driver ixp4xx_hss_driver = { 1409 .driver.name = DRV_NAME, 1410 .probe = hss_init_one, 1411 .remove = hss_remove_one, 1412 }; 1413 1414 static int __init hss_init_module(void) 1415 { 1416 if ((ixp4xx_read_feature_bits() & 1417 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) != 1418 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) 1419 return -ENODEV; 1420 1421 return platform_driver_register(&ixp4xx_hss_driver); 1422 } 1423 1424 static void __exit hss_cleanup_module(void) 1425 { 1426 platform_driver_unregister(&ixp4xx_hss_driver); 1427 } 1428 1429 MODULE_AUTHOR("Krzysztof Halasa"); 1430 MODULE_DESCRIPTION("Intel IXP4xx HSS driver"); 1431 MODULE_LICENSE("GPL v2"); 1432 MODULE_ALIAS("platform:ixp4xx_hss"); 1433 module_init(hss_init_module); 1434 module_exit(hss_cleanup_module); 1435