| cpsw.c (c74a7469f97c0f40b46e82ee979f9fb1bb6e847c) | cpsw.c (79b3325d0d87a6b3af96485ff8029bcc26e070e3) |
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| 1/* 2 * Texas Instruments Ethernet Switch Driver 3 * 4 * Copyright (C) 2012 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. --- 239 unchanged lines hidden (view full) --- 248#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 249#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 250#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 251#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 252#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 253#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 254 255/* Bit definitions for the CPSW2_CONTROL register */ | 1/* 2 * Texas Instruments Ethernet Switch Driver 3 * 4 * Copyright (C) 2012 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. --- 239 unchanged lines hidden (view full) --- 248#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 249#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 250#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 251#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 252#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 253#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 254 255/* Bit definitions for the CPSW2_CONTROL register */ |
| 256#define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 257#define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 258#define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 259#define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 260#define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 261#define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 262#define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 263#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 264#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 265#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 266#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ 267#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ 268#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 269#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 270#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 271#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 272#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ | 256#define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */ 257#define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */ 258#define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */ 259#define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */ 260#define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */ 261#define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */ 262#define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */ 263#define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */ 264#define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */ 265#define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */ 266#define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */ 267#define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */ 268#define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */ 269#define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */ 270#define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */ 271#define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */ 272#define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */ 273#define TS_RX_EN BIT(0) /* Time Sync Receive Enable */ |
| 273 274#define CTRL_V2_TS_BITS \ 275 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 276 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 277 278#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 279#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 280#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 281 282 283#define CTRL_V3_TS_BITS \ | 274 275#define CTRL_V2_TS_BITS \ 276 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ 277 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN) 278 279#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN) 280#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN) 281#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN) 282 283 284#define CTRL_V3_TS_BITS \ |
| 284 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ | 285 (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ |
| 285 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 286 TS_LTYPE1_EN) 287 288#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 289#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 290#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 291 292/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ --- 669 unchanged lines hidden (view full) --- 962{ 963 u32 ch_map; 964 int num_tx, cur_budget, ch; 965 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 966 struct cpsw_vector *txv; 967 968 /* process every unprocessed channel */ 969 ch_map = cpdma_ctrl_txchs_state(cpsw->dma); | 286 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ 287 TS_LTYPE1_EN) 288 289#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN) 290#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN) 291#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN) 292 293/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ --- 669 unchanged lines hidden (view full) --- 963{ 964 u32 ch_map; 965 int num_tx, cur_budget, ch; 966 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx); 967 struct cpsw_vector *txv; 968 969 /* process every unprocessed channel */ 970 ch_map = cpdma_ctrl_txchs_state(cpsw->dma); |
| 970 for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) { 971 if (!(ch_map & 0x01)) | 971 for (ch = 0, num_tx = 0; ch_map & 0xff; ch_map <<= 1, ch++) { 972 if (!(ch_map & 0x80)) |
| 972 continue; 973 974 txv = &cpsw->txv[ch]; 975 if (unlikely(txv->budget > budget - num_tx)) 976 cur_budget = budget - num_tx; 977 else 978 cur_budget = txv->budget; 979 --- 1446 unchanged lines hidden (view full) --- 2426} 2427 2428static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx) 2429{ 2430 struct cpsw_common *cpsw = priv->cpsw; 2431 void (*handler)(void *, int, int); 2432 struct netdev_queue *queue; 2433 struct cpsw_vector *vec; | 973 continue; 974 975 txv = &cpsw->txv[ch]; 976 if (unlikely(txv->budget > budget - num_tx)) 977 cur_budget = budget - num_tx; 978 else 979 cur_budget = txv->budget; 980 --- 1446 unchanged lines hidden (view full) --- 2427} 2428 2429static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx) 2430{ 2431 struct cpsw_common *cpsw = priv->cpsw; 2432 void (*handler)(void *, int, int); 2433 struct netdev_queue *queue; 2434 struct cpsw_vector *vec; |
| 2434 int ret, *ch; | 2435 int ret, *ch, vch; |
| 2435 2436 if (rx) { 2437 ch = &cpsw->rx_ch_num; 2438 vec = cpsw->rxv; 2439 handler = cpsw_rx_handler; 2440 } else { 2441 ch = &cpsw->tx_ch_num; 2442 vec = cpsw->txv; 2443 handler = cpsw_tx_handler; 2444 } 2445 2446 while (*ch < ch_num) { | 2436 2437 if (rx) { 2438 ch = &cpsw->rx_ch_num; 2439 vec = cpsw->rxv; 2440 handler = cpsw_rx_handler; 2441 } else { 2442 ch = &cpsw->tx_ch_num; 2443 vec = cpsw->txv; 2444 handler = cpsw_tx_handler; 2445 } 2446 2447 while (*ch < ch_num) { |
| 2447 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx); | 2448 vch = rx ? *ch : 7 - *ch; 2449 vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx); |
| 2448 queue = netdev_get_tx_queue(priv->ndev, *ch); 2449 queue->tx_maxrate = 0; 2450 2451 if (IS_ERR(vec[*ch].ch)) 2452 return PTR_ERR(vec[*ch].ch); 2453 2454 if (!vec[*ch].ch) 2455 return -EINVAL; --- 466 unchanged lines hidden (view full) --- 2922 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2923 2924 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2925 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2926 ETH_ALEN); 2927 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n", 2928 priv_sl2->mac_addr); 2929 } else { | 2450 queue = netdev_get_tx_queue(priv->ndev, *ch); 2451 queue->tx_maxrate = 0; 2452 2453 if (IS_ERR(vec[*ch].ch)) 2454 return PTR_ERR(vec[*ch].ch); 2455 2456 if (!vec[*ch].ch) 2457 return -EINVAL; --- 466 unchanged lines hidden (view full) --- 2924 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 2925 2926 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 2927 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 2928 ETH_ALEN); 2929 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n", 2930 priv_sl2->mac_addr); 2931 } else { |
| 2930 random_ether_addr(priv_sl2->mac_addr); | 2932 eth_random_addr(priv_sl2->mac_addr); |
| 2931 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n", 2932 priv_sl2->mac_addr); 2933 } 2934 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2935 2936 priv_sl2->emac_port = 1; 2937 cpsw->slaves[1].ndev = ndev; 2938 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; --- 37 unchanged lines hidden (view full) --- 2976 struct cpsw_ale_params ale_params; 2977 void __iomem *ss_regs; 2978 void __iomem *cpts_regs; 2979 struct resource *res, *ss_res; 2980 struct gpio_descs *mode; 2981 u32 slave_offset, sliver_offset, slave_size; 2982 const struct soc_device_attribute *soc; 2983 struct cpsw_common *cpsw; | 2933 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n", 2934 priv_sl2->mac_addr); 2935 } 2936 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 2937 2938 priv_sl2->emac_port = 1; 2939 cpsw->slaves[1].ndev = ndev; 2940 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; --- 37 unchanged lines hidden (view full) --- 2978 struct cpsw_ale_params ale_params; 2979 void __iomem *ss_regs; 2980 void __iomem *cpts_regs; 2981 struct resource *res, *ss_res; 2982 struct gpio_descs *mode; 2983 u32 slave_offset, sliver_offset, slave_size; 2984 const struct soc_device_attribute *soc; 2985 struct cpsw_common *cpsw; |
| 2984 int ret = 0, i; | 2986 int ret = 0, i, ch; |
| 2985 int irq; 2986 2987 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); 2988 if (!cpsw) 2989 return -ENOMEM; 2990 2991 cpsw->dev = &pdev->dev; 2992 --- 158 unchanged lines hidden (view full) --- 3151 ret = -ENOMEM; 3152 goto clean_dt_ret; 3153 } 3154 3155 soc = soc_device_match(cpsw_soc_devices); 3156 if (soc) 3157 cpsw->quirk_irq = 1; 3158 | 2987 int irq; 2988 2989 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); 2990 if (!cpsw) 2991 return -ENOMEM; 2992 2993 cpsw->dev = &pdev->dev; 2994 --- 158 unchanged lines hidden (view full) --- 3153 ret = -ENOMEM; 3154 goto clean_dt_ret; 3155 } 3156 3157 soc = soc_device_match(cpsw_soc_devices); 3158 if (soc) 3159 cpsw->quirk_irq = 1; 3160 |
| 3159 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0); | 3161 ch = cpsw->quirk_irq ? 0 : 7; 3162 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0); |
| 3160 if (IS_ERR(cpsw->txv[0].ch)) { 3161 dev_err(priv->dev, "error initializing tx dma channel\n"); 3162 ret = PTR_ERR(cpsw->txv[0].ch); 3163 goto clean_dma_ret; 3164 } 3165 3166 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); 3167 if (IS_ERR(cpsw->rxv[0].ch)) { --- 217 unchanged lines hidden --- | 3163 if (IS_ERR(cpsw->txv[0].ch)) { 3164 dev_err(priv->dev, "error initializing tx dma channel\n"); 3165 ret = PTR_ERR(cpsw->txv[0].ch); 3166 goto clean_dma_ret; 3167 } 3168 3169 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); 3170 if (IS_ERR(cpsw->rxv[0].ch)) { --- 217 unchanged lines hidden --- |