pci.c (9938b04472d5c59f8bd8152a548533a8599596a2) pci.c (e009a7e858fed215cb4eed5174a31cadd42d8797)
1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */

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16#include <linux/sort.h>
17#include <linux/pci.h>
18#include <linux/of.h>
19#include <linux/delay.h>
20#include <asm/opal.h>
21#include <asm/msi_bitmap.h>
22#include <asm/pnv-pci.h>
23#include <asm/io.h>
1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */

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16#include <linux/sort.h>
17#include <linux/pci.h>
18#include <linux/of.h>
19#include <linux/delay.h>
20#include <asm/opal.h>
21#include <asm/msi_bitmap.h>
22#include <asm/pnv-pci.h>
23#include <asm/io.h>
24#include <asm/reg.h>
24
25#include "cxl.h"
26#include <misc/cxl.h>
27
28
29#define CXL_PCI_VSEC_ID 0x1280
30#define CXL_VSEC_MIN_SIZE 0x80
31

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316 for (i = 0; i < afu_cr_num; i++) {
317 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
318 show_reg("CR Vendor", val & 0xffff);
319 show_reg("CR Device", (val >> 16) & 0xffff);
320 }
321#undef show_reg
322}
323
25
26#include "cxl.h"
27#include <misc/cxl.h>
28
29
30#define CXL_PCI_VSEC_ID 0x1280
31#define CXL_VSEC_MIN_SIZE 0x80
32

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317 for (i = 0; i < afu_cr_num; i++) {
318 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
319 show_reg("CR Vendor", val & 0xffff);
320 show_reg("CR Device", (val >> 16) & 0xffff);
321 }
322#undef show_reg
323}
324
325#define CAPP_UNIT0_ID 0xBA
326#define CAPP_UNIT1_ID 0XBE
327
328static u64 get_capp_unit_id(struct device_node *np)
329{
330 u32 phb_index;
331
332 /*
333 * For chips other than POWER8NVL, we only have CAPP 0,
334 * irrespective of which PHB is used.
335 */
336 if (!pvr_version_is(PVR_POWER8NVL))
337 return CAPP_UNIT0_ID;
338
339 /*
340 * For POWER8NVL, assume CAPP 0 is attached to PHB0 and
341 * CAPP 1 is attached to PHB1.
342 */
343 if (of_property_read_u32(np, "ibm,phb-index", &phb_index))
344 return 0;
345
346 if (phb_index == 0)
347 return CAPP_UNIT0_ID;
348
349 if (phb_index == 1)
350 return CAPP_UNIT1_ID;
351
352 return 0;
353}
354
324static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
325{
326 struct device_node *np;
327 const __be32 *prop;
328 u64 psl_dsnctl;
329 u64 chipid;
355static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
356{
357 struct device_node *np;
358 const __be32 *prop;
359 u64 psl_dsnctl;
360 u64 chipid;
361 u64 capp_unit_id;
330
331 if (!(np = pnv_pci_get_phb_node(dev)))
332 return -ENODEV;
333
334 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
335 np = of_get_next_parent(np);
336 if (!np)
337 return -ENODEV;
338 chipid = be32_to_cpup(prop);
362
363 if (!(np = pnv_pci_get_phb_node(dev)))
364 return -ENODEV;
365
366 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
367 np = of_get_next_parent(np);
368 if (!np)
369 return -ENODEV;
370 chipid = be32_to_cpup(prop);
371 capp_unit_id = get_capp_unit_id(np);
339 of_node_put(np);
372 of_node_put(np);
373 if (!capp_unit_id) {
374 pr_err("cxl: invalid capp unit id\n");
375 return -ENODEV;
376 }
340
341 /* Tell PSL where to route data to */
377
378 /* Tell PSL where to route data to */
342 psl_dsnctl = 0x02E8900002000000ULL | (chipid << (63-5));
379 psl_dsnctl = 0x0000900002000000ULL | (chipid << (63-5));
380 psl_dsnctl |= (capp_unit_id << (63-13));
381
343 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
344 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
345 /* snoop write mask */
346 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
347 /* set fir_accum */
348 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL);
349 /* for debugging with trace arrays */
350 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
351
352 return 0;
353}
354
355#define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
356#define _2048_250MHZ_CYCLES 1
357
382 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
383 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
384 /* snoop write mask */
385 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
386 /* set fir_accum */
387 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL);
388 /* for debugging with trace arrays */
389 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
390
391 return 0;
392}
393
394#define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
395#define _2048_250MHZ_CYCLES 1
396
358static int cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
397static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
359{
360 u64 psl_tb;
361 int delta;
362 unsigned int retry = 0;
363 struct device_node *np;
364
398{
399 u64 psl_tb;
400 int delta;
401 unsigned int retry = 0;
402 struct device_node *np;
403
404 adapter->psl_timebase_synced = false;
405
365 if (!(np = pnv_pci_get_phb_node(dev)))
406 if (!(np = pnv_pci_get_phb_node(dev)))
366 return -ENODEV;
407 return;
367
368 /* Do not fail when CAPP timebase sync is not supported by OPAL */
369 of_node_get(np);
370 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
371 of_node_put(np);
408
409 /* Do not fail when CAPP timebase sync is not supported by OPAL */
410 of_node_get(np);
411 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
412 of_node_put(np);
372 pr_err("PSL: Timebase sync: OPAL support missing\n");
373 return 0;
413 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
414 return;
374 }
375 of_node_put(np);
376
377 /*
378 * Setup PSL Timebase Control and Status register
379 * with the recommended Timebase Sync Count value
380 */
381 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
382 TBSYNC_CNT(2 * _2048_250MHZ_CYCLES));
383
384 /* Enable PSL Timebase */
385 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
386 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
387
388 /* Wait until CORE TB and PSL TB difference <= 16usecs */
389 do {
390 msleep(1);
391 if (retry++ > 5) {
415 }
416 of_node_put(np);
417
418 /*
419 * Setup PSL Timebase Control and Status register
420 * with the recommended Timebase Sync Count value
421 */
422 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
423 TBSYNC_CNT(2 * _2048_250MHZ_CYCLES));
424
425 /* Enable PSL Timebase */
426 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
427 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
428
429 /* Wait until CORE TB and PSL TB difference <= 16usecs */
430 do {
431 msleep(1);
432 if (retry++ > 5) {
392 pr_err("PSL: Timebase sync: giving up!\n");
393 return -EIO;
433 dev_info(&dev->dev, "PSL timebase can't synchronize\n");
434 return;
394 }
395 psl_tb = cxl_p1_read(adapter, CXL_PSL_Timebase);
396 delta = mftb() - psl_tb;
397 if (delta < 0)
398 delta = -delta;
399 } while (tb_to_ns(delta) > 16000);
400
435 }
436 psl_tb = cxl_p1_read(adapter, CXL_PSL_Timebase);
437 delta = mftb() - psl_tb;
438 if (delta < 0)
439 delta = -delta;
440 } while (tb_to_ns(delta) > 16000);
441
401 return 0;
442 adapter->psl_timebase_synced = true;
443 return;
402}
403
404static int init_implementation_afu_regs(struct cxl_afu *afu)
405{
406 /* read/write masks for this slice */
407 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
408 /* APC read/write masks for this slice */
409 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);

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1139 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI)))
1140 goto err;
1141
1142 /* If recovery happened, the last step is to turn on snooping.
1143 * In the non-recovery case this has no effect */
1144 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1145 goto err;
1146
444}
445
446static int init_implementation_afu_regs(struct cxl_afu *afu)
447{
448 /* read/write masks for this slice */
449 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
450 /* APC read/write masks for this slice */
451 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);

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1181 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI)))
1182 goto err;
1183
1184 /* If recovery happened, the last step is to turn on snooping.
1185 * In the non-recovery case this has no effect */
1186 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1187 goto err;
1188
1147 if ((rc = cxl_setup_psl_timebase(adapter, dev)))
1148 goto err;
1189 /* Ignore error, adapter init is not dependant on timebase sync */
1190 cxl_setup_psl_timebase(adapter, dev);
1149
1150 if ((rc = cxl_native_register_psl_err_irq(adapter)))
1151 goto err;
1152
1153 return 0;
1154
1155err:
1156 cxl_unmap_adapter_regs(adapter);

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1192 if ((rc = cxl_native_register_psl_err_irq(adapter)))
1193 goto err;
1194
1195 return 0;
1196
1197err:
1198 cxl_unmap_adapter_regs(adapter);

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