1 /* 2 * Copyright 2014 IBM Corp. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 */ 9 10 #include <linux/pci_regs.h> 11 #include <linux/pci_ids.h> 12 #include <linux/device.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/sort.h> 17 #include <linux/pci.h> 18 #include <linux/of.h> 19 #include <linux/delay.h> 20 #include <asm/opal.h> 21 #include <asm/msi_bitmap.h> 22 #include <asm/pnv-pci.h> 23 #include <asm/io.h> 24 #include <asm/reg.h> 25 26 #include "cxl.h" 27 #include <misc/cxl.h> 28 29 30 #define CXL_PCI_VSEC_ID 0x1280 31 #define CXL_VSEC_MIN_SIZE 0x80 32 33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \ 34 { \ 35 pci_read_config_word(dev, vsec + 0x6, dest); \ 36 *dest >>= 4; \ 37 } 38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \ 39 pci_read_config_byte(dev, vsec + 0x8, dest) 40 41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \ 42 pci_read_config_byte(dev, vsec + 0x9, dest) 43 #define CXL_STATUS_SECOND_PORT 0x80 44 #define CXL_STATUS_MSI_X_FULL 0x40 45 #define CXL_STATUS_MSI_X_SINGLE 0x20 46 #define CXL_STATUS_FLASH_RW 0x08 47 #define CXL_STATUS_FLASH_RO 0x04 48 #define CXL_STATUS_LOADABLE_AFU 0x02 49 #define CXL_STATUS_LOADABLE_PSL 0x01 50 /* If we see these features we won't try to use the card */ 51 #define CXL_UNSUPPORTED_FEATURES \ 52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE) 53 54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \ 55 pci_read_config_byte(dev, vsec + 0xa, dest) 56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \ 57 pci_write_config_byte(dev, vsec + 0xa, val) 58 #define CXL_VSEC_PROTOCOL_MASK 0xe0 59 #define CXL_VSEC_PROTOCOL_1024TB 0x80 60 #define CXL_VSEC_PROTOCOL_512TB 0x40 61 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8 uses this */ 62 #define CXL_VSEC_PROTOCOL_ENABLE 0x01 63 64 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \ 65 pci_read_config_word(dev, vsec + 0xc, dest) 66 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \ 67 pci_read_config_byte(dev, vsec + 0xe, dest) 68 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \ 69 pci_read_config_byte(dev, vsec + 0xf, dest) 70 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \ 71 pci_read_config_word(dev, vsec + 0x10, dest) 72 73 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \ 74 pci_read_config_byte(dev, vsec + 0x13, dest) 75 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \ 76 pci_write_config_byte(dev, vsec + 0x13, val) 77 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */ 78 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */ 79 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */ 80 81 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \ 82 pci_read_config_dword(dev, vsec + 0x20, dest) 83 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \ 84 pci_read_config_dword(dev, vsec + 0x24, dest) 85 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \ 86 pci_read_config_dword(dev, vsec + 0x28, dest) 87 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \ 88 pci_read_config_dword(dev, vsec + 0x2c, dest) 89 90 91 /* This works a little different than the p1/p2 register accesses to make it 92 * easier to pull out individual fields */ 93 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off) 94 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off) 95 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit))) 96 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be)) 97 98 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0) 99 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15) 100 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31) 101 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47) 102 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48) 103 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55) 104 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59) 105 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61) 106 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63) 107 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20) 108 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 109 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28) 110 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30) 111 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6) 112 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7) 113 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 114 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38) 115 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40) 116 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63) 117 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48) 118 119 static const struct pci_device_id cxl_pci_tbl[] = { 120 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), }, 121 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), }, 122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), }, 123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), }, 124 { PCI_DEVICE_CLASS(0x120000, ~0), }, 125 126 { } 127 }; 128 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl); 129 130 131 /* 132 * Mostly using these wrappers to avoid confusion: 133 * priv 1 is BAR2, while priv 2 is BAR0 134 */ 135 static inline resource_size_t p1_base(struct pci_dev *dev) 136 { 137 return pci_resource_start(dev, 2); 138 } 139 140 static inline resource_size_t p1_size(struct pci_dev *dev) 141 { 142 return pci_resource_len(dev, 2); 143 } 144 145 static inline resource_size_t p2_base(struct pci_dev *dev) 146 { 147 return pci_resource_start(dev, 0); 148 } 149 150 static inline resource_size_t p2_size(struct pci_dev *dev) 151 { 152 return pci_resource_len(dev, 0); 153 } 154 155 static int find_cxl_vsec(struct pci_dev *dev) 156 { 157 int vsec = 0; 158 u16 val; 159 160 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) { 161 pci_read_config_word(dev, vsec + 0x4, &val); 162 if (val == CXL_PCI_VSEC_ID) 163 return vsec; 164 } 165 return 0; 166 167 } 168 169 static void dump_cxl_config_space(struct pci_dev *dev) 170 { 171 int vsec; 172 u32 val; 173 174 dev_info(&dev->dev, "dump_cxl_config_space\n"); 175 176 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val); 177 dev_info(&dev->dev, "BAR0: %#.8x\n", val); 178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val); 179 dev_info(&dev->dev, "BAR1: %#.8x\n", val); 180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val); 181 dev_info(&dev->dev, "BAR2: %#.8x\n", val); 182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val); 183 dev_info(&dev->dev, "BAR3: %#.8x\n", val); 184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val); 185 dev_info(&dev->dev, "BAR4: %#.8x\n", val); 186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val); 187 dev_info(&dev->dev, "BAR5: %#.8x\n", val); 188 189 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n", 190 p1_base(dev), p1_size(dev)); 191 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n", 192 p2_base(dev), p2_size(dev)); 193 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n", 194 pci_resource_start(dev, 4), pci_resource_len(dev, 4)); 195 196 if (!(vsec = find_cxl_vsec(dev))) 197 return; 198 199 #define show_reg(name, what) \ 200 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what) 201 202 pci_read_config_dword(dev, vsec + 0x0, &val); 203 show_reg("Cap ID", (val >> 0) & 0xffff); 204 show_reg("Cap Ver", (val >> 16) & 0xf); 205 show_reg("Next Cap Ptr", (val >> 20) & 0xfff); 206 pci_read_config_dword(dev, vsec + 0x4, &val); 207 show_reg("VSEC ID", (val >> 0) & 0xffff); 208 show_reg("VSEC Rev", (val >> 16) & 0xf); 209 show_reg("VSEC Length", (val >> 20) & 0xfff); 210 pci_read_config_dword(dev, vsec + 0x8, &val); 211 show_reg("Num AFUs", (val >> 0) & 0xff); 212 show_reg("Status", (val >> 8) & 0xff); 213 show_reg("Mode Control", (val >> 16) & 0xff); 214 show_reg("Reserved", (val >> 24) & 0xff); 215 pci_read_config_dword(dev, vsec + 0xc, &val); 216 show_reg("PSL Rev", (val >> 0) & 0xffff); 217 show_reg("CAIA Ver", (val >> 16) & 0xffff); 218 pci_read_config_dword(dev, vsec + 0x10, &val); 219 show_reg("Base Image Rev", (val >> 0) & 0xffff); 220 show_reg("Reserved", (val >> 16) & 0x0fff); 221 show_reg("Image Control", (val >> 28) & 0x3); 222 show_reg("Reserved", (val >> 30) & 0x1); 223 show_reg("Image Loaded", (val >> 31) & 0x1); 224 225 pci_read_config_dword(dev, vsec + 0x14, &val); 226 show_reg("Reserved", val); 227 pci_read_config_dword(dev, vsec + 0x18, &val); 228 show_reg("Reserved", val); 229 pci_read_config_dword(dev, vsec + 0x1c, &val); 230 show_reg("Reserved", val); 231 232 pci_read_config_dword(dev, vsec + 0x20, &val); 233 show_reg("AFU Descriptor Offset", val); 234 pci_read_config_dword(dev, vsec + 0x24, &val); 235 show_reg("AFU Descriptor Size", val); 236 pci_read_config_dword(dev, vsec + 0x28, &val); 237 show_reg("Problem State Offset", val); 238 pci_read_config_dword(dev, vsec + 0x2c, &val); 239 show_reg("Problem State Size", val); 240 241 pci_read_config_dword(dev, vsec + 0x30, &val); 242 show_reg("Reserved", val); 243 pci_read_config_dword(dev, vsec + 0x34, &val); 244 show_reg("Reserved", val); 245 pci_read_config_dword(dev, vsec + 0x38, &val); 246 show_reg("Reserved", val); 247 pci_read_config_dword(dev, vsec + 0x3c, &val); 248 show_reg("Reserved", val); 249 250 pci_read_config_dword(dev, vsec + 0x40, &val); 251 show_reg("PSL Programming Port", val); 252 pci_read_config_dword(dev, vsec + 0x44, &val); 253 show_reg("PSL Programming Control", val); 254 255 pci_read_config_dword(dev, vsec + 0x48, &val); 256 show_reg("Reserved", val); 257 pci_read_config_dword(dev, vsec + 0x4c, &val); 258 show_reg("Reserved", val); 259 260 pci_read_config_dword(dev, vsec + 0x50, &val); 261 show_reg("Flash Address Register", val); 262 pci_read_config_dword(dev, vsec + 0x54, &val); 263 show_reg("Flash Size Register", val); 264 pci_read_config_dword(dev, vsec + 0x58, &val); 265 show_reg("Flash Status/Control Register", val); 266 pci_read_config_dword(dev, vsec + 0x58, &val); 267 show_reg("Flash Data Port", val); 268 269 #undef show_reg 270 } 271 272 static void dump_afu_descriptor(struct cxl_afu *afu) 273 { 274 u64 val, afu_cr_num, afu_cr_off, afu_cr_len; 275 int i; 276 277 #define show_reg(name, what) \ 278 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what) 279 280 val = AFUD_READ_INFO(afu); 281 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val)); 282 show_reg("num_of_processes", AFUD_NUM_PROCS(val)); 283 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val)); 284 show_reg("req_prog_mode", val & 0xffffULL); 285 afu_cr_num = AFUD_NUM_CRS(val); 286 287 val = AFUD_READ(afu, 0x8); 288 show_reg("Reserved", val); 289 val = AFUD_READ(afu, 0x10); 290 show_reg("Reserved", val); 291 val = AFUD_READ(afu, 0x18); 292 show_reg("Reserved", val); 293 294 val = AFUD_READ_CR(afu); 295 show_reg("Reserved", (val >> (63-7)) & 0xff); 296 show_reg("AFU_CR_len", AFUD_CR_LEN(val)); 297 afu_cr_len = AFUD_CR_LEN(val) * 256; 298 299 val = AFUD_READ_CR_OFF(afu); 300 afu_cr_off = val; 301 show_reg("AFU_CR_offset", val); 302 303 val = AFUD_READ_PPPSA(afu); 304 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff); 305 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val)); 306 307 val = AFUD_READ_PPPSA_OFF(afu); 308 show_reg("PerProcessPSA_offset", val); 309 310 val = AFUD_READ_EB(afu); 311 show_reg("Reserved", (val >> (63-7)) & 0xff); 312 show_reg("AFU_EB_len", AFUD_EB_LEN(val)); 313 314 val = AFUD_READ_EB_OFF(afu); 315 show_reg("AFU_EB_offset", val); 316 317 for (i = 0; i < afu_cr_num; i++) { 318 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len); 319 show_reg("CR Vendor", val & 0xffff); 320 show_reg("CR Device", (val >> 16) & 0xffff); 321 } 322 #undef show_reg 323 } 324 325 #define CAPP_UNIT0_ID 0xBA 326 #define CAPP_UNIT1_ID 0XBE 327 328 static u64 get_capp_unit_id(struct device_node *np) 329 { 330 u32 phb_index; 331 332 /* 333 * For chips other than POWER8NVL, we only have CAPP 0, 334 * irrespective of which PHB is used. 335 */ 336 if (!pvr_version_is(PVR_POWER8NVL)) 337 return CAPP_UNIT0_ID; 338 339 /* 340 * For POWER8NVL, assume CAPP 0 is attached to PHB0 and 341 * CAPP 1 is attached to PHB1. 342 */ 343 if (of_property_read_u32(np, "ibm,phb-index", &phb_index)) 344 return 0; 345 346 if (phb_index == 0) 347 return CAPP_UNIT0_ID; 348 349 if (phb_index == 1) 350 return CAPP_UNIT1_ID; 351 352 return 0; 353 } 354 355 static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev) 356 { 357 struct device_node *np; 358 const __be32 *prop; 359 u64 psl_dsnctl; 360 u64 chipid; 361 u64 capp_unit_id; 362 363 if (!(np = pnv_pci_get_phb_node(dev))) 364 return -ENODEV; 365 366 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL))) 367 np = of_get_next_parent(np); 368 if (!np) 369 return -ENODEV; 370 chipid = be32_to_cpup(prop); 371 capp_unit_id = get_capp_unit_id(np); 372 of_node_put(np); 373 if (!capp_unit_id) { 374 pr_err("cxl: invalid capp unit id\n"); 375 return -ENODEV; 376 } 377 378 /* Tell PSL where to route data to */ 379 psl_dsnctl = 0x0000900002000000ULL | (chipid << (63-5)); 380 psl_dsnctl |= (capp_unit_id << (63-13)); 381 382 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl); 383 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL); 384 /* snoop write mask */ 385 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL); 386 /* set fir_accum */ 387 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, 0x0800000000000000ULL); 388 /* for debugging with trace arrays */ 389 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL); 390 391 return 0; 392 } 393 394 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6)) 395 #define _2048_250MHZ_CYCLES 1 396 397 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev) 398 { 399 u64 psl_tb; 400 int delta; 401 unsigned int retry = 0; 402 struct device_node *np; 403 404 adapter->psl_timebase_synced = false; 405 406 if (!(np = pnv_pci_get_phb_node(dev))) 407 return; 408 409 /* Do not fail when CAPP timebase sync is not supported by OPAL */ 410 of_node_get(np); 411 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) { 412 of_node_put(np); 413 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n"); 414 return; 415 } 416 of_node_put(np); 417 418 /* 419 * Setup PSL Timebase Control and Status register 420 * with the recommended Timebase Sync Count value 421 */ 422 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT, 423 TBSYNC_CNT(2 * _2048_250MHZ_CYCLES)); 424 425 /* Enable PSL Timebase */ 426 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000); 427 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb); 428 429 /* Wait until CORE TB and PSL TB difference <= 16usecs */ 430 do { 431 msleep(1); 432 if (retry++ > 5) { 433 dev_info(&dev->dev, "PSL timebase can't synchronize\n"); 434 return; 435 } 436 psl_tb = cxl_p1_read(adapter, CXL_PSL_Timebase); 437 delta = mftb() - psl_tb; 438 if (delta < 0) 439 delta = -delta; 440 } while (tb_to_ns(delta) > 16000); 441 442 adapter->psl_timebase_synced = true; 443 return; 444 } 445 446 static int init_implementation_afu_regs(struct cxl_afu *afu) 447 { 448 /* read/write masks for this slice */ 449 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL); 450 /* APC read/write masks for this slice */ 451 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL); 452 /* for debugging with trace arrays */ 453 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL); 454 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S); 455 456 return 0; 457 } 458 459 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, 460 unsigned int virq) 461 { 462 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 463 464 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq); 465 } 466 467 int cxl_update_image_control(struct cxl *adapter) 468 { 469 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 470 int rc; 471 int vsec; 472 u8 image_state; 473 474 if (!(vsec = find_cxl_vsec(dev))) { 475 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 476 return -ENODEV; 477 } 478 479 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) { 480 dev_err(&dev->dev, "failed to read image state: %i\n", rc); 481 return rc; 482 } 483 484 if (adapter->perst_loads_image) 485 image_state |= CXL_VSEC_PERST_LOADS_IMAGE; 486 else 487 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE; 488 489 if (adapter->perst_select_user) 490 image_state |= CXL_VSEC_PERST_SELECT_USER; 491 else 492 image_state &= ~CXL_VSEC_PERST_SELECT_USER; 493 494 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) { 495 dev_err(&dev->dev, "failed to update image control: %i\n", rc); 496 return rc; 497 } 498 499 return 0; 500 } 501 502 int cxl_pci_alloc_one_irq(struct cxl *adapter) 503 { 504 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 505 506 return pnv_cxl_alloc_hwirqs(dev, 1); 507 } 508 509 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq) 510 { 511 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 512 513 return pnv_cxl_release_hwirqs(dev, hwirq, 1); 514 } 515 516 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, 517 struct cxl *adapter, unsigned int num) 518 { 519 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 520 521 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num); 522 } 523 524 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, 525 struct cxl *adapter) 526 { 527 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 528 529 pnv_cxl_release_hwirq_ranges(irqs, dev); 530 } 531 532 static int setup_cxl_bars(struct pci_dev *dev) 533 { 534 /* Safety check in case we get backported to < 3.17 without M64 */ 535 if ((p1_base(dev) < 0x100000000ULL) || 536 (p2_base(dev) < 0x100000000ULL)) { 537 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n"); 538 return -ENODEV; 539 } 540 541 /* 542 * BAR 4/5 has a special meaning for CXL and must be programmed with a 543 * special value corresponding to the CXL protocol address range. 544 * For POWER 8 that means bits 48:49 must be set to 10 545 */ 546 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000); 547 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000); 548 549 return 0; 550 } 551 552 /* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */ 553 static int switch_card_to_cxl(struct pci_dev *dev) 554 { 555 int vsec; 556 u8 val; 557 int rc; 558 559 dev_info(&dev->dev, "switch card to CXL\n"); 560 561 if (!(vsec = find_cxl_vsec(dev))) { 562 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 563 return -ENODEV; 564 } 565 566 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) { 567 dev_err(&dev->dev, "failed to read current mode control: %i", rc); 568 return rc; 569 } 570 val &= ~CXL_VSEC_PROTOCOL_MASK; 571 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE; 572 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) { 573 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc); 574 return rc; 575 } 576 /* 577 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states 578 * we must wait 100ms after this mode switch before touching 579 * PCIe config space. 580 */ 581 msleep(100); 582 583 return 0; 584 } 585 586 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) 587 { 588 u64 p1n_base, p2n_base, afu_desc; 589 const u64 p1n_size = 0x100; 590 const u64 p2n_size = 0x1000; 591 592 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); 593 p2n_base = p2_base(dev) + (afu->slice * p2n_size); 594 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size)); 595 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size); 596 597 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size))) 598 goto err; 599 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size))) 600 goto err1; 601 if (afu_desc) { 602 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size))) 603 goto err2; 604 } 605 606 return 0; 607 err2: 608 iounmap(afu->p2n_mmio); 609 err1: 610 iounmap(afu->native->p1n_mmio); 611 err: 612 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n"); 613 return -ENOMEM; 614 } 615 616 static void pci_unmap_slice_regs(struct cxl_afu *afu) 617 { 618 if (afu->p2n_mmio) { 619 iounmap(afu->p2n_mmio); 620 afu->p2n_mmio = NULL; 621 } 622 if (afu->native->p1n_mmio) { 623 iounmap(afu->native->p1n_mmio); 624 afu->native->p1n_mmio = NULL; 625 } 626 if (afu->native->afu_desc_mmio) { 627 iounmap(afu->native->afu_desc_mmio); 628 afu->native->afu_desc_mmio = NULL; 629 } 630 } 631 632 void cxl_pci_release_afu(struct device *dev) 633 { 634 struct cxl_afu *afu = to_cxl_afu(dev); 635 636 pr_devel("%s\n", __func__); 637 638 idr_destroy(&afu->contexts_idr); 639 cxl_release_spa(afu); 640 641 kfree(afu->native); 642 kfree(afu); 643 } 644 645 /* Expects AFU struct to have recently been zeroed out */ 646 static int cxl_read_afu_descriptor(struct cxl_afu *afu) 647 { 648 u64 val; 649 650 val = AFUD_READ_INFO(afu); 651 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val); 652 afu->max_procs_virtualised = AFUD_NUM_PROCS(val); 653 afu->crs_num = AFUD_NUM_CRS(val); 654 655 if (AFUD_AFU_DIRECTED(val)) 656 afu->modes_supported |= CXL_MODE_DIRECTED; 657 if (AFUD_DEDICATED_PROCESS(val)) 658 afu->modes_supported |= CXL_MODE_DEDICATED; 659 if (AFUD_TIME_SLICED(val)) 660 afu->modes_supported |= CXL_MODE_TIME_SLICED; 661 662 val = AFUD_READ_PPPSA(afu); 663 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096; 664 afu->psa = AFUD_PPPSA_PSA(val); 665 if ((afu->pp_psa = AFUD_PPPSA_PP(val))) 666 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu); 667 668 val = AFUD_READ_CR(afu); 669 afu->crs_len = AFUD_CR_LEN(val) * 256; 670 afu->crs_offset = AFUD_READ_CR_OFF(afu); 671 672 673 /* eb_len is in multiple of 4K */ 674 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096; 675 afu->eb_offset = AFUD_READ_EB_OFF(afu); 676 677 /* eb_off is 4K aligned so lower 12 bits are always zero */ 678 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) { 679 dev_warn(&afu->dev, 680 "Invalid AFU error buffer offset %Lx\n", 681 afu->eb_offset); 682 dev_info(&afu->dev, 683 "Ignoring AFU error buffer in the descriptor\n"); 684 /* indicate that no afu buffer exists */ 685 afu->eb_len = 0; 686 } 687 688 return 0; 689 } 690 691 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu) 692 { 693 int i, rc; 694 u32 val; 695 696 if (afu->psa && afu->adapter->ps_size < 697 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { 698 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n"); 699 return -ENODEV; 700 } 701 702 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE)) 703 dev_warn(&afu->dev, "AFU uses < PAGE_SIZE per-process PSA!"); 704 705 for (i = 0; i < afu->crs_num; i++) { 706 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val); 707 if (rc || val == 0) { 708 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i); 709 return -EINVAL; 710 } 711 } 712 713 return 0; 714 } 715 716 static int sanitise_afu_regs(struct cxl_afu *afu) 717 { 718 u64 reg; 719 720 /* 721 * Clear out any regs that contain either an IVTE or address or may be 722 * waiting on an acknowledgement to try to be a bit safer as we bring 723 * it online 724 */ 725 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An); 726 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { 727 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg); 728 if (cxl_ops->afu_reset(afu)) 729 return -EIO; 730 if (cxl_afu_disable(afu)) 731 return -EIO; 732 if (cxl_psl_purge(afu)) 733 return -EIO; 734 } 735 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000); 736 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000); 737 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000); 738 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000); 739 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000); 740 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000); 741 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000); 742 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000); 743 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000); 744 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000); 745 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000); 746 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An); 747 if (reg) { 748 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg); 749 if (reg & CXL_PSL_DSISR_TRANS) 750 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); 751 else 752 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); 753 } 754 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An); 755 if (reg) { 756 if (reg & ~0xffff) 757 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg); 758 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff); 759 } 760 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); 761 if (reg) { 762 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg); 763 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg); 764 } 765 766 return 0; 767 } 768 769 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE 770 /* 771 * afu_eb_read: 772 * Called from sysfs and reads the afu error info buffer. The h/w only supports 773 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte 774 * aligned the function uses a bounce buffer which can be max PAGE_SIZE. 775 */ 776 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf, 777 loff_t off, size_t count) 778 { 779 loff_t aligned_start, aligned_end; 780 size_t aligned_length; 781 void *tbuf; 782 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset; 783 784 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len) 785 return 0; 786 787 /* calculate aligned read window */ 788 count = min((size_t)(afu->eb_len - off), count); 789 aligned_start = round_down(off, 8); 790 aligned_end = round_up(off + count, 8); 791 aligned_length = aligned_end - aligned_start; 792 793 /* max we can copy in one read is PAGE_SIZE */ 794 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) { 795 aligned_length = ERR_BUFF_MAX_COPY_SIZE; 796 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7); 797 } 798 799 /* use bounce buffer for copy */ 800 tbuf = (void *)__get_free_page(GFP_TEMPORARY); 801 if (!tbuf) 802 return -ENOMEM; 803 804 /* perform aligned read from the mmio region */ 805 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length); 806 memcpy(buf, tbuf + (off & 0x7), count); 807 808 free_page((unsigned long)tbuf); 809 810 return count; 811 } 812 813 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev) 814 { 815 int rc; 816 817 if ((rc = pci_map_slice_regs(afu, adapter, dev))) 818 return rc; 819 820 if ((rc = sanitise_afu_regs(afu))) 821 goto err1; 822 823 /* We need to reset the AFU before we can read the AFU descriptor */ 824 if ((rc = cxl_ops->afu_reset(afu))) 825 goto err1; 826 827 if (cxl_verbose) 828 dump_afu_descriptor(afu); 829 830 if ((rc = cxl_read_afu_descriptor(afu))) 831 goto err1; 832 833 if ((rc = cxl_afu_descriptor_looks_ok(afu))) 834 goto err1; 835 836 if ((rc = init_implementation_afu_regs(afu))) 837 goto err1; 838 839 if ((rc = cxl_native_register_serr_irq(afu))) 840 goto err1; 841 842 if ((rc = cxl_native_register_psl_irq(afu))) 843 goto err2; 844 845 return 0; 846 847 err2: 848 cxl_native_release_serr_irq(afu); 849 err1: 850 pci_unmap_slice_regs(afu); 851 return rc; 852 } 853 854 static void pci_deconfigure_afu(struct cxl_afu *afu) 855 { 856 cxl_native_release_psl_irq(afu); 857 cxl_native_release_serr_irq(afu); 858 pci_unmap_slice_regs(afu); 859 } 860 861 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) 862 { 863 struct cxl_afu *afu; 864 int rc = -ENOMEM; 865 866 afu = cxl_alloc_afu(adapter, slice); 867 if (!afu) 868 return -ENOMEM; 869 870 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL); 871 if (!afu->native) 872 goto err_free_afu; 873 874 mutex_init(&afu->native->spa_mutex); 875 876 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice); 877 if (rc) 878 goto err_free_native; 879 880 rc = pci_configure_afu(afu, adapter, dev); 881 if (rc) 882 goto err_free_native; 883 884 /* Don't care if this fails */ 885 cxl_debugfs_afu_add(afu); 886 887 /* 888 * After we call this function we must not free the afu directly, even 889 * if it returns an error! 890 */ 891 if ((rc = cxl_register_afu(afu))) 892 goto err_put1; 893 894 if ((rc = cxl_sysfs_afu_add(afu))) 895 goto err_put1; 896 897 adapter->afu[afu->slice] = afu; 898 899 if ((rc = cxl_pci_vphb_add(afu))) 900 dev_info(&afu->dev, "Can't register vPHB\n"); 901 902 return 0; 903 904 err_put1: 905 pci_deconfigure_afu(afu); 906 cxl_debugfs_afu_remove(afu); 907 device_unregister(&afu->dev); 908 return rc; 909 910 err_free_native: 911 kfree(afu->native); 912 err_free_afu: 913 kfree(afu); 914 return rc; 915 916 } 917 918 static void cxl_pci_remove_afu(struct cxl_afu *afu) 919 { 920 pr_devel("%s\n", __func__); 921 922 if (!afu) 923 return; 924 925 cxl_pci_vphb_remove(afu); 926 cxl_sysfs_afu_remove(afu); 927 cxl_debugfs_afu_remove(afu); 928 929 spin_lock(&afu->adapter->afu_list_lock); 930 afu->adapter->afu[afu->slice] = NULL; 931 spin_unlock(&afu->adapter->afu_list_lock); 932 933 cxl_context_detach_all(afu); 934 cxl_ops->afu_deactivate_mode(afu, afu->current_mode); 935 936 pci_deconfigure_afu(afu); 937 device_unregister(&afu->dev); 938 } 939 940 int cxl_pci_reset(struct cxl *adapter) 941 { 942 struct pci_dev *dev = to_pci_dev(adapter->dev.parent); 943 int rc; 944 945 if (adapter->perst_same_image) { 946 dev_warn(&dev->dev, 947 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n"); 948 return -EINVAL; 949 } 950 951 dev_info(&dev->dev, "CXL reset\n"); 952 953 /* pcie_warm_reset requests a fundamental pci reset which includes a 954 * PERST assert/deassert. PERST triggers a loading of the image 955 * if "user" or "factory" is selected in sysfs */ 956 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) { 957 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n"); 958 return rc; 959 } 960 961 return rc; 962 } 963 964 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev) 965 { 966 if (pci_request_region(dev, 2, "priv 2 regs")) 967 goto err1; 968 if (pci_request_region(dev, 0, "priv 1 regs")) 969 goto err2; 970 971 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx", 972 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev)); 973 974 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev)))) 975 goto err3; 976 977 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev)))) 978 goto err4; 979 980 return 0; 981 982 err4: 983 iounmap(adapter->native->p1_mmio); 984 adapter->native->p1_mmio = NULL; 985 err3: 986 pci_release_region(dev, 0); 987 err2: 988 pci_release_region(dev, 2); 989 err1: 990 return -ENOMEM; 991 } 992 993 static void cxl_unmap_adapter_regs(struct cxl *adapter) 994 { 995 if (adapter->native->p1_mmio) { 996 iounmap(adapter->native->p1_mmio); 997 adapter->native->p1_mmio = NULL; 998 pci_release_region(to_pci_dev(adapter->dev.parent), 2); 999 } 1000 if (adapter->native->p2_mmio) { 1001 iounmap(adapter->native->p2_mmio); 1002 adapter->native->p2_mmio = NULL; 1003 pci_release_region(to_pci_dev(adapter->dev.parent), 0); 1004 } 1005 } 1006 1007 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev) 1008 { 1009 int vsec; 1010 u32 afu_desc_off, afu_desc_size; 1011 u32 ps_off, ps_size; 1012 u16 vseclen; 1013 u8 image_state; 1014 1015 if (!(vsec = find_cxl_vsec(dev))) { 1016 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n"); 1017 return -ENODEV; 1018 } 1019 1020 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen); 1021 if (vseclen < CXL_VSEC_MIN_SIZE) { 1022 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n"); 1023 return -EINVAL; 1024 } 1025 1026 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status); 1027 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev); 1028 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major); 1029 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor); 1030 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image); 1031 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state); 1032 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); 1033 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED); 1034 1035 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); 1036 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off); 1037 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size); 1038 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off); 1039 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size); 1040 1041 /* Convert everything to bytes, because there is NO WAY I'd look at the 1042 * code a month later and forget what units these are in ;-) */ 1043 adapter->native->ps_off = ps_off * 64 * 1024; 1044 adapter->ps_size = ps_size * 64 * 1024; 1045 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024; 1046 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024; 1047 1048 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */ 1049 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; 1050 1051 return 0; 1052 } 1053 1054 /* 1055 * Workaround a PCIe Host Bridge defect on some cards, that can cause 1056 * malformed Transaction Layer Packet (TLP) errors to be erroneously 1057 * reported. Mask this error in the Uncorrectable Error Mask Register. 1058 * 1059 * The upper nibble of the PSL revision is used to distinguish between 1060 * different cards. The affected ones have it set to 0. 1061 */ 1062 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev) 1063 { 1064 int aer; 1065 u32 data; 1066 1067 if (adapter->psl_rev & 0xf000) 1068 return; 1069 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))) 1070 return; 1071 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data); 1072 if (data & PCI_ERR_UNC_MALF_TLP) 1073 if (data & PCI_ERR_UNC_INTN) 1074 return; 1075 data |= PCI_ERR_UNC_MALF_TLP; 1076 data |= PCI_ERR_UNC_INTN; 1077 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data); 1078 } 1079 1080 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev) 1081 { 1082 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT) 1083 return -EBUSY; 1084 1085 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) { 1086 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n"); 1087 return -EINVAL; 1088 } 1089 1090 if (!adapter->slices) { 1091 /* Once we support dynamic reprogramming we can use the card if 1092 * it supports loadable AFUs */ 1093 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n"); 1094 return -EINVAL; 1095 } 1096 1097 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) { 1098 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n"); 1099 return -EINVAL; 1100 } 1101 1102 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) { 1103 dev_err(&dev->dev, "ABORTING: Problem state size larger than " 1104 "available in BAR2: 0x%llx > 0x%llx\n", 1105 adapter->ps_size, p2_size(dev) - adapter->native->ps_off); 1106 return -EINVAL; 1107 } 1108 1109 return 0; 1110 } 1111 1112 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len) 1113 { 1114 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf); 1115 } 1116 1117 static void cxl_release_adapter(struct device *dev) 1118 { 1119 struct cxl *adapter = to_cxl_adapter(dev); 1120 1121 pr_devel("cxl_release_adapter\n"); 1122 1123 cxl_remove_adapter_nr(adapter); 1124 1125 kfree(adapter->native); 1126 kfree(adapter); 1127 } 1128 1129 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31)) 1130 1131 static int sanitise_adapter_regs(struct cxl *adapter) 1132 { 1133 /* Clear PSL tberror bit by writing 1 to it */ 1134 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror); 1135 return cxl_tlb_slb_invalidate(adapter); 1136 } 1137 1138 /* This should contain *only* operations that can safely be done in 1139 * both creation and recovery. 1140 */ 1141 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev) 1142 { 1143 int rc; 1144 1145 adapter->dev.parent = &dev->dev; 1146 adapter->dev.release = cxl_release_adapter; 1147 pci_set_drvdata(dev, adapter); 1148 1149 rc = pci_enable_device(dev); 1150 if (rc) { 1151 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc); 1152 return rc; 1153 } 1154 1155 if ((rc = cxl_read_vsec(adapter, dev))) 1156 return rc; 1157 1158 if ((rc = cxl_vsec_looks_ok(adapter, dev))) 1159 return rc; 1160 1161 cxl_fixup_malformed_tlp(adapter, dev); 1162 1163 if ((rc = setup_cxl_bars(dev))) 1164 return rc; 1165 1166 if ((rc = switch_card_to_cxl(dev))) 1167 return rc; 1168 1169 if ((rc = cxl_update_image_control(adapter))) 1170 return rc; 1171 1172 if ((rc = cxl_map_adapter_regs(adapter, dev))) 1173 return rc; 1174 1175 if ((rc = sanitise_adapter_regs(adapter))) 1176 goto err; 1177 1178 if ((rc = init_implementation_adapter_regs(adapter, dev))) 1179 goto err; 1180 1181 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_CAPI))) 1182 goto err; 1183 1184 /* If recovery happened, the last step is to turn on snooping. 1185 * In the non-recovery case this has no effect */ 1186 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON))) 1187 goto err; 1188 1189 /* Ignore error, adapter init is not dependant on timebase sync */ 1190 cxl_setup_psl_timebase(adapter, dev); 1191 1192 if ((rc = cxl_native_register_psl_err_irq(adapter))) 1193 goto err; 1194 1195 return 0; 1196 1197 err: 1198 cxl_unmap_adapter_regs(adapter); 1199 return rc; 1200 1201 } 1202 1203 static void cxl_deconfigure_adapter(struct cxl *adapter) 1204 { 1205 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent); 1206 1207 cxl_native_release_psl_err_irq(adapter); 1208 cxl_unmap_adapter_regs(adapter); 1209 1210 pci_disable_device(pdev); 1211 } 1212 1213 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev) 1214 { 1215 struct cxl *adapter; 1216 int rc; 1217 1218 adapter = cxl_alloc_adapter(); 1219 if (!adapter) 1220 return ERR_PTR(-ENOMEM); 1221 1222 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL); 1223 if (!adapter->native) { 1224 rc = -ENOMEM; 1225 goto err_release; 1226 } 1227 1228 /* Set defaults for parameters which need to persist over 1229 * configure/reconfigure 1230 */ 1231 adapter->perst_loads_image = true; 1232 adapter->perst_same_image = false; 1233 1234 rc = cxl_configure_adapter(adapter, dev); 1235 if (rc) { 1236 pci_disable_device(dev); 1237 goto err_release; 1238 } 1239 1240 /* Don't care if this one fails: */ 1241 cxl_debugfs_adapter_add(adapter); 1242 1243 /* 1244 * After we call this function we must not free the adapter directly, 1245 * even if it returns an error! 1246 */ 1247 if ((rc = cxl_register_adapter(adapter))) 1248 goto err_put1; 1249 1250 if ((rc = cxl_sysfs_adapter_add(adapter))) 1251 goto err_put1; 1252 1253 return adapter; 1254 1255 err_put1: 1256 /* This should mirror cxl_remove_adapter, except without the 1257 * sysfs parts 1258 */ 1259 cxl_debugfs_adapter_remove(adapter); 1260 cxl_deconfigure_adapter(adapter); 1261 device_unregister(&adapter->dev); 1262 return ERR_PTR(rc); 1263 1264 err_release: 1265 cxl_release_adapter(&adapter->dev); 1266 return ERR_PTR(rc); 1267 } 1268 1269 static void cxl_pci_remove_adapter(struct cxl *adapter) 1270 { 1271 pr_devel("cxl_remove_adapter\n"); 1272 1273 cxl_sysfs_adapter_remove(adapter); 1274 cxl_debugfs_adapter_remove(adapter); 1275 1276 cxl_deconfigure_adapter(adapter); 1277 1278 device_unregister(&adapter->dev); 1279 } 1280 1281 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) 1282 { 1283 struct cxl *adapter; 1284 int slice; 1285 int rc; 1286 1287 if (cxl_pci_is_vphb_device(dev)) { 1288 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n"); 1289 return -ENODEV; 1290 } 1291 1292 if (cxl_verbose) 1293 dump_cxl_config_space(dev); 1294 1295 adapter = cxl_pci_init_adapter(dev); 1296 if (IS_ERR(adapter)) { 1297 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter)); 1298 return PTR_ERR(adapter); 1299 } 1300 1301 for (slice = 0; slice < adapter->slices; slice++) { 1302 if ((rc = pci_init_afu(adapter, slice, dev))) { 1303 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc); 1304 continue; 1305 } 1306 1307 rc = cxl_afu_select_best_mode(adapter->afu[slice]); 1308 if (rc) 1309 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc); 1310 } 1311 1312 return 0; 1313 } 1314 1315 static void cxl_remove(struct pci_dev *dev) 1316 { 1317 struct cxl *adapter = pci_get_drvdata(dev); 1318 struct cxl_afu *afu; 1319 int i; 1320 1321 /* 1322 * Lock to prevent someone grabbing a ref through the adapter list as 1323 * we are removing it 1324 */ 1325 for (i = 0; i < adapter->slices; i++) { 1326 afu = adapter->afu[i]; 1327 cxl_pci_remove_afu(afu); 1328 } 1329 cxl_pci_remove_adapter(adapter); 1330 } 1331 1332 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu, 1333 pci_channel_state_t state) 1334 { 1335 struct pci_dev *afu_dev; 1336 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET; 1337 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET; 1338 1339 /* There should only be one entry, but go through the list 1340 * anyway 1341 */ 1342 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 1343 if (!afu_dev->driver) 1344 continue; 1345 1346 afu_dev->error_state = state; 1347 1348 if (afu_dev->driver->err_handler) 1349 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev, 1350 state); 1351 /* Disconnect trumps all, NONE trumps NEED_RESET */ 1352 if (afu_result == PCI_ERS_RESULT_DISCONNECT) 1353 result = PCI_ERS_RESULT_DISCONNECT; 1354 else if ((afu_result == PCI_ERS_RESULT_NONE) && 1355 (result == PCI_ERS_RESULT_NEED_RESET)) 1356 result = PCI_ERS_RESULT_NONE; 1357 } 1358 return result; 1359 } 1360 1361 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, 1362 pci_channel_state_t state) 1363 { 1364 struct cxl *adapter = pci_get_drvdata(pdev); 1365 struct cxl_afu *afu; 1366 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET; 1367 int i; 1368 1369 /* At this point, we could still have an interrupt pending. 1370 * Let's try to get them out of the way before they do 1371 * anything we don't like. 1372 */ 1373 schedule(); 1374 1375 /* If we're permanently dead, give up. */ 1376 if (state == pci_channel_io_perm_failure) { 1377 /* Tell the AFU drivers; but we don't care what they 1378 * say, we're going away. 1379 */ 1380 for (i = 0; i < adapter->slices; i++) { 1381 afu = adapter->afu[i]; 1382 cxl_vphb_error_detected(afu, state); 1383 } 1384 return PCI_ERS_RESULT_DISCONNECT; 1385 } 1386 1387 /* Are we reflashing? 1388 * 1389 * If we reflash, we could come back as something entirely 1390 * different, including a non-CAPI card. As such, by default 1391 * we don't participate in the process. We'll be unbound and 1392 * the slot re-probed. (TODO: check EEH doesn't blindly rebind 1393 * us!) 1394 * 1395 * However, this isn't the entire story: for reliablity 1396 * reasons, we usually want to reflash the FPGA on PERST in 1397 * order to get back to a more reliable known-good state. 1398 * 1399 * This causes us a bit of a problem: if we reflash we can't 1400 * trust that we'll come back the same - we could have a new 1401 * image and been PERSTed in order to load that 1402 * image. However, most of the time we actually *will* come 1403 * back the same - for example a regular EEH event. 1404 * 1405 * Therefore, we allow the user to assert that the image is 1406 * indeed the same and that we should continue on into EEH 1407 * anyway. 1408 */ 1409 if (adapter->perst_loads_image && !adapter->perst_same_image) { 1410 /* TODO take the PHB out of CXL mode */ 1411 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n"); 1412 return PCI_ERS_RESULT_NONE; 1413 } 1414 1415 /* 1416 * At this point, we want to try to recover. We'll always 1417 * need a complete slot reset: we don't trust any other reset. 1418 * 1419 * Now, we go through each AFU: 1420 * - We send the driver, if bound, an error_detected callback. 1421 * We expect it to clean up, but it can also tell us to give 1422 * up and permanently detach the card. To simplify things, if 1423 * any bound AFU driver doesn't support EEH, we give up on EEH. 1424 * 1425 * - We detach all contexts associated with the AFU. This 1426 * does not free them, but puts them into a CLOSED state 1427 * which causes any the associated files to return useful 1428 * errors to userland. It also unmaps, but does not free, 1429 * any IRQs. 1430 * 1431 * - We clean up our side: releasing and unmapping resources we hold 1432 * so we can wire them up again when the hardware comes back up. 1433 * 1434 * Driver authors should note: 1435 * 1436 * - Any contexts you create in your kernel driver (except 1437 * those associated with anonymous file descriptors) are 1438 * your responsibility to free and recreate. Likewise with 1439 * any attached resources. 1440 * 1441 * - We will take responsibility for re-initialising the 1442 * device context (the one set up for you in 1443 * cxl_pci_enable_device_hook and accessed through 1444 * cxl_get_context). If you've attached IRQs or other 1445 * resources to it, they remains yours to free. 1446 * 1447 * You can call the same functions to release resources as you 1448 * normally would: we make sure that these functions continue 1449 * to work when the hardware is down. 1450 * 1451 * Two examples: 1452 * 1453 * 1) If you normally free all your resources at the end of 1454 * each request, or if you use anonymous FDs, your 1455 * error_detected callback can simply set a flag to tell 1456 * your driver not to start any new calls. You can then 1457 * clear the flag in the resume callback. 1458 * 1459 * 2) If you normally allocate your resources on startup: 1460 * * Set a flag in error_detected as above. 1461 * * Let CXL detach your contexts. 1462 * * In slot_reset, free the old resources and allocate new ones. 1463 * * In resume, clear the flag to allow things to start. 1464 */ 1465 for (i = 0; i < adapter->slices; i++) { 1466 afu = adapter->afu[i]; 1467 1468 result = cxl_vphb_error_detected(afu, state); 1469 1470 /* Only continue if everyone agrees on NEED_RESET */ 1471 if (result != PCI_ERS_RESULT_NEED_RESET) 1472 return result; 1473 1474 cxl_context_detach_all(afu); 1475 cxl_ops->afu_deactivate_mode(afu, afu->current_mode); 1476 pci_deconfigure_afu(afu); 1477 } 1478 cxl_deconfigure_adapter(adapter); 1479 1480 return result; 1481 } 1482 1483 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev) 1484 { 1485 struct cxl *adapter = pci_get_drvdata(pdev); 1486 struct cxl_afu *afu; 1487 struct cxl_context *ctx; 1488 struct pci_dev *afu_dev; 1489 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED; 1490 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED; 1491 int i; 1492 1493 if (cxl_configure_adapter(adapter, pdev)) 1494 goto err; 1495 1496 for (i = 0; i < adapter->slices; i++) { 1497 afu = adapter->afu[i]; 1498 1499 if (pci_configure_afu(afu, adapter, pdev)) 1500 goto err; 1501 1502 if (cxl_afu_select_best_mode(afu)) 1503 goto err; 1504 1505 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 1506 /* Reset the device context. 1507 * TODO: make this less disruptive 1508 */ 1509 ctx = cxl_get_context(afu_dev); 1510 1511 if (ctx && cxl_release_context(ctx)) 1512 goto err; 1513 1514 ctx = cxl_dev_context_init(afu_dev); 1515 if (!ctx) 1516 goto err; 1517 1518 afu_dev->dev.archdata.cxl_ctx = ctx; 1519 1520 if (cxl_ops->afu_check_and_enable(afu)) 1521 goto err; 1522 1523 afu_dev->error_state = pci_channel_io_normal; 1524 1525 /* If there's a driver attached, allow it to 1526 * chime in on recovery. Drivers should check 1527 * if everything has come back OK, but 1528 * shouldn't start new work until we call 1529 * their resume function. 1530 */ 1531 if (!afu_dev->driver) 1532 continue; 1533 1534 if (afu_dev->driver->err_handler && 1535 afu_dev->driver->err_handler->slot_reset) 1536 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev); 1537 1538 if (afu_result == PCI_ERS_RESULT_DISCONNECT) 1539 result = PCI_ERS_RESULT_DISCONNECT; 1540 } 1541 } 1542 return result; 1543 1544 err: 1545 /* All the bits that happen in both error_detected and cxl_remove 1546 * should be idempotent, so we don't need to worry about leaving a mix 1547 * of unconfigured and reconfigured resources. 1548 */ 1549 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n"); 1550 return PCI_ERS_RESULT_DISCONNECT; 1551 } 1552 1553 static void cxl_pci_resume(struct pci_dev *pdev) 1554 { 1555 struct cxl *adapter = pci_get_drvdata(pdev); 1556 struct cxl_afu *afu; 1557 struct pci_dev *afu_dev; 1558 int i; 1559 1560 /* Everything is back now. Drivers should restart work now. 1561 * This is not the place to be checking if everything came back up 1562 * properly, because there's no return value: do that in slot_reset. 1563 */ 1564 for (i = 0; i < adapter->slices; i++) { 1565 afu = adapter->afu[i]; 1566 1567 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) { 1568 if (afu_dev->driver && afu_dev->driver->err_handler && 1569 afu_dev->driver->err_handler->resume) 1570 afu_dev->driver->err_handler->resume(afu_dev); 1571 } 1572 } 1573 } 1574 1575 static const struct pci_error_handlers cxl_err_handler = { 1576 .error_detected = cxl_pci_error_detected, 1577 .slot_reset = cxl_pci_slot_reset, 1578 .resume = cxl_pci_resume, 1579 }; 1580 1581 struct pci_driver cxl_pci_driver = { 1582 .name = "cxl-pci", 1583 .id_table = cxl_pci_tbl, 1584 .probe = cxl_probe, 1585 .remove = cxl_remove, 1586 .shutdown = cxl_remove, 1587 .err_handler = &cxl_err_handler, 1588 }; 1589