sor.c (a02001086bbfb4da35d1228bebc2f1b442db455f) sor.c (62b9e06321a254c3039966cff831487498e831a5)
1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

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262 unsigned long value, timeout;
263
264 /* enable display controller outputs */
265 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
266 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
267 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
268 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
269
1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

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262 unsigned long value, timeout;
263
264 /* enable display controller outputs */
265 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
266 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
267 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
268 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
269
270 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
271 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
270 tegra_dc_commit(dc);
272
273 timeout = jiffies + msecs_to_jiffies(250);
274
275 /* wait for head to wake up */
276 while (time_before(jiffies, timeout)) {
277 value = tegra_sor_readl(sor, SOR_TEST);
278 value &= SOR_TEST_HEAD_MODE_MASK;
279

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1075 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1076 value &= ~DISP_CTRL_MODE_MASK;
1077 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1078
1079 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1080 value &= ~SOR_ENABLE;
1081 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1082
271
272 timeout = jiffies + msecs_to_jiffies(250);
273
274 /* wait for head to wake up */
275 while (time_before(jiffies, timeout)) {
276 value = tegra_sor_readl(sor, SOR_TEST);
277 value &= SOR_TEST_HEAD_MODE_MASK;
278

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1074 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1075 value &= ~DISP_CTRL_MODE_MASK;
1076 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1077
1078 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1079 value &= ~SOR_ENABLE;
1080 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1081
1083 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1084 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1082 tegra_dc_commit(dc);
1085 }
1086
1087 err = tegra_sor_power_down(sor);
1088 if (err < 0) {
1089 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1090 goto unlock;
1091 }
1092

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1084
1085 err = tegra_sor_power_down(sor);
1086 if (err < 0) {
1087 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1088 goto unlock;
1089 }
1090

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