1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/debugfs.h> 11 #include <linux/io.h> 12 #include <linux/platform_device.h> 13 #include <linux/reset.h> 14 15 #include <soc/tegra/pmc.h> 16 17 #include <drm/drm_dp_helper.h> 18 19 #include "dc.h" 20 #include "drm.h" 21 #include "sor.h" 22 23 struct tegra_sor { 24 struct host1x_client client; 25 struct tegra_output output; 26 struct device *dev; 27 28 void __iomem *regs; 29 30 struct reset_control *rst; 31 struct clk *clk_parent; 32 struct clk *clk_safe; 33 struct clk *clk_dp; 34 struct clk *clk; 35 36 struct tegra_dpaux *dpaux; 37 38 struct mutex lock; 39 bool enabled; 40 41 struct dentry *debugfs; 42 }; 43 44 struct tegra_sor_config { 45 u32 bits_per_pixel; 46 47 u32 active_polarity; 48 u32 active_count; 49 u32 tu_size; 50 u32 active_frac; 51 u32 watermark; 52 53 u32 hblank_symbols; 54 u32 vblank_symbols; 55 }; 56 57 static inline struct tegra_sor * 58 host1x_client_to_sor(struct host1x_client *client) 59 { 60 return container_of(client, struct tegra_sor, client); 61 } 62 63 static inline struct tegra_sor *to_sor(struct tegra_output *output) 64 { 65 return container_of(output, struct tegra_sor, output); 66 } 67 68 static inline unsigned long tegra_sor_readl(struct tegra_sor *sor, 69 unsigned long offset) 70 { 71 return readl(sor->regs + (offset << 2)); 72 } 73 74 static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value, 75 unsigned long offset) 76 { 77 writel(value, sor->regs + (offset << 2)); 78 } 79 80 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, 81 struct drm_dp_link *link) 82 { 83 unsigned long value; 84 unsigned int i; 85 u8 pattern; 86 int err; 87 88 /* setup lane parameters */ 89 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | 90 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | 91 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | 92 SOR_LANE_DRIVE_CURRENT_LANE0(0x40); 93 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0); 94 95 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | 96 SOR_LANE_PREEMPHASIS_LANE2(0x0f) | 97 SOR_LANE_PREEMPHASIS_LANE1(0x0f) | 98 SOR_LANE_PREEMPHASIS_LANE0(0x0f); 99 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0); 100 101 value = SOR_LANE_POST_CURSOR_LANE3(0x00) | 102 SOR_LANE_POST_CURSOR_LANE2(0x00) | 103 SOR_LANE_POST_CURSOR_LANE1(0x00) | 104 SOR_LANE_POST_CURSOR_LANE0(0x00); 105 tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0); 106 107 /* disable LVDS mode */ 108 tegra_sor_writel(sor, 0, SOR_LVDS); 109 110 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 111 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 112 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 113 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ 114 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 115 116 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 117 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 118 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; 119 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 120 121 usleep_range(10, 100); 122 123 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 124 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 125 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 126 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 127 128 err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B); 129 if (err < 0) 130 return err; 131 132 for (i = 0, value = 0; i < link->num_lanes; i++) { 133 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 134 SOR_DP_TPG_SCRAMBLER_NONE | 135 SOR_DP_TPG_PATTERN_TRAIN1; 136 value = (value << 8) | lane; 137 } 138 139 tegra_sor_writel(sor, value, SOR_DP_TPG); 140 141 pattern = DP_TRAINING_PATTERN_1; 142 143 err = tegra_dpaux_train(sor->dpaux, link, pattern); 144 if (err < 0) 145 return err; 146 147 value = tegra_sor_readl(sor, SOR_DP_SPARE_0); 148 value |= SOR_DP_SPARE_SEQ_ENABLE; 149 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 150 value |= SOR_DP_SPARE_MACRO_SOR_CLK; 151 tegra_sor_writel(sor, value, SOR_DP_SPARE_0); 152 153 for (i = 0, value = 0; i < link->num_lanes; i++) { 154 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 155 SOR_DP_TPG_SCRAMBLER_NONE | 156 SOR_DP_TPG_PATTERN_TRAIN2; 157 value = (value << 8) | lane; 158 } 159 160 tegra_sor_writel(sor, value, SOR_DP_TPG); 161 162 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; 163 164 err = tegra_dpaux_train(sor->dpaux, link, pattern); 165 if (err < 0) 166 return err; 167 168 for (i = 0, value = 0; i < link->num_lanes; i++) { 169 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 170 SOR_DP_TPG_SCRAMBLER_GALIOS | 171 SOR_DP_TPG_PATTERN_NONE; 172 value = (value << 8) | lane; 173 } 174 175 tegra_sor_writel(sor, value, SOR_DP_TPG); 176 177 pattern = DP_TRAINING_PATTERN_DISABLE; 178 179 err = tegra_dpaux_train(sor->dpaux, link, pattern); 180 if (err < 0) 181 return err; 182 183 return 0; 184 } 185 186 static void tegra_sor_super_update(struct tegra_sor *sor) 187 { 188 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); 189 tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0); 190 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); 191 } 192 193 static void tegra_sor_update(struct tegra_sor *sor) 194 { 195 tegra_sor_writel(sor, 0, SOR_STATE_0); 196 tegra_sor_writel(sor, 1, SOR_STATE_0); 197 tegra_sor_writel(sor, 0, SOR_STATE_0); 198 } 199 200 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 201 { 202 unsigned long value; 203 204 value = tegra_sor_readl(sor, SOR_PWM_DIV); 205 value &= ~SOR_PWM_DIV_MASK; 206 value |= 0x400; /* period */ 207 tegra_sor_writel(sor, value, SOR_PWM_DIV); 208 209 value = tegra_sor_readl(sor, SOR_PWM_CTL); 210 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 211 value |= 0x400; /* duty cycle */ 212 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 213 value |= SOR_PWM_CTL_TRIGGER; 214 tegra_sor_writel(sor, value, SOR_PWM_CTL); 215 216 timeout = jiffies + msecs_to_jiffies(timeout); 217 218 while (time_before(jiffies, timeout)) { 219 value = tegra_sor_readl(sor, SOR_PWM_CTL); 220 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 221 return 0; 222 223 usleep_range(25, 100); 224 } 225 226 return -ETIMEDOUT; 227 } 228 229 static int tegra_sor_attach(struct tegra_sor *sor) 230 { 231 unsigned long value, timeout; 232 233 /* wake up in normal mode */ 234 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 235 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 236 value |= SOR_SUPER_STATE_MODE_NORMAL; 237 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 238 tegra_sor_super_update(sor); 239 240 /* attach */ 241 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 242 value |= SOR_SUPER_STATE_ATTACHED; 243 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 244 tegra_sor_super_update(sor); 245 246 timeout = jiffies + msecs_to_jiffies(250); 247 248 while (time_before(jiffies, timeout)) { 249 value = tegra_sor_readl(sor, SOR_TEST); 250 if ((value & SOR_TEST_ATTACHED) != 0) 251 return 0; 252 253 usleep_range(25, 100); 254 } 255 256 return -ETIMEDOUT; 257 } 258 259 static int tegra_sor_wakeup(struct tegra_sor *sor) 260 { 261 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 262 unsigned long value, timeout; 263 264 /* enable display controller outputs */ 265 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 266 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 267 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 268 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 269 270 tegra_dc_commit(dc); 271 272 timeout = jiffies + msecs_to_jiffies(250); 273 274 /* wait for head to wake up */ 275 while (time_before(jiffies, timeout)) { 276 value = tegra_sor_readl(sor, SOR_TEST); 277 value &= SOR_TEST_HEAD_MODE_MASK; 278 279 if (value == SOR_TEST_HEAD_MODE_AWAKE) 280 return 0; 281 282 usleep_range(25, 100); 283 } 284 285 return -ETIMEDOUT; 286 } 287 288 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 289 { 290 unsigned long value; 291 292 value = tegra_sor_readl(sor, SOR_PWR); 293 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 294 tegra_sor_writel(sor, value, SOR_PWR); 295 296 timeout = jiffies + msecs_to_jiffies(timeout); 297 298 while (time_before(jiffies, timeout)) { 299 value = tegra_sor_readl(sor, SOR_PWR); 300 if ((value & SOR_PWR_TRIGGER) == 0) 301 return 0; 302 303 usleep_range(25, 100); 304 } 305 306 return -ETIMEDOUT; 307 } 308 309 struct tegra_sor_params { 310 /* number of link clocks per line */ 311 unsigned int num_clocks; 312 /* ratio between input and output */ 313 u64 ratio; 314 /* precision factor */ 315 u64 precision; 316 317 unsigned int active_polarity; 318 unsigned int active_count; 319 unsigned int active_frac; 320 unsigned int tu_size; 321 unsigned int error; 322 }; 323 324 static int tegra_sor_compute_params(struct tegra_sor *sor, 325 struct tegra_sor_params *params, 326 unsigned int tu_size) 327 { 328 u64 active_sym, active_count, frac, approx; 329 u32 active_polarity, active_frac = 0; 330 const u64 f = params->precision; 331 s64 error; 332 333 active_sym = params->ratio * tu_size; 334 active_count = div_u64(active_sym, f) * f; 335 frac = active_sym - active_count; 336 337 /* fraction < 0.5 */ 338 if (frac >= (f / 2)) { 339 active_polarity = 1; 340 frac = f - frac; 341 } else { 342 active_polarity = 0; 343 } 344 345 if (frac != 0) { 346 frac = div_u64(f * f, frac); /* 1/fraction */ 347 if (frac <= (15 * f)) { 348 active_frac = div_u64(frac, f); 349 350 /* round up */ 351 if (active_polarity) 352 active_frac++; 353 } else { 354 active_frac = active_polarity ? 1 : 15; 355 } 356 } 357 358 if (active_frac == 1) 359 active_polarity = 0; 360 361 if (active_polarity == 1) { 362 if (active_frac) { 363 approx = active_count + (active_frac * (f - 1)) * f; 364 approx = div_u64(approx, active_frac * f); 365 } else { 366 approx = active_count + f; 367 } 368 } else { 369 if (active_frac) 370 approx = active_count + div_u64(f, active_frac); 371 else 372 approx = active_count; 373 } 374 375 error = div_s64(active_sym - approx, tu_size); 376 error *= params->num_clocks; 377 378 if (error <= 0 && abs64(error) < params->error) { 379 params->active_count = div_u64(active_count, f); 380 params->active_polarity = active_polarity; 381 params->active_frac = active_frac; 382 params->error = abs64(error); 383 params->tu_size = tu_size; 384 385 if (error == 0) 386 return true; 387 } 388 389 return false; 390 } 391 392 static int tegra_sor_calc_config(struct tegra_sor *sor, 393 struct drm_display_mode *mode, 394 struct tegra_sor_config *config, 395 struct drm_dp_link *link) 396 { 397 const u64 f = 100000, link_rate = link->rate * 1000; 398 const u64 pclk = mode->clock * 1000; 399 u64 input, output, watermark, num; 400 struct tegra_sor_params params; 401 u32 num_syms_per_line; 402 unsigned int i; 403 404 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) 405 return -EINVAL; 406 407 output = link_rate * 8 * link->num_lanes; 408 input = pclk * config->bits_per_pixel; 409 410 if (input >= output) 411 return -ERANGE; 412 413 memset(¶ms, 0, sizeof(params)); 414 params.ratio = div64_u64(input * f, output); 415 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 416 params.precision = f; 417 params.error = 64 * f; 418 params.tu_size = 64; 419 420 for (i = params.tu_size; i >= 32; i--) 421 if (tegra_sor_compute_params(sor, ¶ms, i)) 422 break; 423 424 if (params.active_frac == 0) { 425 config->active_polarity = 0; 426 config->active_count = params.active_count; 427 428 if (!params.active_polarity) 429 config->active_count--; 430 431 config->tu_size = params.tu_size; 432 config->active_frac = 1; 433 } else { 434 config->active_polarity = params.active_polarity; 435 config->active_count = params.active_count; 436 config->active_frac = params.active_frac; 437 config->tu_size = params.tu_size; 438 } 439 440 dev_dbg(sor->dev, 441 "polarity: %d active count: %d tu size: %d active frac: %d\n", 442 config->active_polarity, config->active_count, 443 config->tu_size, config->active_frac); 444 445 watermark = params.ratio * config->tu_size * (f - params.ratio); 446 watermark = div_u64(watermark, f); 447 448 watermark = div_u64(watermark + params.error, f); 449 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 450 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 451 (link->num_lanes * 8); 452 453 if (config->watermark > 30) { 454 config->watermark = 30; 455 dev_err(sor->dev, 456 "unable to compute TU size, forcing watermark to %u\n", 457 config->watermark); 458 } else if (config->watermark > num_syms_per_line) { 459 config->watermark = num_syms_per_line; 460 dev_err(sor->dev, "watermark too high, forcing to %u\n", 461 config->watermark); 462 } 463 464 /* compute the number of symbols per horizontal blanking interval */ 465 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 466 config->hblank_symbols = div_u64(num, pclk); 467 468 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 469 config->hblank_symbols -= 3; 470 471 config->hblank_symbols -= 12 / link->num_lanes; 472 473 /* compute the number of symbols per vertical blanking interval */ 474 num = (mode->hdisplay - 25) * link_rate; 475 config->vblank_symbols = div_u64(num, pclk); 476 config->vblank_symbols -= 36 / link->num_lanes + 4; 477 478 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 479 config->vblank_symbols); 480 481 return 0; 482 } 483 484 static int tegra_output_sor_enable(struct tegra_output *output) 485 { 486 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 487 struct drm_display_mode *mode = &dc->base.mode; 488 unsigned int vbe, vse, hbe, hse, vbs, hbs, i; 489 struct tegra_sor *sor = to_sor(output); 490 struct tegra_sor_config config; 491 struct drm_dp_link link; 492 struct drm_dp_aux *aux; 493 unsigned long value; 494 int err = 0; 495 496 mutex_lock(&sor->lock); 497 498 if (sor->enabled) 499 goto unlock; 500 501 err = clk_prepare_enable(sor->clk); 502 if (err < 0) 503 goto unlock; 504 505 reset_control_deassert(sor->rst); 506 507 /* FIXME: properly convert to struct drm_dp_aux */ 508 aux = (struct drm_dp_aux *)sor->dpaux; 509 510 if (sor->dpaux) { 511 err = tegra_dpaux_enable(sor->dpaux); 512 if (err < 0) 513 dev_err(sor->dev, "failed to enable DP: %d\n", err); 514 515 err = drm_dp_link_probe(aux, &link); 516 if (err < 0) { 517 dev_err(sor->dev, "failed to probe eDP link: %d\n", 518 err); 519 goto unlock; 520 } 521 } 522 523 err = clk_set_parent(sor->clk, sor->clk_safe); 524 if (err < 0) 525 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 526 527 memset(&config, 0, sizeof(config)); 528 config.bits_per_pixel = output->connector.display_info.bpc * 3; 529 530 err = tegra_sor_calc_config(sor, mode, &config, &link); 531 if (err < 0) 532 dev_err(sor->dev, "failed to compute link configuration: %d\n", 533 err); 534 535 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 536 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 537 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 538 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 539 540 value = tegra_sor_readl(sor, SOR_PLL_2); 541 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; 542 tegra_sor_writel(sor, value, SOR_PLL_2); 543 usleep_range(20, 100); 544 545 value = tegra_sor_readl(sor, SOR_PLL_3); 546 value |= SOR_PLL_3_PLL_VDD_MODE_V3_3; 547 tegra_sor_writel(sor, value, SOR_PLL_3); 548 549 value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST | 550 SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT; 551 tegra_sor_writel(sor, value, SOR_PLL_0); 552 553 value = tegra_sor_readl(sor, SOR_PLL_2); 554 value |= SOR_PLL_2_SEQ_PLLCAPPD; 555 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 556 value |= SOR_PLL_2_LVDS_ENABLE; 557 tegra_sor_writel(sor, value, SOR_PLL_2); 558 559 value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM; 560 tegra_sor_writel(sor, value, SOR_PLL_1); 561 562 while (true) { 563 value = tegra_sor_readl(sor, SOR_PLL_2); 564 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0) 565 break; 566 567 usleep_range(250, 1000); 568 } 569 570 value = tegra_sor_readl(sor, SOR_PLL_2); 571 value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE; 572 value &= ~SOR_PLL_2_PORT_POWERDOWN; 573 tegra_sor_writel(sor, value, SOR_PLL_2); 574 575 /* 576 * power up 577 */ 578 579 /* set safe link bandwidth (1.62 Gbps) */ 580 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 581 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 582 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; 583 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 584 585 /* step 1 */ 586 value = tegra_sor_readl(sor, SOR_PLL_2); 587 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN | 588 SOR_PLL_2_BANDGAP_POWERDOWN; 589 tegra_sor_writel(sor, value, SOR_PLL_2); 590 591 value = tegra_sor_readl(sor, SOR_PLL_0); 592 value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF; 593 tegra_sor_writel(sor, value, SOR_PLL_0); 594 595 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 596 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 597 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 598 599 /* step 2 */ 600 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); 601 if (err < 0) { 602 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); 603 goto unlock; 604 } 605 606 usleep_range(5, 100); 607 608 /* step 3 */ 609 value = tegra_sor_readl(sor, SOR_PLL_2); 610 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; 611 tegra_sor_writel(sor, value, SOR_PLL_2); 612 613 usleep_range(20, 100); 614 615 /* step 4 */ 616 value = tegra_sor_readl(sor, SOR_PLL_0); 617 value &= ~SOR_PLL_0_POWER_OFF; 618 value &= ~SOR_PLL_0_VCOPD; 619 tegra_sor_writel(sor, value, SOR_PLL_0); 620 621 value = tegra_sor_readl(sor, SOR_PLL_2); 622 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 623 tegra_sor_writel(sor, value, SOR_PLL_2); 624 625 usleep_range(200, 1000); 626 627 /* step 5 */ 628 value = tegra_sor_readl(sor, SOR_PLL_2); 629 value &= ~SOR_PLL_2_PORT_POWERDOWN; 630 tegra_sor_writel(sor, value, SOR_PLL_2); 631 632 /* switch to DP clock */ 633 err = clk_set_parent(sor->clk, sor->clk_dp); 634 if (err < 0) 635 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); 636 637 /* power DP lanes */ 638 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 639 640 if (link.num_lanes <= 2) 641 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); 642 else 643 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; 644 645 if (link.num_lanes <= 1) 646 value &= ~SOR_DP_PADCTL_PD_TXD_1; 647 else 648 value |= SOR_DP_PADCTL_PD_TXD_1; 649 650 if (link.num_lanes == 0) 651 value &= ~SOR_DP_PADCTL_PD_TXD_0; 652 else 653 value |= SOR_DP_PADCTL_PD_TXD_0; 654 655 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 656 657 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 658 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 659 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); 660 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 661 662 /* start lane sequencer */ 663 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 664 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 665 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 666 667 while (true) { 668 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 669 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 670 break; 671 672 usleep_range(250, 1000); 673 } 674 675 /* set link bandwidth */ 676 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 677 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 678 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; 679 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 680 681 /* set linkctl */ 682 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 683 value |= SOR_DP_LINKCTL_ENABLE; 684 685 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 686 value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size); 687 688 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 689 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 690 691 for (i = 0, value = 0; i < 4; i++) { 692 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 693 SOR_DP_TPG_SCRAMBLER_GALIOS | 694 SOR_DP_TPG_PATTERN_NONE; 695 value = (value << 8) | lane; 696 } 697 698 tegra_sor_writel(sor, value, SOR_DP_TPG); 699 700 value = tegra_sor_readl(sor, SOR_DP_CONFIG_0); 701 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 702 value |= SOR_DP_CONFIG_WATERMARK(config.watermark); 703 704 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 705 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count); 706 707 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 708 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac); 709 710 if (config.active_polarity) 711 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 712 else 713 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 714 715 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 716 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 717 tegra_sor_writel(sor, value, SOR_DP_CONFIG_0); 718 719 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 720 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 721 value |= config.hblank_symbols & 0xffff; 722 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 723 724 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 725 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 726 value |= config.vblank_symbols & 0xffff; 727 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 728 729 /* enable pad calibration logic */ 730 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 731 value |= SOR_DP_PADCTL_PAD_CAL_PD; 732 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 733 734 if (sor->dpaux) { 735 u8 rate, lanes; 736 737 err = drm_dp_link_probe(aux, &link); 738 if (err < 0) { 739 dev_err(sor->dev, "failed to probe eDP link: %d\n", 740 err); 741 goto unlock; 742 } 743 744 err = drm_dp_link_power_up(aux, &link); 745 if (err < 0) { 746 dev_err(sor->dev, "failed to power up eDP link: %d\n", 747 err); 748 goto unlock; 749 } 750 751 err = drm_dp_link_configure(aux, &link); 752 if (err < 0) { 753 dev_err(sor->dev, "failed to configure eDP link: %d\n", 754 err); 755 goto unlock; 756 } 757 758 rate = drm_dp_link_rate_to_bw_code(link.rate); 759 lanes = link.num_lanes; 760 761 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 762 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 763 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 764 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 765 766 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 767 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 768 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 769 770 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 771 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 772 773 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 774 775 /* disable training pattern generator */ 776 777 for (i = 0; i < link.num_lanes; i++) { 778 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 779 SOR_DP_TPG_SCRAMBLER_GALIOS | 780 SOR_DP_TPG_PATTERN_NONE; 781 value = (value << 8) | lane; 782 } 783 784 tegra_sor_writel(sor, value, SOR_DP_TPG); 785 786 err = tegra_sor_dp_train_fast(sor, &link); 787 if (err < 0) { 788 dev_err(sor->dev, "DP fast link training failed: %d\n", 789 err); 790 goto unlock; 791 } 792 793 dev_dbg(sor->dev, "fast link training succeeded\n"); 794 } 795 796 err = tegra_sor_power_up(sor, 250); 797 if (err < 0) { 798 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 799 goto unlock; 800 } 801 802 /* start display controller in continuous mode */ 803 value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); 804 value |= WRITE_MUX; 805 tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); 806 807 tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS); 808 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND); 809 810 value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); 811 value &= ~WRITE_MUX; 812 tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); 813 814 /* 815 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete 816 * raster, associate with display controller) 817 */ 818 value = SOR_STATE_ASY_PROTOCOL_DP_A | 819 SOR_STATE_ASY_CRC_MODE_COMPLETE | 820 SOR_STATE_ASY_OWNER(dc->pipe + 1); 821 822 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 823 value &= ~SOR_STATE_ASY_HSYNCPOL; 824 825 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 826 value |= SOR_STATE_ASY_HSYNCPOL; 827 828 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 829 value &= ~SOR_STATE_ASY_VSYNCPOL; 830 831 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 832 value |= SOR_STATE_ASY_VSYNCPOL; 833 834 switch (config.bits_per_pixel) { 835 case 24: 836 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 837 break; 838 839 case 18: 840 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 841 break; 842 843 default: 844 BUG(); 845 break; 846 } 847 848 tegra_sor_writel(sor, value, SOR_STATE_1); 849 850 /* 851 * TODO: The video timing programming below doesn't seem to match the 852 * register definitions. 853 */ 854 855 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 856 tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0)); 857 858 vse = mode->vsync_end - mode->vsync_start - 1; 859 hse = mode->hsync_end - mode->hsync_start - 1; 860 861 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 862 tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0)); 863 864 vbe = vse + (mode->vsync_start - mode->vdisplay); 865 hbe = hse + (mode->hsync_start - mode->hdisplay); 866 867 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 868 tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0)); 869 870 vbs = vbe + mode->vdisplay; 871 hbs = hbe + mode->hdisplay; 872 873 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 874 tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); 875 876 /* CSTM (LVDS, link A/B, upper) */ 877 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 878 SOR_CSTM_UPPER; 879 tegra_sor_writel(sor, value, SOR_CSTM); 880 881 /* PWM setup */ 882 err = tegra_sor_setup_pwm(sor, 250); 883 if (err < 0) { 884 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 885 goto unlock; 886 } 887 888 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 889 value |= SOR_ENABLE; 890 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 891 892 tegra_sor_update(sor); 893 894 err = tegra_sor_attach(sor); 895 if (err < 0) { 896 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 897 goto unlock; 898 } 899 900 err = tegra_sor_wakeup(sor); 901 if (err < 0) { 902 dev_err(sor->dev, "failed to enable DC: %d\n", err); 903 goto unlock; 904 } 905 906 sor->enabled = true; 907 908 unlock: 909 mutex_unlock(&sor->lock); 910 return err; 911 } 912 913 static int tegra_sor_detach(struct tegra_sor *sor) 914 { 915 unsigned long value, timeout; 916 917 /* switch to safe mode */ 918 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 919 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 920 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 921 tegra_sor_super_update(sor); 922 923 timeout = jiffies + msecs_to_jiffies(250); 924 925 while (time_before(jiffies, timeout)) { 926 value = tegra_sor_readl(sor, SOR_PWR); 927 if (value & SOR_PWR_MODE_SAFE) 928 break; 929 } 930 931 if ((value & SOR_PWR_MODE_SAFE) == 0) 932 return -ETIMEDOUT; 933 934 /* go to sleep */ 935 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 936 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 937 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 938 tegra_sor_super_update(sor); 939 940 /* detach */ 941 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 942 value &= ~SOR_SUPER_STATE_ATTACHED; 943 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 944 tegra_sor_super_update(sor); 945 946 timeout = jiffies + msecs_to_jiffies(250); 947 948 while (time_before(jiffies, timeout)) { 949 value = tegra_sor_readl(sor, SOR_TEST); 950 if ((value & SOR_TEST_ATTACHED) == 0) 951 break; 952 953 usleep_range(25, 100); 954 } 955 956 if ((value & SOR_TEST_ATTACHED) != 0) 957 return -ETIMEDOUT; 958 959 return 0; 960 } 961 962 static int tegra_sor_power_down(struct tegra_sor *sor) 963 { 964 unsigned long value, timeout; 965 int err; 966 967 value = tegra_sor_readl(sor, SOR_PWR); 968 value &= ~SOR_PWR_NORMAL_STATE_PU; 969 value |= SOR_PWR_TRIGGER; 970 tegra_sor_writel(sor, value, SOR_PWR); 971 972 timeout = jiffies + msecs_to_jiffies(250); 973 974 while (time_before(jiffies, timeout)) { 975 value = tegra_sor_readl(sor, SOR_PWR); 976 if ((value & SOR_PWR_TRIGGER) == 0) 977 return 0; 978 979 usleep_range(25, 100); 980 } 981 982 if ((value & SOR_PWR_TRIGGER) != 0) 983 return -ETIMEDOUT; 984 985 err = clk_set_parent(sor->clk, sor->clk_safe); 986 if (err < 0) 987 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 988 989 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 990 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 991 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 992 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 993 994 /* stop lane sequencer */ 995 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 996 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 997 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 998 999 timeout = jiffies + msecs_to_jiffies(250); 1000 1001 while (time_before(jiffies, timeout)) { 1002 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 1003 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 1004 break; 1005 1006 usleep_range(25, 100); 1007 } 1008 1009 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 1010 return -ETIMEDOUT; 1011 1012 value = tegra_sor_readl(sor, SOR_PLL_2); 1013 value |= SOR_PLL_2_PORT_POWERDOWN; 1014 tegra_sor_writel(sor, value, SOR_PLL_2); 1015 1016 usleep_range(20, 100); 1017 1018 value = tegra_sor_readl(sor, SOR_PLL_0); 1019 value |= SOR_PLL_0_POWER_OFF; 1020 value |= SOR_PLL_0_VCOPD; 1021 tegra_sor_writel(sor, value, SOR_PLL_0); 1022 1023 value = tegra_sor_readl(sor, SOR_PLL_2); 1024 value |= SOR_PLL_2_SEQ_PLLCAPPD; 1025 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 1026 tegra_sor_writel(sor, value, SOR_PLL_2); 1027 1028 usleep_range(20, 100); 1029 1030 return 0; 1031 } 1032 1033 static int tegra_output_sor_disable(struct tegra_output *output) 1034 { 1035 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 1036 struct tegra_sor *sor = to_sor(output); 1037 unsigned long value; 1038 int err = 0; 1039 1040 mutex_lock(&sor->lock); 1041 1042 if (!sor->enabled) 1043 goto unlock; 1044 1045 err = tegra_sor_detach(sor); 1046 if (err < 0) { 1047 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1048 goto unlock; 1049 } 1050 1051 tegra_sor_writel(sor, 0, SOR_STATE_1); 1052 tegra_sor_update(sor); 1053 1054 /* 1055 * The following accesses registers of the display controller, so make 1056 * sure it's only executed when the output is attached to one. 1057 */ 1058 if (dc) { 1059 /* 1060 * XXX: We can't do this here because it causes the SOR to go 1061 * into an erroneous state and the output will look scrambled 1062 * the next time it is enabled. Presumably this is because we 1063 * should be doing this only on the next VBLANK. A possible 1064 * solution would be to queue a "power-off" event to trigger 1065 * this code to be run during the next VBLANK. 1066 */ 1067 /* 1068 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 1069 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 1070 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 1071 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 1072 */ 1073 1074 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1075 value &= ~DISP_CTRL_MODE_MASK; 1076 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1077 1078 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1079 value &= ~SOR_ENABLE; 1080 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1081 1082 tegra_dc_commit(dc); 1083 } 1084 1085 err = tegra_sor_power_down(sor); 1086 if (err < 0) { 1087 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1088 goto unlock; 1089 } 1090 1091 if (sor->dpaux) { 1092 err = tegra_dpaux_disable(sor->dpaux); 1093 if (err < 0) { 1094 dev_err(sor->dev, "failed to disable DP: %d\n", err); 1095 goto unlock; 1096 } 1097 } 1098 1099 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); 1100 if (err < 0) { 1101 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); 1102 goto unlock; 1103 } 1104 1105 reset_control_assert(sor->rst); 1106 clk_disable_unprepare(sor->clk); 1107 1108 sor->enabled = false; 1109 1110 unlock: 1111 mutex_unlock(&sor->lock); 1112 return err; 1113 } 1114 1115 static int tegra_output_sor_setup_clock(struct tegra_output *output, 1116 struct clk *clk, unsigned long pclk, 1117 unsigned int *div) 1118 { 1119 struct tegra_sor *sor = to_sor(output); 1120 int err; 1121 1122 err = clk_set_parent(clk, sor->clk_parent); 1123 if (err < 0) { 1124 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 1125 return err; 1126 } 1127 1128 err = clk_set_rate(sor->clk_parent, pclk); 1129 if (err < 0) { 1130 dev_err(sor->dev, "failed to set clock rate to %lu Hz\n", pclk); 1131 return err; 1132 } 1133 1134 *div = 0; 1135 1136 return 0; 1137 } 1138 1139 static int tegra_output_sor_check_mode(struct tegra_output *output, 1140 struct drm_display_mode *mode, 1141 enum drm_mode_status *status) 1142 { 1143 /* 1144 * FIXME: For now, always assume that the mode is okay. 1145 */ 1146 1147 *status = MODE_OK; 1148 1149 return 0; 1150 } 1151 1152 static enum drm_connector_status 1153 tegra_output_sor_detect(struct tegra_output *output) 1154 { 1155 struct tegra_sor *sor = to_sor(output); 1156 1157 if (sor->dpaux) 1158 return tegra_dpaux_detect(sor->dpaux); 1159 1160 return connector_status_unknown; 1161 } 1162 1163 static const struct tegra_output_ops sor_ops = { 1164 .enable = tegra_output_sor_enable, 1165 .disable = tegra_output_sor_disable, 1166 .setup_clock = tegra_output_sor_setup_clock, 1167 .check_mode = tegra_output_sor_check_mode, 1168 .detect = tegra_output_sor_detect, 1169 }; 1170 1171 static int tegra_sor_crc_open(struct inode *inode, struct file *file) 1172 { 1173 file->private_data = inode->i_private; 1174 1175 return 0; 1176 } 1177 1178 static int tegra_sor_crc_release(struct inode *inode, struct file *file) 1179 { 1180 return 0; 1181 } 1182 1183 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 1184 { 1185 u32 value; 1186 1187 timeout = jiffies + msecs_to_jiffies(timeout); 1188 1189 while (time_before(jiffies, timeout)) { 1190 value = tegra_sor_readl(sor, SOR_CRC_A); 1191 if (value & SOR_CRC_A_VALID) 1192 return 0; 1193 1194 usleep_range(100, 200); 1195 } 1196 1197 return -ETIMEDOUT; 1198 } 1199 1200 static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer, 1201 size_t size, loff_t *ppos) 1202 { 1203 struct tegra_sor *sor = file->private_data; 1204 ssize_t num, err; 1205 char buf[10]; 1206 u32 value; 1207 1208 mutex_lock(&sor->lock); 1209 1210 if (!sor->enabled) { 1211 err = -EAGAIN; 1212 goto unlock; 1213 } 1214 1215 value = tegra_sor_readl(sor, SOR_STATE_1); 1216 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1217 tegra_sor_writel(sor, value, SOR_STATE_1); 1218 1219 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 1220 value |= SOR_CRC_CNTRL_ENABLE; 1221 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 1222 1223 value = tegra_sor_readl(sor, SOR_TEST); 1224 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 1225 tegra_sor_writel(sor, value, SOR_TEST); 1226 1227 err = tegra_sor_crc_wait(sor, 100); 1228 if (err < 0) 1229 goto unlock; 1230 1231 tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A); 1232 value = tegra_sor_readl(sor, SOR_CRC_B); 1233 1234 num = scnprintf(buf, sizeof(buf), "%08x\n", value); 1235 1236 err = simple_read_from_buffer(buffer, size, ppos, buf, num); 1237 1238 unlock: 1239 mutex_unlock(&sor->lock); 1240 return err; 1241 } 1242 1243 static const struct file_operations tegra_sor_crc_fops = { 1244 .owner = THIS_MODULE, 1245 .open = tegra_sor_crc_open, 1246 .read = tegra_sor_crc_read, 1247 .release = tegra_sor_crc_release, 1248 }; 1249 1250 static int tegra_sor_debugfs_init(struct tegra_sor *sor, 1251 struct drm_minor *minor) 1252 { 1253 struct dentry *entry; 1254 int err = 0; 1255 1256 sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root); 1257 if (!sor->debugfs) 1258 return -ENOMEM; 1259 1260 entry = debugfs_create_file("crc", 0644, sor->debugfs, sor, 1261 &tegra_sor_crc_fops); 1262 if (!entry) { 1263 dev_err(sor->dev, 1264 "cannot create /sys/kernel/debug/dri/%s/sor/crc\n", 1265 minor->debugfs_root->d_name.name); 1266 err = -ENOMEM; 1267 goto remove; 1268 } 1269 1270 return err; 1271 1272 remove: 1273 debugfs_remove(sor->debugfs); 1274 sor->debugfs = NULL; 1275 return err; 1276 } 1277 1278 static int tegra_sor_debugfs_exit(struct tegra_sor *sor) 1279 { 1280 debugfs_remove_recursive(sor->debugfs); 1281 sor->debugfs = NULL; 1282 1283 return 0; 1284 } 1285 1286 static int tegra_sor_init(struct host1x_client *client) 1287 { 1288 struct drm_device *drm = dev_get_drvdata(client->parent); 1289 struct tegra_sor *sor = host1x_client_to_sor(client); 1290 int err; 1291 1292 if (!sor->dpaux) 1293 return -ENODEV; 1294 1295 sor->output.type = TEGRA_OUTPUT_EDP; 1296 1297 sor->output.dev = sor->dev; 1298 sor->output.ops = &sor_ops; 1299 1300 err = tegra_output_init(drm, &sor->output); 1301 if (err < 0) { 1302 dev_err(sor->dev, "output setup failed: %d\n", err); 1303 return err; 1304 } 1305 1306 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1307 err = tegra_sor_debugfs_init(sor, drm->primary); 1308 if (err < 0) 1309 dev_err(sor->dev, "debugfs setup failed: %d\n", err); 1310 } 1311 1312 if (sor->dpaux) { 1313 err = tegra_dpaux_attach(sor->dpaux, &sor->output); 1314 if (err < 0) { 1315 dev_err(sor->dev, "failed to attach DP: %d\n", err); 1316 return err; 1317 } 1318 } 1319 1320 return 0; 1321 } 1322 1323 static int tegra_sor_exit(struct host1x_client *client) 1324 { 1325 struct tegra_sor *sor = host1x_client_to_sor(client); 1326 int err; 1327 1328 err = tegra_output_disable(&sor->output); 1329 if (err < 0) { 1330 dev_err(sor->dev, "output failed to disable: %d\n", err); 1331 return err; 1332 } 1333 1334 if (sor->dpaux) { 1335 err = tegra_dpaux_detach(sor->dpaux); 1336 if (err < 0) { 1337 dev_err(sor->dev, "failed to detach DP: %d\n", err); 1338 return err; 1339 } 1340 } 1341 1342 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1343 err = tegra_sor_debugfs_exit(sor); 1344 if (err < 0) 1345 dev_err(sor->dev, "debugfs cleanup failed: %d\n", err); 1346 } 1347 1348 err = tegra_output_exit(&sor->output); 1349 if (err < 0) { 1350 dev_err(sor->dev, "output cleanup failed: %d\n", err); 1351 return err; 1352 } 1353 1354 return 0; 1355 } 1356 1357 static const struct host1x_client_ops sor_client_ops = { 1358 .init = tegra_sor_init, 1359 .exit = tegra_sor_exit, 1360 }; 1361 1362 static int tegra_sor_probe(struct platform_device *pdev) 1363 { 1364 struct device_node *np; 1365 struct tegra_sor *sor; 1366 struct resource *regs; 1367 int err; 1368 1369 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 1370 if (!sor) 1371 return -ENOMEM; 1372 1373 sor->output.dev = sor->dev = &pdev->dev; 1374 1375 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 1376 if (np) { 1377 sor->dpaux = tegra_dpaux_find_by_of_node(np); 1378 of_node_put(np); 1379 1380 if (!sor->dpaux) 1381 return -EPROBE_DEFER; 1382 } 1383 1384 err = tegra_output_probe(&sor->output); 1385 if (err < 0) 1386 return err; 1387 1388 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1389 sor->regs = devm_ioremap_resource(&pdev->dev, regs); 1390 if (IS_ERR(sor->regs)) 1391 return PTR_ERR(sor->regs); 1392 1393 sor->rst = devm_reset_control_get(&pdev->dev, "sor"); 1394 if (IS_ERR(sor->rst)) 1395 return PTR_ERR(sor->rst); 1396 1397 sor->clk = devm_clk_get(&pdev->dev, NULL); 1398 if (IS_ERR(sor->clk)) 1399 return PTR_ERR(sor->clk); 1400 1401 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1402 if (IS_ERR(sor->clk_parent)) 1403 return PTR_ERR(sor->clk_parent); 1404 1405 err = clk_prepare_enable(sor->clk_parent); 1406 if (err < 0) 1407 return err; 1408 1409 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 1410 if (IS_ERR(sor->clk_safe)) 1411 return PTR_ERR(sor->clk_safe); 1412 1413 err = clk_prepare_enable(sor->clk_safe); 1414 if (err < 0) 1415 return err; 1416 1417 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 1418 if (IS_ERR(sor->clk_dp)) 1419 return PTR_ERR(sor->clk_dp); 1420 1421 err = clk_prepare_enable(sor->clk_dp); 1422 if (err < 0) 1423 return err; 1424 1425 INIT_LIST_HEAD(&sor->client.list); 1426 sor->client.ops = &sor_client_ops; 1427 sor->client.dev = &pdev->dev; 1428 1429 mutex_init(&sor->lock); 1430 1431 err = host1x_client_register(&sor->client); 1432 if (err < 0) { 1433 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1434 err); 1435 return err; 1436 } 1437 1438 platform_set_drvdata(pdev, sor); 1439 1440 return 0; 1441 } 1442 1443 static int tegra_sor_remove(struct platform_device *pdev) 1444 { 1445 struct tegra_sor *sor = platform_get_drvdata(pdev); 1446 int err; 1447 1448 err = host1x_client_unregister(&sor->client); 1449 if (err < 0) { 1450 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1451 err); 1452 return err; 1453 } 1454 1455 clk_disable_unprepare(sor->clk_parent); 1456 clk_disable_unprepare(sor->clk_safe); 1457 clk_disable_unprepare(sor->clk_dp); 1458 clk_disable_unprepare(sor->clk); 1459 1460 return 0; 1461 } 1462 1463 static const struct of_device_id tegra_sor_of_match[] = { 1464 { .compatible = "nvidia,tegra124-sor", }, 1465 { }, 1466 }; 1467 MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 1468 1469 struct platform_driver tegra_sor_driver = { 1470 .driver = { 1471 .name = "tegra-sor", 1472 .of_match_table = tegra_sor_of_match, 1473 }, 1474 .probe = tegra_sor_probe, 1475 .remove = tegra_sor_remove, 1476 }; 1477