r100.c (ec208491936d6adb8a70c3dd4a517cdfe54e823d) r100.c (550e2d9270e2f0a10c3b063899f70e4cca25fe72)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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60MODULE_FIRMWARE(FIRMWARE_R520);
61
62#include "r100_track.h"
63
64/* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
66 */
67
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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60MODULE_FIRMWARE(FIRMWARE_R520);
61
62#include "r100_track.h"
63
64/* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
66 */
67
68/* hpd for digital panel detect/disconnect */
69bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
70{
71 bool connected = false;
72
73 switch (hpd) {
74 case RADEON_HPD_1:
75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
76 connected = true;
77 break;
78 case RADEON_HPD_2:
79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
80 connected = true;
81 break;
82 default:
83 break;
84 }
85 return connected;
86}
87
88void r100_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
90{
91 u32 tmp;
92 bool connected = r100_hpd_sense(rdev, hpd);
93
94 switch (hpd) {
95 case RADEON_HPD_1:
96 tmp = RREG32(RADEON_FP_GEN_CNTL);
97 if (connected)
98 tmp &= ~RADEON_FP_DETECT_INT_POL;
99 else
100 tmp |= RADEON_FP_DETECT_INT_POL;
101 WREG32(RADEON_FP_GEN_CNTL, tmp);
102 break;
103 case RADEON_HPD_2:
104 tmp = RREG32(RADEON_FP2_GEN_CNTL);
105 if (connected)
106 tmp &= ~RADEON_FP2_DETECT_INT_POL;
107 else
108 tmp |= RADEON_FP2_DETECT_INT_POL;
109 WREG32(RADEON_FP2_GEN_CNTL, tmp);
110 break;
111 default:
112 break;
113 }
114}
115
116void r100_hpd_init(struct radeon_device *rdev)
117{
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
120
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
124 case RADEON_HPD_1:
125 rdev->irq.hpd[0] = true;
126 break;
127 case RADEON_HPD_2:
128 rdev->irq.hpd[1] = true;
129 break;
130 default:
131 break;
132 }
133 }
134 r100_irq_set(rdev);
135}
136
137void r100_hpd_fini(struct radeon_device *rdev)
138{
139 struct drm_device *dev = rdev->ddev;
140 struct drm_connector *connector;
141
142 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
143 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
144 switch (radeon_connector->hpd.hpd) {
145 case RADEON_HPD_1:
146 rdev->irq.hpd[0] = false;
147 break;
148 case RADEON_HPD_2:
149 rdev->irq.hpd[1] = false;
150 break;
151 default:
152 break;
153 }
154 }
155}
156
68/*
69 * PCI GART
70 */
71void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
72{
73 /* TODO: can we do somethings here ? */
74 /* It seems hw only cache one entry so we should discard this
75 * entry otherwise if first GPU GART read hit this entry it

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89 if (r)
90 return r;
91 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
92 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
93 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
94 return radeon_gart_table_ram_alloc(rdev);
95}
96
157/*
158 * PCI GART
159 */
160void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
161{
162 /* TODO: can we do somethings here ? */
163 /* It seems hw only cache one entry so we should discard this
164 * entry otherwise if first GPU GART read hit this entry it

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178 if (r)
179 return r;
180 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
181 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
182 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
183 return radeon_gart_table_ram_alloc(rdev);
184}
185
186/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
187void r100_enable_bm(struct radeon_device *rdev)
188{
189 uint32_t tmp;
190 /* Enable bus mastering */
191 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
192 WREG32(RADEON_BUS_CNTL, tmp);
193}
194
97int r100_pci_gart_enable(struct radeon_device *rdev)
98{
99 uint32_t tmp;
100
101 /* discard memory request outside of configured range */
102 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
103 WREG32(RADEON_AIC_CNTL, tmp);
104 /* set address range for PCI address translate */
105 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
106 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
107 WREG32(RADEON_AIC_HI_ADDR, tmp);
195int r100_pci_gart_enable(struct radeon_device *rdev)
196{
197 uint32_t tmp;
198
199 /* discard memory request outside of configured range */
200 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
201 WREG32(RADEON_AIC_CNTL, tmp);
202 /* set address range for PCI address translate */
203 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
204 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
205 WREG32(RADEON_AIC_HI_ADDR, tmp);
108 /* Enable bus mastering */
109 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
110 WREG32(RADEON_BUS_CNTL, tmp);
111 /* set PCI GART page-table base address */
112 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
113 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
114 WREG32(RADEON_AIC_CNTL, tmp);
115 r100_pci_gart_tlb_flush(rdev);
116 rdev->gart.ready = true;
117 return 0;
118}

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152 tmp |= RADEON_SW_INT_ENABLE;
153 }
154 if (rdev->irq.crtc_vblank_int[0]) {
155 tmp |= RADEON_CRTC_VBLANK_MASK;
156 }
157 if (rdev->irq.crtc_vblank_int[1]) {
158 tmp |= RADEON_CRTC2_VBLANK_MASK;
159 }
206 /* set PCI GART page-table base address */
207 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
208 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
209 WREG32(RADEON_AIC_CNTL, tmp);
210 r100_pci_gart_tlb_flush(rdev);
211 rdev->gart.ready = true;
212 return 0;
213}

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247 tmp |= RADEON_SW_INT_ENABLE;
248 }
249 if (rdev->irq.crtc_vblank_int[0]) {
250 tmp |= RADEON_CRTC_VBLANK_MASK;
251 }
252 if (rdev->irq.crtc_vblank_int[1]) {
253 tmp |= RADEON_CRTC2_VBLANK_MASK;
254 }
255 if (rdev->irq.hpd[0]) {
256 tmp |= RADEON_FP_DETECT_MASK;
257 }
258 if (rdev->irq.hpd[1]) {
259 tmp |= RADEON_FP2_DETECT_MASK;
260 }
160 WREG32(RADEON_GEN_INT_CNTL, tmp);
161 return 0;
162}
163
164void r100_irq_disable(struct radeon_device *rdev)
165{
166 u32 tmp;
167
168 WREG32(R_000040_GEN_INT_CNTL, 0);
169 /* Wait and acknowledge irq */
170 mdelay(1);
171 tmp = RREG32(R_000044_GEN_INT_STATUS);
172 WREG32(R_000044_GEN_INT_STATUS, tmp);
173}
174
175static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
176{
177 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
261 WREG32(RADEON_GEN_INT_CNTL, tmp);
262 return 0;
263}
264
265void r100_irq_disable(struct radeon_device *rdev)
266{
267 u32 tmp;
268
269 WREG32(R_000040_GEN_INT_CNTL, 0);
270 /* Wait and acknowledge irq */
271 mdelay(1);
272 tmp = RREG32(R_000044_GEN_INT_STATUS);
273 WREG32(R_000044_GEN_INT_STATUS, tmp);
274}
275
276static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
277{
278 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
178 uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
179 RADEON_CRTC2_VBLANK_STAT;
279 uint32_t irq_mask = RADEON_SW_INT_TEST |
280 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
281 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
180
181 if (irqs) {
182 WREG32(RADEON_GEN_INT_STATUS, irqs);
183 }
184 return irqs & irq_mask;
185}
186
187int r100_irq_process(struct radeon_device *rdev)
188{
189 uint32_t status, msi_rearm;
282
283 if (irqs) {
284 WREG32(RADEON_GEN_INT_STATUS, irqs);
285 }
286 return irqs & irq_mask;
287}
288
289int r100_irq_process(struct radeon_device *rdev)
290{
291 uint32_t status, msi_rearm;
292 bool queue_hotplug = false;
190
191 status = r100_irq_ack(rdev);
192 if (!status) {
193 return IRQ_NONE;
194 }
195 if (rdev->shutdown) {
196 return IRQ_NONE;
197 }

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202 }
203 /* Vertical blank interrupts */
204 if (status & RADEON_CRTC_VBLANK_STAT) {
205 drm_handle_vblank(rdev->ddev, 0);
206 }
207 if (status & RADEON_CRTC2_VBLANK_STAT) {
208 drm_handle_vblank(rdev->ddev, 1);
209 }
293
294 status = r100_irq_ack(rdev);
295 if (!status) {
296 return IRQ_NONE;
297 }
298 if (rdev->shutdown) {
299 return IRQ_NONE;
300 }

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305 }
306 /* Vertical blank interrupts */
307 if (status & RADEON_CRTC_VBLANK_STAT) {
308 drm_handle_vblank(rdev->ddev, 0);
309 }
310 if (status & RADEON_CRTC2_VBLANK_STAT) {
311 drm_handle_vblank(rdev->ddev, 1);
312 }
313 if (status & RADEON_FP_DETECT_STAT) {
314 queue_hotplug = true;
315 DRM_DEBUG("HPD1\n");
316 }
317 if (status & RADEON_FP2_DETECT_STAT) {
318 queue_hotplug = true;
319 DRM_DEBUG("HPD2\n");
320 }
210 status = r100_irq_ack(rdev);
211 }
321 status = r100_irq_ack(rdev);
322 }
323 if (queue_hotplug)
324 queue_work(rdev->wq, &rdev->hotplug_work);
212 if (rdev->msi_enabled) {
213 switch (rdev->family) {
214 case CHIP_RS400:
215 case CHIP_RS480:
216 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
217 WREG32(RADEON_AIC_CNTL, msi_rearm);
218 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
219 break;

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250 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
251}
252
253int r100_wb_init(struct radeon_device *rdev)
254{
255 int r;
256
257 if (rdev->wb.wb_obj == NULL) {
325 if (rdev->msi_enabled) {
326 switch (rdev->family) {
327 case CHIP_RS400:
328 case CHIP_RS480:
329 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
330 WREG32(RADEON_AIC_CNTL, msi_rearm);
331 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
332 break;

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363 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
364}
365
366int r100_wb_init(struct radeon_device *rdev)
367{
368 int r;
369
370 if (rdev->wb.wb_obj == NULL) {
258 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
259 true,
260 RADEON_GEM_DOMAIN_GTT,
261 false, &rdev->wb.wb_obj);
371 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
372 RADEON_GEM_DOMAIN_GTT,
373 &rdev->wb.wb_obj);
262 if (r) {
374 if (r) {
263 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
375 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
264 return r;
265 }
376 return r;
377 }
266 r = radeon_object_pin(rdev->wb.wb_obj,
267 RADEON_GEM_DOMAIN_GTT,
268 &rdev->wb.gpu_addr);
378 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
379 if (unlikely(r != 0))
380 return r;
381 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
382 &rdev->wb.gpu_addr);
269 if (r) {
383 if (r) {
270 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
384 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
385 radeon_bo_unreserve(rdev->wb.wb_obj);
271 return r;
272 }
386 return r;
387 }
273 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
388 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
389 radeon_bo_unreserve(rdev->wb.wb_obj);
274 if (r) {
390 if (r) {
275 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
391 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
276 return r;
277 }
278 }
279 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
280 WREG32(R_00070C_CP_RB_RPTR_ADDR,
281 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
282 WREG32(R_000770_SCRATCH_UMSK, 0xff);
283 return 0;
284}
285
286void r100_wb_disable(struct radeon_device *rdev)
287{
288 WREG32(R_000770_SCRATCH_UMSK, 0);
289}
290
291void r100_wb_fini(struct radeon_device *rdev)
292{
392 return r;
393 }
394 }
395 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
396 WREG32(R_00070C_CP_RB_RPTR_ADDR,
397 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
398 WREG32(R_000770_SCRATCH_UMSK, 0xff);
399 return 0;
400}
401
402void r100_wb_disable(struct radeon_device *rdev)
403{
404 WREG32(R_000770_SCRATCH_UMSK, 0);
405}
406
407void r100_wb_fini(struct radeon_device *rdev)
408{
409 int r;
410
293 r100_wb_disable(rdev);
294 if (rdev->wb.wb_obj) {
411 r100_wb_disable(rdev);
412 if (rdev->wb.wb_obj) {
295 radeon_object_kunmap(rdev->wb.wb_obj);
296 radeon_object_unpin(rdev->wb.wb_obj);
297 radeon_object_unref(&rdev->wb.wb_obj);
413 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
414 if (unlikely(r != 0)) {
415 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
416 return;
417 }
418 radeon_bo_kunmap(rdev->wb.wb_obj);
419 radeon_bo_unpin(rdev->wb.wb_obj);
420 radeon_bo_unreserve(rdev->wb.wb_obj);
421 radeon_bo_unref(&rdev->wb.wb_obj);
298 rdev->wb.wb = NULL;
299 rdev->wb.wb_obj = NULL;
300 }
301}
302
303int r100_copy_blit(struct radeon_device *rdev,
304 uint64_t src_offset,
305 uint64_t dst_offset,

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1283 reg, idx);
1284 return -EINVAL;
1285 }
1286 return 0;
1287}
1288
1289int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1290 struct radeon_cs_packet *pkt,
422 rdev->wb.wb = NULL;
423 rdev->wb.wb_obj = NULL;
424 }
425}
426
427int r100_copy_blit(struct radeon_device *rdev,
428 uint64_t src_offset,
429 uint64_t dst_offset,

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1407 reg, idx);
1408 return -EINVAL;
1409 }
1410 return 0;
1411}
1412
1413int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1414 struct radeon_cs_packet *pkt,
1291 struct radeon_object *robj)
1415 struct radeon_bo *robj)
1292{
1293 unsigned idx;
1294 u32 value;
1295 idx = pkt->idx + 1;
1296 value = radeon_get_ib_value(p, idx + 2);
1416{
1417 unsigned idx;
1418 u32 value;
1419 idx = pkt->idx + 1;
1420 value = radeon_get_ib_value(p, idx + 2);
1297 if ((value + 1) > radeon_object_size(robj)) {
1421 if ((value + 1) > radeon_bo_size(robj)) {
1298 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1299 "(need %u have %lu) !\n",
1300 value + 1,
1422 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1423 "(need %u have %lu) !\n",
1424 value + 1,
1301 radeon_object_size(robj));
1425 radeon_bo_size(robj));
1302 return -EINVAL;
1303 }
1304 return 0;
1305}
1306
1307static int r100_packet3_check(struct radeon_cs_parser *p,
1308 struct radeon_cs_packet *pkt)
1309{

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1578}
1579
1580void r100_gpu_init(struct radeon_device *rdev)
1581{
1582 /* TODO: anythings to do here ? pipes ? */
1583 r100_hdp_reset(rdev);
1584}
1585
1426 return -EINVAL;
1427 }
1428 return 0;
1429}
1430
1431static int r100_packet3_check(struct radeon_cs_parser *p,
1432 struct radeon_cs_packet *pkt)
1433{

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1702}
1703
1704void r100_gpu_init(struct radeon_device *rdev)
1705{
1706 /* TODO: anythings to do here ? pipes ? */
1707 r100_hdp_reset(rdev);
1708}
1709
1710void r100_hdp_flush(struct radeon_device *rdev)
1711{
1712 u32 tmp;
1713 tmp = RREG32(RADEON_HOST_PATH_CNTL);
1714 tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;
1715 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1716}
1717
1586void r100_hdp_reset(struct radeon_device *rdev)
1587{
1588 uint32_t tmp;
1589
1590 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1591 tmp |= (7 << 28);
1592 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1593 (void)RREG32(RADEON_HOST_PATH_CNTL);

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1645 if (status & (1 << 31)) {
1646 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1647 return -1;
1648 }
1649 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1650 return 0;
1651}
1652
1718void r100_hdp_reset(struct radeon_device *rdev)
1719{
1720 uint32_t tmp;
1721
1722 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1723 tmp |= (7 << 28);
1724 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1725 (void)RREG32(RADEON_HOST_PATH_CNTL);

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1777 if (status & (1 << 31)) {
1778 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1779 return -1;
1780 }
1781 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1782 return 0;
1783}
1784
1785void r100_set_common_regs(struct radeon_device *rdev)
1786{
1787 /* set these so they don't interfere with anything */
1788 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1789 WREG32(RADEON_SUBPIC_CNTL, 0);
1790 WREG32(RADEON_VIPH_CONTROL, 0);
1791 WREG32(RADEON_I2C_CNTL_1, 0);
1792 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1793 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1794 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1795}
1653
1654/*
1655 * VRAM info
1656 */
1657static void r100_vram_get_type(struct radeon_device *rdev)
1658{
1659 uint32_t tmp;
1660

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2589 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2590 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2591}
2592
2593static int r100_cs_track_cube(struct radeon_device *rdev,
2594 struct r100_cs_track *track, unsigned idx)
2595{
2596 unsigned face, w, h;
1796
1797/*
1798 * VRAM info
1799 */
1800static void r100_vram_get_type(struct radeon_device *rdev)
1801{
1802 uint32_t tmp;
1803

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2732 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2733 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2734}
2735
2736static int r100_cs_track_cube(struct radeon_device *rdev,
2737 struct r100_cs_track *track, unsigned idx)
2738{
2739 unsigned face, w, h;
2597 struct radeon_object *cube_robj;
2740 struct radeon_bo *cube_robj;
2598 unsigned long size;
2599
2600 for (face = 0; face < 5; face++) {
2601 cube_robj = track->textures[idx].cube_info[face].robj;
2602 w = track->textures[idx].cube_info[face].width;
2603 h = track->textures[idx].cube_info[face].height;
2604
2605 size = w * h;
2606 size *= track->textures[idx].cpp;
2607
2608 size += track->textures[idx].cube_info[face].offset;
2609
2741 unsigned long size;
2742
2743 for (face = 0; face < 5; face++) {
2744 cube_robj = track->textures[idx].cube_info[face].robj;
2745 w = track->textures[idx].cube_info[face].width;
2746 h = track->textures[idx].cube_info[face].height;
2747
2748 size = w * h;
2749 size *= track->textures[idx].cpp;
2750
2751 size += track->textures[idx].cube_info[face].offset;
2752
2610 if (size > radeon_object_size(cube_robj)) {
2753 if (size > radeon_bo_size(cube_robj)) {
2611 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2754 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2612 size, radeon_object_size(cube_robj));
2755 size, radeon_bo_size(cube_robj));
2613 r100_cs_track_texture_print(&track->textures[idx]);
2614 return -1;
2615 }
2616 }
2617 return 0;
2618}
2619
2620static int r100_cs_track_texture_check(struct radeon_device *rdev,
2621 struct r100_cs_track *track)
2622{
2756 r100_cs_track_texture_print(&track->textures[idx]);
2757 return -1;
2758 }
2759 }
2760 return 0;
2761}
2762
2763static int r100_cs_track_texture_check(struct radeon_device *rdev,
2764 struct r100_cs_track *track)
2765{
2623 struct radeon_object *robj;
2766 struct radeon_bo *robj;
2624 unsigned long size;
2625 unsigned u, i, w, h;
2626 int ret;
2627
2628 for (u = 0; u < track->num_texture; u++) {
2629 if (!track->textures[u].enabled)
2630 continue;
2631 robj = track->textures[u].robj;

--- 39 unchanged lines hidden (view full) ---

2671 } else
2672 size *= 6;
2673 break;
2674 default:
2675 DRM_ERROR("Invalid texture coordinate type %u for unit "
2676 "%u\n", track->textures[u].tex_coord_type, u);
2677 return -EINVAL;
2678 }
2767 unsigned long size;
2768 unsigned u, i, w, h;
2769 int ret;
2770
2771 for (u = 0; u < track->num_texture; u++) {
2772 if (!track->textures[u].enabled)
2773 continue;
2774 robj = track->textures[u].robj;

--- 39 unchanged lines hidden (view full) ---

2814 } else
2815 size *= 6;
2816 break;
2817 default:
2818 DRM_ERROR("Invalid texture coordinate type %u for unit "
2819 "%u\n", track->textures[u].tex_coord_type, u);
2820 return -EINVAL;
2821 }
2679 if (size > radeon_object_size(robj)) {
2822 if (size > radeon_bo_size(robj)) {
2680 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2823 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2681 "%lu\n", u, size, radeon_object_size(robj));
2824 "%lu\n", u, size, radeon_bo_size(robj));
2682 r100_cs_track_texture_print(&track->textures[u]);
2683 return -EINVAL;
2684 }
2685 }
2686 return 0;
2687}
2688
2689int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)

--- 5 unchanged lines hidden (view full) ---

2695
2696 for (i = 0; i < track->num_cb; i++) {
2697 if (track->cb[i].robj == NULL) {
2698 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2699 return -EINVAL;
2700 }
2701 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2702 size += track->cb[i].offset;
2825 r100_cs_track_texture_print(&track->textures[u]);
2826 return -EINVAL;
2827 }
2828 }
2829 return 0;
2830}
2831
2832int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)

--- 5 unchanged lines hidden (view full) ---

2838
2839 for (i = 0; i < track->num_cb; i++) {
2840 if (track->cb[i].robj == NULL) {
2841 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2842 return -EINVAL;
2843 }
2844 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2845 size += track->cb[i].offset;
2703 if (size > radeon_object_size(track->cb[i].robj)) {
2846 if (size > radeon_bo_size(track->cb[i].robj)) {
2704 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2705 "(need %lu have %lu) !\n", i, size,
2847 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2848 "(need %lu have %lu) !\n", i, size,
2706 radeon_object_size(track->cb[i].robj));
2849 radeon_bo_size(track->cb[i].robj));
2707 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2708 i, track->cb[i].pitch, track->cb[i].cpp,
2709 track->cb[i].offset, track->maxy);
2710 return -EINVAL;
2711 }
2712 }
2713 if (track->z_enabled) {
2714 if (track->zb.robj == NULL) {
2715 DRM_ERROR("[drm] No buffer for z buffer !\n");
2716 return -EINVAL;
2717 }
2718 size = track->zb.pitch * track->zb.cpp * track->maxy;
2719 size += track->zb.offset;
2850 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2851 i, track->cb[i].pitch, track->cb[i].cpp,
2852 track->cb[i].offset, track->maxy);
2853 return -EINVAL;
2854 }
2855 }
2856 if (track->z_enabled) {
2857 if (track->zb.robj == NULL) {
2858 DRM_ERROR("[drm] No buffer for z buffer !\n");
2859 return -EINVAL;
2860 }
2861 size = track->zb.pitch * track->zb.cpp * track->maxy;
2862 size += track->zb.offset;
2720 if (size > radeon_object_size(track->zb.robj)) {
2863 if (size > radeon_bo_size(track->zb.robj)) {
2721 DRM_ERROR("[drm] Buffer too small for z buffer "
2722 "(need %lu have %lu) !\n", size,
2864 DRM_ERROR("[drm] Buffer too small for z buffer "
2865 "(need %lu have %lu) !\n", size,
2723 radeon_object_size(track->zb.robj));
2866 radeon_bo_size(track->zb.robj));
2724 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2725 track->zb.pitch, track->zb.cpp,
2726 track->zb.offset, track->maxy);
2727 return -EINVAL;
2728 }
2729 }
2730 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2731 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2732 switch (prim_walk) {
2733 case 1:
2734 for (i = 0; i < track->num_arrays; i++) {
2735 size = track->arrays[i].esize * track->max_indx * 4;
2736 if (track->arrays[i].robj == NULL) {
2737 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2738 "bound\n", prim_walk, i);
2739 return -EINVAL;
2740 }
2867 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2868 track->zb.pitch, track->zb.cpp,
2869 track->zb.offset, track->maxy);
2870 return -EINVAL;
2871 }
2872 }
2873 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2874 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2875 switch (prim_walk) {
2876 case 1:
2877 for (i = 0; i < track->num_arrays; i++) {
2878 size = track->arrays[i].esize * track->max_indx * 4;
2879 if (track->arrays[i].robj == NULL) {
2880 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2881 "bound\n", prim_walk, i);
2882 return -EINVAL;
2883 }
2741 if (size > radeon_object_size(track->arrays[i].robj)) {
2742 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2743 "have %lu dwords\n", prim_walk, i,
2744 size >> 2,
2745 radeon_object_size(track->arrays[i].robj) >> 2);
2884 if (size > radeon_bo_size(track->arrays[i].robj)) {
2885 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2886 "need %lu dwords have %lu dwords\n",
2887 prim_walk, i, size >> 2,
2888 radeon_bo_size(track->arrays[i].robj)
2889 >> 2);
2746 DRM_ERROR("Max indices %u\n", track->max_indx);
2747 return -EINVAL;
2748 }
2749 }
2750 break;
2751 case 2:
2752 for (i = 0; i < track->num_arrays; i++) {
2753 size = track->arrays[i].esize * (nverts - 1) * 4;
2754 if (track->arrays[i].robj == NULL) {
2755 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2756 "bound\n", prim_walk, i);
2757 return -EINVAL;
2758 }
2890 DRM_ERROR("Max indices %u\n", track->max_indx);
2891 return -EINVAL;
2892 }
2893 }
2894 break;
2895 case 2:
2896 for (i = 0; i < track->num_arrays; i++) {
2897 size = track->arrays[i].esize * (nverts - 1) * 4;
2898 if (track->arrays[i].robj == NULL) {
2899 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2900 "bound\n", prim_walk, i);
2901 return -EINVAL;
2902 }
2759 if (size > radeon_object_size(track->arrays[i].robj)) {
2760 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2761 "have %lu dwords\n", prim_walk, i, size >> 2,
2762 radeon_object_size(track->arrays[i].robj) >> 2);
2903 if (size > radeon_bo_size(track->arrays[i].robj)) {
2904 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2905 "need %lu dwords have %lu dwords\n",
2906 prim_walk, i, size >> 2,
2907 radeon_bo_size(track->arrays[i].robj)
2908 >> 2);
2763 return -EINVAL;
2764 }
2765 }
2766 break;
2767 case 3:
2768 size = track->vtx_size * nverts;
2769 if (size != track->immd_dwords) {
2770 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",

--- 325 unchanged lines hidden (view full) ---

3096 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3097 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3098}
3099
3100static int r100_startup(struct radeon_device *rdev)
3101{
3102 int r;
3103
2909 return -EINVAL;
2910 }
2911 }
2912 break;
2913 case 3:
2914 size = track->vtx_size * nverts;
2915 if (size != track->immd_dwords) {
2916 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",

--- 325 unchanged lines hidden (view full) ---

3242 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3243 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3244}
3245
3246static int r100_startup(struct radeon_device *rdev)
3247{
3248 int r;
3249
3250 /* set common regs */
3251 r100_set_common_regs(rdev);
3252 /* program mc */
3104 r100_mc_program(rdev);
3105 /* Resume clock */
3106 r100_clock_startup(rdev);
3107 /* Initialize GPU configuration (# pipes, ...) */
3108 r100_gpu_init(rdev);
3109 /* Initialize GART (initialize after TTM so we can allocate
3110 * memory through TTM but finalize after TTM) */
3253 r100_mc_program(rdev);
3254 /* Resume clock */
3255 r100_clock_startup(rdev);
3256 /* Initialize GPU configuration (# pipes, ...) */
3257 r100_gpu_init(rdev);
3258 /* Initialize GART (initialize after TTM so we can allocate
3259 * memory through TTM but finalize after TTM) */
3260 r100_enable_bm(rdev);
3111 if (rdev->flags & RADEON_IS_PCI) {
3112 r = r100_pci_gart_enable(rdev);
3113 if (r)
3114 return r;
3115 }
3116 /* Enable IRQ */
3261 if (rdev->flags & RADEON_IS_PCI) {
3262 r = r100_pci_gart_enable(rdev);
3263 if (r)
3264 return r;
3265 }
3266 /* Enable IRQ */
3117 rdev->irq.sw_int = true;
3118 r100_irq_set(rdev);
3119 /* 1M ring buffer */
3120 r = r100_cp_init(rdev, 1024 * 1024);
3121 if (r) {
3122 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3123 return r;
3124 }
3125 r = r100_wb_init(rdev);

--- 19 unchanged lines hidden (view full) ---

3145 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3146 RREG32(R_000E40_RBBM_STATUS),
3147 RREG32(R_0007C0_CP_STAT));
3148 }
3149 /* post */
3150 radeon_combios_asic_init(rdev->ddev);
3151 /* Resume clock after posting */
3152 r100_clock_startup(rdev);
3267 r100_irq_set(rdev);
3268 /* 1M ring buffer */
3269 r = r100_cp_init(rdev, 1024 * 1024);
3270 if (r) {
3271 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3272 return r;
3273 }
3274 r = r100_wb_init(rdev);

--- 19 unchanged lines hidden (view full) ---

3294 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3295 RREG32(R_000E40_RBBM_STATUS),
3296 RREG32(R_0007C0_CP_STAT));
3297 }
3298 /* post */
3299 radeon_combios_asic_init(rdev->ddev);
3300 /* Resume clock after posting */
3301 r100_clock_startup(rdev);
3302 /* Initialize surface registers */
3303 radeon_surface_init(rdev);
3153 return r100_startup(rdev);
3154}
3155
3156int r100_suspend(struct radeon_device *rdev)
3157{
3158 r100_cp_disable(rdev);
3159 r100_wb_disable(rdev);
3160 r100_irq_disable(rdev);

--- 8 unchanged lines hidden (view full) ---

3169 r100_cp_fini(rdev);
3170 r100_wb_fini(rdev);
3171 r100_ib_fini(rdev);
3172 radeon_gem_fini(rdev);
3173 if (rdev->flags & RADEON_IS_PCI)
3174 r100_pci_gart_fini(rdev);
3175 radeon_irq_kms_fini(rdev);
3176 radeon_fence_driver_fini(rdev);
3304 return r100_startup(rdev);
3305}
3306
3307int r100_suspend(struct radeon_device *rdev)
3308{
3309 r100_cp_disable(rdev);
3310 r100_wb_disable(rdev);
3311 r100_irq_disable(rdev);

--- 8 unchanged lines hidden (view full) ---

3320 r100_cp_fini(rdev);
3321 r100_wb_fini(rdev);
3322 r100_ib_fini(rdev);
3323 radeon_gem_fini(rdev);
3324 if (rdev->flags & RADEON_IS_PCI)
3325 r100_pci_gart_fini(rdev);
3326 radeon_irq_kms_fini(rdev);
3327 radeon_fence_driver_fini(rdev);
3177 radeon_object_fini(rdev);
3328 radeon_bo_fini(rdev);
3178 radeon_atombios_fini(rdev);
3179 kfree(rdev->bios);
3180 rdev->bios = NULL;
3181}
3182
3183int r100_mc_init(struct radeon_device *rdev)
3184{
3185 int r;

--- 51 unchanged lines hidden (view full) ---

3237 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3238 if (radeon_gpu_reset(rdev)) {
3239 dev_warn(rdev->dev,
3240 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3241 RREG32(R_000E40_RBBM_STATUS),
3242 RREG32(R_0007C0_CP_STAT));
3243 }
3244 /* check if cards are posted or not */
3329 radeon_atombios_fini(rdev);
3330 kfree(rdev->bios);
3331 rdev->bios = NULL;
3332}
3333
3334int r100_mc_init(struct radeon_device *rdev)
3335{
3336 int r;

--- 51 unchanged lines hidden (view full) ---

3388 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3389 if (radeon_gpu_reset(rdev)) {
3390 dev_warn(rdev->dev,
3391 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3392 RREG32(R_000E40_RBBM_STATUS),
3393 RREG32(R_0007C0_CP_STAT));
3394 }
3395 /* check if cards are posted or not */
3245 if (!radeon_card_posted(rdev) && rdev->bios) {
3246 DRM_INFO("GPU not posted. posting now...\n");
3247 radeon_combios_asic_init(rdev->ddev);
3248 }
3396 if (radeon_boot_test_post_card(rdev) == false)
3397 return -EINVAL;
3249 /* Set asic errata */
3250 r100_errata(rdev);
3251 /* Initialize clocks */
3252 radeon_get_clock_info(rdev->ddev);
3253 /* Get vram informations */
3254 r100_vram_info(rdev);
3255 /* Initialize memory controller (also test AGP) */
3256 r = r100_mc_init(rdev);
3257 if (r)
3258 return r;
3259 /* Fence driver */
3260 r = radeon_fence_driver_init(rdev);
3261 if (r)
3262 return r;
3263 r = radeon_irq_kms_init(rdev);
3264 if (r)
3265 return r;
3266 /* Memory manager */
3398 /* Set asic errata */
3399 r100_errata(rdev);
3400 /* Initialize clocks */
3401 radeon_get_clock_info(rdev->ddev);
3402 /* Get vram informations */
3403 r100_vram_info(rdev);
3404 /* Initialize memory controller (also test AGP) */
3405 r = r100_mc_init(rdev);
3406 if (r)
3407 return r;
3408 /* Fence driver */
3409 r = radeon_fence_driver_init(rdev);
3410 if (r)
3411 return r;
3412 r = radeon_irq_kms_init(rdev);
3413 if (r)
3414 return r;
3415 /* Memory manager */
3267 r = radeon_object_init(rdev);
3416 r = radeon_bo_init(rdev);
3268 if (r)
3269 return r;
3270 if (rdev->flags & RADEON_IS_PCI) {
3271 r = r100_pci_gart_init(rdev);
3272 if (r)
3273 return r;
3274 }
3275 r100_set_safe_registers(rdev);

--- 16 unchanged lines hidden --- 		3417 if (r)
3418 return r;
3419 if (rdev->flags & RADEON_IS_PCI) {
3420 r = r100_pci_gart_init(rdev);
3421 if (r)
3422 return r;
3423 }
3424 r100_set_safe_registers(rdev);

--- 16 unchanged lines hidden ---