1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <linux/seq_file.h> 29 #include "drmP.h" 30 #include "drm.h" 31 #include "radeon_drm.h" 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "r100d.h" 35 #include "rs100d.h" 36 #include "rv200d.h" 37 #include "rv250d.h" 38 39 #include <linux/firmware.h> 40 #include <linux/platform_device.h> 41 42 #include "r100_reg_safe.h" 43 #include "rn50_reg_safe.h" 44 45 /* Firmware Names */ 46 #define FIRMWARE_R100 "radeon/R100_cp.bin" 47 #define FIRMWARE_R200 "radeon/R200_cp.bin" 48 #define FIRMWARE_R300 "radeon/R300_cp.bin" 49 #define FIRMWARE_R420 "radeon/R420_cp.bin" 50 #define FIRMWARE_RS690 "radeon/RS690_cp.bin" 51 #define FIRMWARE_RS600 "radeon/RS600_cp.bin" 52 #define FIRMWARE_R520 "radeon/R520_cp.bin" 53 54 MODULE_FIRMWARE(FIRMWARE_R100); 55 MODULE_FIRMWARE(FIRMWARE_R200); 56 MODULE_FIRMWARE(FIRMWARE_R300); 57 MODULE_FIRMWARE(FIRMWARE_R420); 58 MODULE_FIRMWARE(FIRMWARE_RS690); 59 MODULE_FIRMWARE(FIRMWARE_RS600); 60 MODULE_FIRMWARE(FIRMWARE_R520); 61 62 #include "r100_track.h" 63 64 /* This files gather functions specifics to: 65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 66 */ 67 68 /* hpd for digital panel detect/disconnect */ 69 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 70 { 71 bool connected = false; 72 73 switch (hpd) { 74 case RADEON_HPD_1: 75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 76 connected = true; 77 break; 78 case RADEON_HPD_2: 79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 80 connected = true; 81 break; 82 default: 83 break; 84 } 85 return connected; 86 } 87 88 void r100_hpd_set_polarity(struct radeon_device *rdev, 89 enum radeon_hpd_id hpd) 90 { 91 u32 tmp; 92 bool connected = r100_hpd_sense(rdev, hpd); 93 94 switch (hpd) { 95 case RADEON_HPD_1: 96 tmp = RREG32(RADEON_FP_GEN_CNTL); 97 if (connected) 98 tmp &= ~RADEON_FP_DETECT_INT_POL; 99 else 100 tmp |= RADEON_FP_DETECT_INT_POL; 101 WREG32(RADEON_FP_GEN_CNTL, tmp); 102 break; 103 case RADEON_HPD_2: 104 tmp = RREG32(RADEON_FP2_GEN_CNTL); 105 if (connected) 106 tmp &= ~RADEON_FP2_DETECT_INT_POL; 107 else 108 tmp |= RADEON_FP2_DETECT_INT_POL; 109 WREG32(RADEON_FP2_GEN_CNTL, tmp); 110 break; 111 default: 112 break; 113 } 114 } 115 116 void r100_hpd_init(struct radeon_device *rdev) 117 { 118 struct drm_device *dev = rdev->ddev; 119 struct drm_connector *connector; 120 121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 122 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 123 switch (radeon_connector->hpd.hpd) { 124 case RADEON_HPD_1: 125 rdev->irq.hpd[0] = true; 126 break; 127 case RADEON_HPD_2: 128 rdev->irq.hpd[1] = true; 129 break; 130 default: 131 break; 132 } 133 } 134 r100_irq_set(rdev); 135 } 136 137 void r100_hpd_fini(struct radeon_device *rdev) 138 { 139 struct drm_device *dev = rdev->ddev; 140 struct drm_connector *connector; 141 142 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 143 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 144 switch (radeon_connector->hpd.hpd) { 145 case RADEON_HPD_1: 146 rdev->irq.hpd[0] = false; 147 break; 148 case RADEON_HPD_2: 149 rdev->irq.hpd[1] = false; 150 break; 151 default: 152 break; 153 } 154 } 155 } 156 157 /* 158 * PCI GART 159 */ 160 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 161 { 162 /* TODO: can we do somethings here ? */ 163 /* It seems hw only cache one entry so we should discard this 164 * entry otherwise if first GPU GART read hit this entry it 165 * could end up in wrong address. */ 166 } 167 168 int r100_pci_gart_init(struct radeon_device *rdev) 169 { 170 int r; 171 172 if (rdev->gart.table.ram.ptr) { 173 WARN(1, "R100 PCI GART already initialized.\n"); 174 return 0; 175 } 176 /* Initialize common gart structure */ 177 r = radeon_gart_init(rdev); 178 if (r) 179 return r; 180 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 181 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 182 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 183 return radeon_gart_table_ram_alloc(rdev); 184 } 185 186 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 187 void r100_enable_bm(struct radeon_device *rdev) 188 { 189 uint32_t tmp; 190 /* Enable bus mastering */ 191 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 192 WREG32(RADEON_BUS_CNTL, tmp); 193 } 194 195 int r100_pci_gart_enable(struct radeon_device *rdev) 196 { 197 uint32_t tmp; 198 199 /* discard memory request outside of configured range */ 200 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 201 WREG32(RADEON_AIC_CNTL, tmp); 202 /* set address range for PCI address translate */ 203 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location); 204 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; 205 WREG32(RADEON_AIC_HI_ADDR, tmp); 206 /* set PCI GART page-table base address */ 207 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 208 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 209 WREG32(RADEON_AIC_CNTL, tmp); 210 r100_pci_gart_tlb_flush(rdev); 211 rdev->gart.ready = true; 212 return 0; 213 } 214 215 void r100_pci_gart_disable(struct radeon_device *rdev) 216 { 217 uint32_t tmp; 218 219 /* discard memory request outside of configured range */ 220 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 221 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 222 WREG32(RADEON_AIC_LO_ADDR, 0); 223 WREG32(RADEON_AIC_HI_ADDR, 0); 224 } 225 226 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 227 { 228 if (i < 0 || i > rdev->gart.num_gpu_pages) { 229 return -EINVAL; 230 } 231 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr)); 232 return 0; 233 } 234 235 void r100_pci_gart_fini(struct radeon_device *rdev) 236 { 237 r100_pci_gart_disable(rdev); 238 radeon_gart_table_ram_free(rdev); 239 radeon_gart_fini(rdev); 240 } 241 242 int r100_irq_set(struct radeon_device *rdev) 243 { 244 uint32_t tmp = 0; 245 246 if (rdev->irq.sw_int) { 247 tmp |= RADEON_SW_INT_ENABLE; 248 } 249 if (rdev->irq.crtc_vblank_int[0]) { 250 tmp |= RADEON_CRTC_VBLANK_MASK; 251 } 252 if (rdev->irq.crtc_vblank_int[1]) { 253 tmp |= RADEON_CRTC2_VBLANK_MASK; 254 } 255 if (rdev->irq.hpd[0]) { 256 tmp |= RADEON_FP_DETECT_MASK; 257 } 258 if (rdev->irq.hpd[1]) { 259 tmp |= RADEON_FP2_DETECT_MASK; 260 } 261 WREG32(RADEON_GEN_INT_CNTL, tmp); 262 return 0; 263 } 264 265 void r100_irq_disable(struct radeon_device *rdev) 266 { 267 u32 tmp; 268 269 WREG32(R_000040_GEN_INT_CNTL, 0); 270 /* Wait and acknowledge irq */ 271 mdelay(1); 272 tmp = RREG32(R_000044_GEN_INT_STATUS); 273 WREG32(R_000044_GEN_INT_STATUS, tmp); 274 } 275 276 static inline uint32_t r100_irq_ack(struct radeon_device *rdev) 277 { 278 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 279 uint32_t irq_mask = RADEON_SW_INT_TEST | 280 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 281 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 282 283 if (irqs) { 284 WREG32(RADEON_GEN_INT_STATUS, irqs); 285 } 286 return irqs & irq_mask; 287 } 288 289 int r100_irq_process(struct radeon_device *rdev) 290 { 291 uint32_t status, msi_rearm; 292 bool queue_hotplug = false; 293 294 status = r100_irq_ack(rdev); 295 if (!status) { 296 return IRQ_NONE; 297 } 298 if (rdev->shutdown) { 299 return IRQ_NONE; 300 } 301 while (status) { 302 /* SW interrupt */ 303 if (status & RADEON_SW_INT_TEST) { 304 radeon_fence_process(rdev); 305 } 306 /* Vertical blank interrupts */ 307 if (status & RADEON_CRTC_VBLANK_STAT) { 308 drm_handle_vblank(rdev->ddev, 0); 309 } 310 if (status & RADEON_CRTC2_VBLANK_STAT) { 311 drm_handle_vblank(rdev->ddev, 1); 312 } 313 if (status & RADEON_FP_DETECT_STAT) { 314 queue_hotplug = true; 315 DRM_DEBUG("HPD1\n"); 316 } 317 if (status & RADEON_FP2_DETECT_STAT) { 318 queue_hotplug = true; 319 DRM_DEBUG("HPD2\n"); 320 } 321 status = r100_irq_ack(rdev); 322 } 323 if (queue_hotplug) 324 queue_work(rdev->wq, &rdev->hotplug_work); 325 if (rdev->msi_enabled) { 326 switch (rdev->family) { 327 case CHIP_RS400: 328 case CHIP_RS480: 329 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 330 WREG32(RADEON_AIC_CNTL, msi_rearm); 331 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 332 break; 333 default: 334 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; 335 WREG32(RADEON_MSI_REARM_EN, msi_rearm); 336 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); 337 break; 338 } 339 } 340 return IRQ_HANDLED; 341 } 342 343 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 344 { 345 if (crtc == 0) 346 return RREG32(RADEON_CRTC_CRNT_FRAME); 347 else 348 return RREG32(RADEON_CRTC2_CRNT_FRAME); 349 } 350 351 void r100_fence_ring_emit(struct radeon_device *rdev, 352 struct radeon_fence *fence) 353 { 354 /* Who ever call radeon_fence_emit should call ring_lock and ask 355 * for enough space (today caller are ib schedule and buffer move) */ 356 /* Wait until IDLE & CLEAN */ 357 radeon_ring_write(rdev, PACKET0(0x1720, 0)); 358 radeon_ring_write(rdev, (1 << 16) | (1 << 17)); 359 /* Emit fence sequence & fire IRQ */ 360 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 361 radeon_ring_write(rdev, fence->seq); 362 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 363 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 364 } 365 366 int r100_wb_init(struct radeon_device *rdev) 367 { 368 int r; 369 370 if (rdev->wb.wb_obj == NULL) { 371 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, 372 RADEON_GEM_DOMAIN_GTT, 373 &rdev->wb.wb_obj); 374 if (r) { 375 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r); 376 return r; 377 } 378 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 379 if (unlikely(r != 0)) 380 return r; 381 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 382 &rdev->wb.gpu_addr); 383 if (r) { 384 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r); 385 radeon_bo_unreserve(rdev->wb.wb_obj); 386 return r; 387 } 388 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 389 radeon_bo_unreserve(rdev->wb.wb_obj); 390 if (r) { 391 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r); 392 return r; 393 } 394 } 395 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr); 396 WREG32(R_00070C_CP_RB_RPTR_ADDR, 397 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2)); 398 WREG32(R_000770_SCRATCH_UMSK, 0xff); 399 return 0; 400 } 401 402 void r100_wb_disable(struct radeon_device *rdev) 403 { 404 WREG32(R_000770_SCRATCH_UMSK, 0); 405 } 406 407 void r100_wb_fini(struct radeon_device *rdev) 408 { 409 int r; 410 411 r100_wb_disable(rdev); 412 if (rdev->wb.wb_obj) { 413 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 414 if (unlikely(r != 0)) { 415 dev_err(rdev->dev, "(%d) can't finish WB\n", r); 416 return; 417 } 418 radeon_bo_kunmap(rdev->wb.wb_obj); 419 radeon_bo_unpin(rdev->wb.wb_obj); 420 radeon_bo_unreserve(rdev->wb.wb_obj); 421 radeon_bo_unref(&rdev->wb.wb_obj); 422 rdev->wb.wb = NULL; 423 rdev->wb.wb_obj = NULL; 424 } 425 } 426 427 int r100_copy_blit(struct radeon_device *rdev, 428 uint64_t src_offset, 429 uint64_t dst_offset, 430 unsigned num_pages, 431 struct radeon_fence *fence) 432 { 433 uint32_t cur_pages; 434 uint32_t stride_bytes = PAGE_SIZE; 435 uint32_t pitch; 436 uint32_t stride_pixels; 437 unsigned ndw; 438 int num_loops; 439 int r = 0; 440 441 /* radeon limited to 16k stride */ 442 stride_bytes &= 0x3fff; 443 /* radeon pitch is /64 */ 444 pitch = stride_bytes / 64; 445 stride_pixels = stride_bytes / 4; 446 num_loops = DIV_ROUND_UP(num_pages, 8191); 447 448 /* Ask for enough room for blit + flush + fence */ 449 ndw = 64 + (10 * num_loops); 450 r = radeon_ring_lock(rdev, ndw); 451 if (r) { 452 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 453 return -EINVAL; 454 } 455 while (num_pages > 0) { 456 cur_pages = num_pages; 457 if (cur_pages > 8191) { 458 cur_pages = 8191; 459 } 460 num_pages -= cur_pages; 461 462 /* pages are in Y direction - height 463 page width in X direction - width */ 464 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); 465 radeon_ring_write(rdev, 466 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 467 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 468 RADEON_GMC_SRC_CLIPPING | 469 RADEON_GMC_DST_CLIPPING | 470 RADEON_GMC_BRUSH_NONE | 471 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 472 RADEON_GMC_SRC_DATATYPE_COLOR | 473 RADEON_ROP3_S | 474 RADEON_DP_SRC_SOURCE_MEMORY | 475 RADEON_GMC_CLR_CMP_CNTL_DIS | 476 RADEON_GMC_WR_MSK_DIS); 477 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); 478 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); 479 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 480 radeon_ring_write(rdev, 0); 481 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 482 radeon_ring_write(rdev, num_pages); 483 radeon_ring_write(rdev, num_pages); 484 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); 485 } 486 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 487 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); 488 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 489 radeon_ring_write(rdev, 490 RADEON_WAIT_2D_IDLECLEAN | 491 RADEON_WAIT_HOST_IDLECLEAN | 492 RADEON_WAIT_DMA_GUI_IDLE); 493 if (fence) { 494 r = radeon_fence_emit(rdev, fence); 495 } 496 radeon_ring_unlock_commit(rdev); 497 return r; 498 } 499 500 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 501 { 502 unsigned i; 503 u32 tmp; 504 505 for (i = 0; i < rdev->usec_timeout; i++) { 506 tmp = RREG32(R_000E40_RBBM_STATUS); 507 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 508 return 0; 509 } 510 udelay(1); 511 } 512 return -1; 513 } 514 515 void r100_ring_start(struct radeon_device *rdev) 516 { 517 int r; 518 519 r = radeon_ring_lock(rdev, 2); 520 if (r) { 521 return; 522 } 523 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 524 radeon_ring_write(rdev, 525 RADEON_ISYNC_ANY2D_IDLE3D | 526 RADEON_ISYNC_ANY3D_IDLE2D | 527 RADEON_ISYNC_WAIT_IDLEGUI | 528 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 529 radeon_ring_unlock_commit(rdev); 530 } 531 532 533 /* Load the microcode for the CP */ 534 static int r100_cp_init_microcode(struct radeon_device *rdev) 535 { 536 struct platform_device *pdev; 537 const char *fw_name = NULL; 538 int err; 539 540 DRM_DEBUG("\n"); 541 542 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 543 err = IS_ERR(pdev); 544 if (err) { 545 printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); 546 return -EINVAL; 547 } 548 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 549 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 550 (rdev->family == CHIP_RS200)) { 551 DRM_INFO("Loading R100 Microcode\n"); 552 fw_name = FIRMWARE_R100; 553 } else if ((rdev->family == CHIP_R200) || 554 (rdev->family == CHIP_RV250) || 555 (rdev->family == CHIP_RV280) || 556 (rdev->family == CHIP_RS300)) { 557 DRM_INFO("Loading R200 Microcode\n"); 558 fw_name = FIRMWARE_R200; 559 } else if ((rdev->family == CHIP_R300) || 560 (rdev->family == CHIP_R350) || 561 (rdev->family == CHIP_RV350) || 562 (rdev->family == CHIP_RV380) || 563 (rdev->family == CHIP_RS400) || 564 (rdev->family == CHIP_RS480)) { 565 DRM_INFO("Loading R300 Microcode\n"); 566 fw_name = FIRMWARE_R300; 567 } else if ((rdev->family == CHIP_R420) || 568 (rdev->family == CHIP_R423) || 569 (rdev->family == CHIP_RV410)) { 570 DRM_INFO("Loading R400 Microcode\n"); 571 fw_name = FIRMWARE_R420; 572 } else if ((rdev->family == CHIP_RS690) || 573 (rdev->family == CHIP_RS740)) { 574 DRM_INFO("Loading RS690/RS740 Microcode\n"); 575 fw_name = FIRMWARE_RS690; 576 } else if (rdev->family == CHIP_RS600) { 577 DRM_INFO("Loading RS600 Microcode\n"); 578 fw_name = FIRMWARE_RS600; 579 } else if ((rdev->family == CHIP_RV515) || 580 (rdev->family == CHIP_R520) || 581 (rdev->family == CHIP_RV530) || 582 (rdev->family == CHIP_R580) || 583 (rdev->family == CHIP_RV560) || 584 (rdev->family == CHIP_RV570)) { 585 DRM_INFO("Loading R500 Microcode\n"); 586 fw_name = FIRMWARE_R520; 587 } 588 589 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); 590 platform_device_unregister(pdev); 591 if (err) { 592 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", 593 fw_name); 594 } else if (rdev->me_fw->size % 8) { 595 printk(KERN_ERR 596 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 597 rdev->me_fw->size, fw_name); 598 err = -EINVAL; 599 release_firmware(rdev->me_fw); 600 rdev->me_fw = NULL; 601 } 602 return err; 603 } 604 605 static void r100_cp_load_microcode(struct radeon_device *rdev) 606 { 607 const __be32 *fw_data; 608 int i, size; 609 610 if (r100_gui_wait_for_idle(rdev)) { 611 printk(KERN_WARNING "Failed to wait GUI idle while " 612 "programming pipes. Bad things might happen.\n"); 613 } 614 615 if (rdev->me_fw) { 616 size = rdev->me_fw->size / 4; 617 fw_data = (const __be32 *)&rdev->me_fw->data[0]; 618 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 619 for (i = 0; i < size; i += 2) { 620 WREG32(RADEON_CP_ME_RAM_DATAH, 621 be32_to_cpup(&fw_data[i])); 622 WREG32(RADEON_CP_ME_RAM_DATAL, 623 be32_to_cpup(&fw_data[i + 1])); 624 } 625 } 626 } 627 628 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 629 { 630 unsigned rb_bufsz; 631 unsigned rb_blksz; 632 unsigned max_fetch; 633 unsigned pre_write_timer; 634 unsigned pre_write_limit; 635 unsigned indirect2_start; 636 unsigned indirect1_start; 637 uint32_t tmp; 638 int r; 639 640 if (r100_debugfs_cp_init(rdev)) { 641 DRM_ERROR("Failed to register debugfs file for CP !\n"); 642 } 643 /* Reset CP */ 644 tmp = RREG32(RADEON_CP_CSQ_STAT); 645 if ((tmp & (1 << 31))) { 646 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp); 647 WREG32(RADEON_CP_CSQ_MODE, 0); 648 WREG32(RADEON_CP_CSQ_CNTL, 0); 649 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP); 650 tmp = RREG32(RADEON_RBBM_SOFT_RESET); 651 mdelay(2); 652 WREG32(RADEON_RBBM_SOFT_RESET, 0); 653 tmp = RREG32(RADEON_RBBM_SOFT_RESET); 654 mdelay(2); 655 tmp = RREG32(RADEON_CP_CSQ_STAT); 656 if ((tmp & (1 << 31))) { 657 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp); 658 } 659 } else { 660 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp); 661 } 662 663 if (!rdev->me_fw) { 664 r = r100_cp_init_microcode(rdev); 665 if (r) { 666 DRM_ERROR("Failed to load firmware!\n"); 667 return r; 668 } 669 } 670 671 /* Align ring size */ 672 rb_bufsz = drm_order(ring_size / 8); 673 ring_size = (1 << (rb_bufsz + 1)) * 4; 674 r100_cp_load_microcode(rdev); 675 r = radeon_ring_init(rdev, ring_size); 676 if (r) { 677 return r; 678 } 679 /* Each time the cp read 1024 bytes (16 dword/quadword) update 680 * the rptr copy in system ram */ 681 rb_blksz = 9; 682 /* cp will read 128bytes at a time (4 dwords) */ 683 max_fetch = 1; 684 rdev->cp.align_mask = 16 - 1; 685 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 686 pre_write_timer = 64; 687 /* Force CP_RB_WPTR write if written more than one time before the 688 * delay expire 689 */ 690 pre_write_limit = 0; 691 /* Setup the cp cache like this (cache size is 96 dwords) : 692 * RING 0 to 15 693 * INDIRECT1 16 to 79 694 * INDIRECT2 80 to 95 695 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 696 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 697 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 698 * Idea being that most of the gpu cmd will be through indirect1 buffer 699 * so it gets the bigger cache. 700 */ 701 indirect2_start = 80; 702 indirect1_start = 16; 703 /* cp setup */ 704 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 705 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 706 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 707 REG_SET(RADEON_MAX_FETCH, max_fetch) | 708 RADEON_RB_NO_UPDATE); 709 #ifdef __BIG_ENDIAN 710 tmp |= RADEON_BUF_SWAP_32BIT; 711 #endif 712 WREG32(RADEON_CP_RB_CNTL, tmp); 713 714 /* Set ring address */ 715 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); 716 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); 717 /* Force read & write ptr to 0 */ 718 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 719 WREG32(RADEON_CP_RB_RPTR_WR, 0); 720 WREG32(RADEON_CP_RB_WPTR, 0); 721 WREG32(RADEON_CP_RB_CNTL, tmp); 722 udelay(10); 723 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 724 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); 725 /* Set cp mode to bus mastering & enable cp*/ 726 WREG32(RADEON_CP_CSQ_MODE, 727 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 728 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 729 WREG32(0x718, 0); 730 WREG32(0x744, 0x00004D4D); 731 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 732 radeon_ring_start(rdev); 733 r = radeon_ring_test(rdev); 734 if (r) { 735 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 736 return r; 737 } 738 rdev->cp.ready = true; 739 return 0; 740 } 741 742 void r100_cp_fini(struct radeon_device *rdev) 743 { 744 if (r100_cp_wait_for_idle(rdev)) { 745 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 746 } 747 /* Disable ring */ 748 r100_cp_disable(rdev); 749 radeon_ring_fini(rdev); 750 DRM_INFO("radeon: cp finalized\n"); 751 } 752 753 void r100_cp_disable(struct radeon_device *rdev) 754 { 755 /* Disable ring */ 756 rdev->cp.ready = false; 757 WREG32(RADEON_CP_CSQ_MODE, 0); 758 WREG32(RADEON_CP_CSQ_CNTL, 0); 759 if (r100_gui_wait_for_idle(rdev)) { 760 printk(KERN_WARNING "Failed to wait GUI idle while " 761 "programming pipes. Bad things might happen.\n"); 762 } 763 } 764 765 int r100_cp_reset(struct radeon_device *rdev) 766 { 767 uint32_t tmp; 768 bool reinit_cp; 769 int i; 770 771 reinit_cp = rdev->cp.ready; 772 rdev->cp.ready = false; 773 WREG32(RADEON_CP_CSQ_MODE, 0); 774 WREG32(RADEON_CP_CSQ_CNTL, 0); 775 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP); 776 (void)RREG32(RADEON_RBBM_SOFT_RESET); 777 udelay(200); 778 WREG32(RADEON_RBBM_SOFT_RESET, 0); 779 /* Wait to prevent race in RBBM_STATUS */ 780 mdelay(1); 781 for (i = 0; i < rdev->usec_timeout; i++) { 782 tmp = RREG32(RADEON_RBBM_STATUS); 783 if (!(tmp & (1 << 16))) { 784 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n", 785 tmp); 786 if (reinit_cp) { 787 return r100_cp_init(rdev, rdev->cp.ring_size); 788 } 789 return 0; 790 } 791 DRM_UDELAY(1); 792 } 793 tmp = RREG32(RADEON_RBBM_STATUS); 794 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp); 795 return -1; 796 } 797 798 void r100_cp_commit(struct radeon_device *rdev) 799 { 800 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 801 (void)RREG32(RADEON_CP_RB_WPTR); 802 } 803 804 805 /* 806 * CS functions 807 */ 808 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 809 struct radeon_cs_packet *pkt, 810 const unsigned *auth, unsigned n, 811 radeon_packet0_check_t check) 812 { 813 unsigned reg; 814 unsigned i, j, m; 815 unsigned idx; 816 int r; 817 818 idx = pkt->idx + 1; 819 reg = pkt->reg; 820 /* Check that register fall into register range 821 * determined by the number of entry (n) in the 822 * safe register bitmap. 823 */ 824 if (pkt->one_reg_wr) { 825 if ((reg >> 7) > n) { 826 return -EINVAL; 827 } 828 } else { 829 if (((reg + (pkt->count << 2)) >> 7) > n) { 830 return -EINVAL; 831 } 832 } 833 for (i = 0; i <= pkt->count; i++, idx++) { 834 j = (reg >> 7); 835 m = 1 << ((reg >> 2) & 31); 836 if (auth[j] & m) { 837 r = check(p, pkt, idx, reg); 838 if (r) { 839 return r; 840 } 841 } 842 if (pkt->one_reg_wr) { 843 if (!(auth[j] & m)) { 844 break; 845 } 846 } else { 847 reg += 4; 848 } 849 } 850 return 0; 851 } 852 853 void r100_cs_dump_packet(struct radeon_cs_parser *p, 854 struct radeon_cs_packet *pkt) 855 { 856 volatile uint32_t *ib; 857 unsigned i; 858 unsigned idx; 859 860 ib = p->ib->ptr; 861 idx = pkt->idx; 862 for (i = 0; i <= (pkt->count + 1); i++, idx++) { 863 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 864 } 865 } 866 867 /** 868 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet 869 * @parser: parser structure holding parsing context. 870 * @pkt: where to store packet informations 871 * 872 * Assume that chunk_ib_index is properly set. Will return -EINVAL 873 * if packet is bigger than remaining ib size. or if packets is unknown. 874 **/ 875 int r100_cs_packet_parse(struct radeon_cs_parser *p, 876 struct radeon_cs_packet *pkt, 877 unsigned idx) 878 { 879 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 880 uint32_t header; 881 882 if (idx >= ib_chunk->length_dw) { 883 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 884 idx, ib_chunk->length_dw); 885 return -EINVAL; 886 } 887 header = radeon_get_ib_value(p, idx); 888 pkt->idx = idx; 889 pkt->type = CP_PACKET_GET_TYPE(header); 890 pkt->count = CP_PACKET_GET_COUNT(header); 891 switch (pkt->type) { 892 case PACKET_TYPE0: 893 pkt->reg = CP_PACKET0_GET_REG(header); 894 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); 895 break; 896 case PACKET_TYPE3: 897 pkt->opcode = CP_PACKET3_GET_OPCODE(header); 898 break; 899 case PACKET_TYPE2: 900 pkt->count = -1; 901 break; 902 default: 903 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 904 return -EINVAL; 905 } 906 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 907 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 908 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 909 return -EINVAL; 910 } 911 return 0; 912 } 913 914 /** 915 * r100_cs_packet_next_vline() - parse userspace VLINE packet 916 * @parser: parser structure holding parsing context. 917 * 918 * Userspace sends a special sequence for VLINE waits. 919 * PACKET0 - VLINE_START_END + value 920 * PACKET0 - WAIT_UNTIL +_value 921 * RELOC (P3) - crtc_id in reloc. 922 * 923 * This function parses this and relocates the VLINE START END 924 * and WAIT UNTIL packets to the correct crtc. 925 * It also detects a switched off crtc and nulls out the 926 * wait in that case. 927 */ 928 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 929 { 930 struct drm_mode_object *obj; 931 struct drm_crtc *crtc; 932 struct radeon_crtc *radeon_crtc; 933 struct radeon_cs_packet p3reloc, waitreloc; 934 int crtc_id; 935 int r; 936 uint32_t header, h_idx, reg; 937 volatile uint32_t *ib; 938 939 ib = p->ib->ptr; 940 941 /* parse the wait until */ 942 r = r100_cs_packet_parse(p, &waitreloc, p->idx); 943 if (r) 944 return r; 945 946 /* check its a wait until and only 1 count */ 947 if (waitreloc.reg != RADEON_WAIT_UNTIL || 948 waitreloc.count != 0) { 949 DRM_ERROR("vline wait had illegal wait until segment\n"); 950 r = -EINVAL; 951 return r; 952 } 953 954 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 955 DRM_ERROR("vline wait had illegal wait until\n"); 956 r = -EINVAL; 957 return r; 958 } 959 960 /* jump over the NOP */ 961 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 962 if (r) 963 return r; 964 965 h_idx = p->idx - 2; 966 p->idx += waitreloc.count + 2; 967 p->idx += p3reloc.count + 2; 968 969 header = radeon_get_ib_value(p, h_idx); 970 crtc_id = radeon_get_ib_value(p, h_idx + 5); 971 reg = CP_PACKET0_GET_REG(header); 972 mutex_lock(&p->rdev->ddev->mode_config.mutex); 973 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 974 if (!obj) { 975 DRM_ERROR("cannot find crtc %d\n", crtc_id); 976 r = -EINVAL; 977 goto out; 978 } 979 crtc = obj_to_crtc(obj); 980 radeon_crtc = to_radeon_crtc(crtc); 981 crtc_id = radeon_crtc->crtc_id; 982 983 if (!crtc->enabled) { 984 /* if the CRTC isn't enabled - we need to nop out the wait until */ 985 ib[h_idx + 2] = PACKET2(0); 986 ib[h_idx + 3] = PACKET2(0); 987 } else if (crtc_id == 1) { 988 switch (reg) { 989 case AVIVO_D1MODE_VLINE_START_END: 990 header &= ~R300_CP_PACKET0_REG_MASK; 991 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 992 break; 993 case RADEON_CRTC_GUI_TRIG_VLINE: 994 header &= ~R300_CP_PACKET0_REG_MASK; 995 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 996 break; 997 default: 998 DRM_ERROR("unknown crtc reloc\n"); 999 r = -EINVAL; 1000 goto out; 1001 } 1002 ib[h_idx] = header; 1003 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1004 } 1005 out: 1006 mutex_unlock(&p->rdev->ddev->mode_config.mutex); 1007 return r; 1008 } 1009 1010 /** 1011 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 1012 * @parser: parser structure holding parsing context. 1013 * @data: pointer to relocation data 1014 * @offset_start: starting offset 1015 * @offset_mask: offset mask (to align start offset on) 1016 * @reloc: reloc informations 1017 * 1018 * Check next packet is relocation packet3, do bo validation and compute 1019 * GPU offset using the provided start. 1020 **/ 1021 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 1022 struct radeon_cs_reloc **cs_reloc) 1023 { 1024 struct radeon_cs_chunk *relocs_chunk; 1025 struct radeon_cs_packet p3reloc; 1026 unsigned idx; 1027 int r; 1028 1029 if (p->chunk_relocs_idx == -1) { 1030 DRM_ERROR("No relocation chunk !\n"); 1031 return -EINVAL; 1032 } 1033 *cs_reloc = NULL; 1034 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1035 r = r100_cs_packet_parse(p, &p3reloc, p->idx); 1036 if (r) { 1037 return r; 1038 } 1039 p->idx += p3reloc.count + 2; 1040 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1041 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1042 p3reloc.idx); 1043 r100_cs_dump_packet(p, &p3reloc); 1044 return -EINVAL; 1045 } 1046 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1047 if (idx >= relocs_chunk->length_dw) { 1048 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1049 idx, relocs_chunk->length_dw); 1050 r100_cs_dump_packet(p, &p3reloc); 1051 return -EINVAL; 1052 } 1053 /* FIXME: we assume reloc size is 4 dwords */ 1054 *cs_reloc = p->relocs_ptr[(idx / 4)]; 1055 return 0; 1056 } 1057 1058 static int r100_get_vtx_size(uint32_t vtx_fmt) 1059 { 1060 int vtx_size; 1061 vtx_size = 2; 1062 /* ordered according to bits in spec */ 1063 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1064 vtx_size++; 1065 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1066 vtx_size += 3; 1067 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1068 vtx_size++; 1069 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1070 vtx_size++; 1071 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1072 vtx_size += 3; 1073 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1074 vtx_size++; 1075 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1076 vtx_size++; 1077 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1078 vtx_size += 2; 1079 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1080 vtx_size += 2; 1081 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1082 vtx_size++; 1083 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1084 vtx_size += 2; 1085 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1086 vtx_size++; 1087 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1088 vtx_size += 2; 1089 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1090 vtx_size++; 1091 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1092 vtx_size++; 1093 /* blend weight */ 1094 if (vtx_fmt & (0x7 << 15)) 1095 vtx_size += (vtx_fmt >> 15) & 0x7; 1096 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1097 vtx_size += 3; 1098 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1099 vtx_size += 2; 1100 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1101 vtx_size++; 1102 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1103 vtx_size++; 1104 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1105 vtx_size++; 1106 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1107 vtx_size++; 1108 return vtx_size; 1109 } 1110 1111 static int r100_packet0_check(struct radeon_cs_parser *p, 1112 struct radeon_cs_packet *pkt, 1113 unsigned idx, unsigned reg) 1114 { 1115 struct radeon_cs_reloc *reloc; 1116 struct r100_cs_track *track; 1117 volatile uint32_t *ib; 1118 uint32_t tmp; 1119 int r; 1120 int i, face; 1121 u32 tile_flags = 0; 1122 u32 idx_value; 1123 1124 ib = p->ib->ptr; 1125 track = (struct r100_cs_track *)p->track; 1126 1127 idx_value = radeon_get_ib_value(p, idx); 1128 1129 switch (reg) { 1130 case RADEON_CRTC_GUI_TRIG_VLINE: 1131 r = r100_cs_packet_parse_vline(p); 1132 if (r) { 1133 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1134 idx, reg); 1135 r100_cs_dump_packet(p, pkt); 1136 return r; 1137 } 1138 break; 1139 /* FIXME: only allow PACKET3 blit? easier to check for out of 1140 * range access */ 1141 case RADEON_DST_PITCH_OFFSET: 1142 case RADEON_SRC_PITCH_OFFSET: 1143 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1144 if (r) 1145 return r; 1146 break; 1147 case RADEON_RB3D_DEPTHOFFSET: 1148 r = r100_cs_packet_next_reloc(p, &reloc); 1149 if (r) { 1150 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1151 idx, reg); 1152 r100_cs_dump_packet(p, pkt); 1153 return r; 1154 } 1155 track->zb.robj = reloc->robj; 1156 track->zb.offset = idx_value; 1157 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1158 break; 1159 case RADEON_RB3D_COLOROFFSET: 1160 r = r100_cs_packet_next_reloc(p, &reloc); 1161 if (r) { 1162 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1163 idx, reg); 1164 r100_cs_dump_packet(p, pkt); 1165 return r; 1166 } 1167 track->cb[0].robj = reloc->robj; 1168 track->cb[0].offset = idx_value; 1169 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1170 break; 1171 case RADEON_PP_TXOFFSET_0: 1172 case RADEON_PP_TXOFFSET_1: 1173 case RADEON_PP_TXOFFSET_2: 1174 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1175 r = r100_cs_packet_next_reloc(p, &reloc); 1176 if (r) { 1177 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1178 idx, reg); 1179 r100_cs_dump_packet(p, pkt); 1180 return r; 1181 } 1182 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1183 track->textures[i].robj = reloc->robj; 1184 break; 1185 case RADEON_PP_CUBIC_OFFSET_T0_0: 1186 case RADEON_PP_CUBIC_OFFSET_T0_1: 1187 case RADEON_PP_CUBIC_OFFSET_T0_2: 1188 case RADEON_PP_CUBIC_OFFSET_T0_3: 1189 case RADEON_PP_CUBIC_OFFSET_T0_4: 1190 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1191 r = r100_cs_packet_next_reloc(p, &reloc); 1192 if (r) { 1193 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1194 idx, reg); 1195 r100_cs_dump_packet(p, pkt); 1196 return r; 1197 } 1198 track->textures[0].cube_info[i].offset = idx_value; 1199 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1200 track->textures[0].cube_info[i].robj = reloc->robj; 1201 break; 1202 case RADEON_PP_CUBIC_OFFSET_T1_0: 1203 case RADEON_PP_CUBIC_OFFSET_T1_1: 1204 case RADEON_PP_CUBIC_OFFSET_T1_2: 1205 case RADEON_PP_CUBIC_OFFSET_T1_3: 1206 case RADEON_PP_CUBIC_OFFSET_T1_4: 1207 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1208 r = r100_cs_packet_next_reloc(p, &reloc); 1209 if (r) { 1210 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1211 idx, reg); 1212 r100_cs_dump_packet(p, pkt); 1213 return r; 1214 } 1215 track->textures[1].cube_info[i].offset = idx_value; 1216 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1217 track->textures[1].cube_info[i].robj = reloc->robj; 1218 break; 1219 case RADEON_PP_CUBIC_OFFSET_T2_0: 1220 case RADEON_PP_CUBIC_OFFSET_T2_1: 1221 case RADEON_PP_CUBIC_OFFSET_T2_2: 1222 case RADEON_PP_CUBIC_OFFSET_T2_3: 1223 case RADEON_PP_CUBIC_OFFSET_T2_4: 1224 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1225 r = r100_cs_packet_next_reloc(p, &reloc); 1226 if (r) { 1227 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1228 idx, reg); 1229 r100_cs_dump_packet(p, pkt); 1230 return r; 1231 } 1232 track->textures[2].cube_info[i].offset = idx_value; 1233 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1234 track->textures[2].cube_info[i].robj = reloc->robj; 1235 break; 1236 case RADEON_RE_WIDTH_HEIGHT: 1237 track->maxy = ((idx_value >> 16) & 0x7FF); 1238 break; 1239 case RADEON_RB3D_COLORPITCH: 1240 r = r100_cs_packet_next_reloc(p, &reloc); 1241 if (r) { 1242 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1243 idx, reg); 1244 r100_cs_dump_packet(p, pkt); 1245 return r; 1246 } 1247 1248 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1249 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1250 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1251 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1252 1253 tmp = idx_value & ~(0x7 << 16); 1254 tmp |= tile_flags; 1255 ib[idx] = tmp; 1256 1257 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1258 break; 1259 case RADEON_RB3D_DEPTHPITCH: 1260 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1261 break; 1262 case RADEON_RB3D_CNTL: 1263 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1264 case 7: 1265 case 8: 1266 case 9: 1267 case 11: 1268 case 12: 1269 track->cb[0].cpp = 1; 1270 break; 1271 case 3: 1272 case 4: 1273 case 15: 1274 track->cb[0].cpp = 2; 1275 break; 1276 case 6: 1277 track->cb[0].cpp = 4; 1278 break; 1279 default: 1280 DRM_ERROR("Invalid color buffer format (%d) !\n", 1281 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1282 return -EINVAL; 1283 } 1284 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1285 break; 1286 case RADEON_RB3D_ZSTENCILCNTL: 1287 switch (idx_value & 0xf) { 1288 case 0: 1289 track->zb.cpp = 2; 1290 break; 1291 case 2: 1292 case 3: 1293 case 4: 1294 case 5: 1295 case 9: 1296 case 11: 1297 track->zb.cpp = 4; 1298 break; 1299 default: 1300 break; 1301 } 1302 break; 1303 case RADEON_RB3D_ZPASS_ADDR: 1304 r = r100_cs_packet_next_reloc(p, &reloc); 1305 if (r) { 1306 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1307 idx, reg); 1308 r100_cs_dump_packet(p, pkt); 1309 return r; 1310 } 1311 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1312 break; 1313 case RADEON_PP_CNTL: 1314 { 1315 uint32_t temp = idx_value >> 4; 1316 for (i = 0; i < track->num_texture; i++) 1317 track->textures[i].enabled = !!(temp & (1 << i)); 1318 } 1319 break; 1320 case RADEON_SE_VF_CNTL: 1321 track->vap_vf_cntl = idx_value; 1322 break; 1323 case RADEON_SE_VTX_FMT: 1324 track->vtx_size = r100_get_vtx_size(idx_value); 1325 break; 1326 case RADEON_PP_TEX_SIZE_0: 1327 case RADEON_PP_TEX_SIZE_1: 1328 case RADEON_PP_TEX_SIZE_2: 1329 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1330 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1331 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1332 break; 1333 case RADEON_PP_TEX_PITCH_0: 1334 case RADEON_PP_TEX_PITCH_1: 1335 case RADEON_PP_TEX_PITCH_2: 1336 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1337 track->textures[i].pitch = idx_value + 32; 1338 break; 1339 case RADEON_PP_TXFILTER_0: 1340 case RADEON_PP_TXFILTER_1: 1341 case RADEON_PP_TXFILTER_2: 1342 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1343 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1344 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1345 tmp = (idx_value >> 23) & 0x7; 1346 if (tmp == 2 || tmp == 6) 1347 track->textures[i].roundup_w = false; 1348 tmp = (idx_value >> 27) & 0x7; 1349 if (tmp == 2 || tmp == 6) 1350 track->textures[i].roundup_h = false; 1351 break; 1352 case RADEON_PP_TXFORMAT_0: 1353 case RADEON_PP_TXFORMAT_1: 1354 case RADEON_PP_TXFORMAT_2: 1355 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1356 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1357 track->textures[i].use_pitch = 1; 1358 } else { 1359 track->textures[i].use_pitch = 0; 1360 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1361 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1362 } 1363 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1364 track->textures[i].tex_coord_type = 2; 1365 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1366 case RADEON_TXFORMAT_I8: 1367 case RADEON_TXFORMAT_RGB332: 1368 case RADEON_TXFORMAT_Y8: 1369 track->textures[i].cpp = 1; 1370 break; 1371 case RADEON_TXFORMAT_AI88: 1372 case RADEON_TXFORMAT_ARGB1555: 1373 case RADEON_TXFORMAT_RGB565: 1374 case RADEON_TXFORMAT_ARGB4444: 1375 case RADEON_TXFORMAT_VYUY422: 1376 case RADEON_TXFORMAT_YVYU422: 1377 case RADEON_TXFORMAT_DXT1: 1378 case RADEON_TXFORMAT_SHADOW16: 1379 case RADEON_TXFORMAT_LDUDV655: 1380 case RADEON_TXFORMAT_DUDV88: 1381 track->textures[i].cpp = 2; 1382 break; 1383 case RADEON_TXFORMAT_ARGB8888: 1384 case RADEON_TXFORMAT_RGBA8888: 1385 case RADEON_TXFORMAT_DXT23: 1386 case RADEON_TXFORMAT_DXT45: 1387 case RADEON_TXFORMAT_SHADOW32: 1388 case RADEON_TXFORMAT_LDUDUV8888: 1389 track->textures[i].cpp = 4; 1390 break; 1391 } 1392 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1393 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1394 break; 1395 case RADEON_PP_CUBIC_FACES_0: 1396 case RADEON_PP_CUBIC_FACES_1: 1397 case RADEON_PP_CUBIC_FACES_2: 1398 tmp = idx_value; 1399 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1400 for (face = 0; face < 4; face++) { 1401 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1402 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1403 } 1404 break; 1405 default: 1406 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1407 reg, idx); 1408 return -EINVAL; 1409 } 1410 return 0; 1411 } 1412 1413 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1414 struct radeon_cs_packet *pkt, 1415 struct radeon_bo *robj) 1416 { 1417 unsigned idx; 1418 u32 value; 1419 idx = pkt->idx + 1; 1420 value = radeon_get_ib_value(p, idx + 2); 1421 if ((value + 1) > radeon_bo_size(robj)) { 1422 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1423 "(need %u have %lu) !\n", 1424 value + 1, 1425 radeon_bo_size(robj)); 1426 return -EINVAL; 1427 } 1428 return 0; 1429 } 1430 1431 static int r100_packet3_check(struct radeon_cs_parser *p, 1432 struct radeon_cs_packet *pkt) 1433 { 1434 struct radeon_cs_reloc *reloc; 1435 struct r100_cs_track *track; 1436 unsigned idx; 1437 volatile uint32_t *ib; 1438 int r; 1439 1440 ib = p->ib->ptr; 1441 idx = pkt->idx + 1; 1442 track = (struct r100_cs_track *)p->track; 1443 switch (pkt->opcode) { 1444 case PACKET3_3D_LOAD_VBPNTR: 1445 r = r100_packet3_load_vbpntr(p, pkt, idx); 1446 if (r) 1447 return r; 1448 break; 1449 case PACKET3_INDX_BUFFER: 1450 r = r100_cs_packet_next_reloc(p, &reloc); 1451 if (r) { 1452 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1453 r100_cs_dump_packet(p, pkt); 1454 return r; 1455 } 1456 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1457 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1458 if (r) { 1459 return r; 1460 } 1461 break; 1462 case 0x23: 1463 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1464 r = r100_cs_packet_next_reloc(p, &reloc); 1465 if (r) { 1466 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1467 r100_cs_dump_packet(p, pkt); 1468 return r; 1469 } 1470 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1471 track->num_arrays = 1; 1472 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1473 1474 track->arrays[0].robj = reloc->robj; 1475 track->arrays[0].esize = track->vtx_size; 1476 1477 track->max_indx = radeon_get_ib_value(p, idx+1); 1478 1479 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 1480 track->immd_dwords = pkt->count - 1; 1481 r = r100_cs_track_check(p->rdev, track); 1482 if (r) 1483 return r; 1484 break; 1485 case PACKET3_3D_DRAW_IMMD: 1486 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1487 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1488 return -EINVAL; 1489 } 1490 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1491 track->immd_dwords = pkt->count - 1; 1492 r = r100_cs_track_check(p->rdev, track); 1493 if (r) 1494 return r; 1495 break; 1496 /* triggers drawing using in-packet vertex data */ 1497 case PACKET3_3D_DRAW_IMMD_2: 1498 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1499 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1500 return -EINVAL; 1501 } 1502 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1503 track->immd_dwords = pkt->count; 1504 r = r100_cs_track_check(p->rdev, track); 1505 if (r) 1506 return r; 1507 break; 1508 /* triggers drawing using in-packet vertex data */ 1509 case PACKET3_3D_DRAW_VBUF_2: 1510 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1511 r = r100_cs_track_check(p->rdev, track); 1512 if (r) 1513 return r; 1514 break; 1515 /* triggers drawing of vertex buffers setup elsewhere */ 1516 case PACKET3_3D_DRAW_INDX_2: 1517 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1518 r = r100_cs_track_check(p->rdev, track); 1519 if (r) 1520 return r; 1521 break; 1522 /* triggers drawing using indices to vertex buffer */ 1523 case PACKET3_3D_DRAW_VBUF: 1524 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1525 r = r100_cs_track_check(p->rdev, track); 1526 if (r) 1527 return r; 1528 break; 1529 /* triggers drawing of vertex buffers setup elsewhere */ 1530 case PACKET3_3D_DRAW_INDX: 1531 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1532 r = r100_cs_track_check(p->rdev, track); 1533 if (r) 1534 return r; 1535 break; 1536 /* triggers drawing using indices to vertex buffer */ 1537 case PACKET3_NOP: 1538 break; 1539 default: 1540 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1541 return -EINVAL; 1542 } 1543 return 0; 1544 } 1545 1546 int r100_cs_parse(struct radeon_cs_parser *p) 1547 { 1548 struct radeon_cs_packet pkt; 1549 struct r100_cs_track *track; 1550 int r; 1551 1552 track = kzalloc(sizeof(*track), GFP_KERNEL); 1553 r100_cs_track_clear(p->rdev, track); 1554 p->track = track; 1555 do { 1556 r = r100_cs_packet_parse(p, &pkt, p->idx); 1557 if (r) { 1558 return r; 1559 } 1560 p->idx += pkt.count + 2; 1561 switch (pkt.type) { 1562 case PACKET_TYPE0: 1563 if (p->rdev->family >= CHIP_R200) 1564 r = r100_cs_parse_packet0(p, &pkt, 1565 p->rdev->config.r100.reg_safe_bm, 1566 p->rdev->config.r100.reg_safe_bm_size, 1567 &r200_packet0_check); 1568 else 1569 r = r100_cs_parse_packet0(p, &pkt, 1570 p->rdev->config.r100.reg_safe_bm, 1571 p->rdev->config.r100.reg_safe_bm_size, 1572 &r100_packet0_check); 1573 break; 1574 case PACKET_TYPE2: 1575 break; 1576 case PACKET_TYPE3: 1577 r = r100_packet3_check(p, &pkt); 1578 break; 1579 default: 1580 DRM_ERROR("Unknown packet type %d !\n", 1581 pkt.type); 1582 return -EINVAL; 1583 } 1584 if (r) { 1585 return r; 1586 } 1587 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1588 return 0; 1589 } 1590 1591 1592 /* 1593 * Global GPU functions 1594 */ 1595 void r100_errata(struct radeon_device *rdev) 1596 { 1597 rdev->pll_errata = 0; 1598 1599 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 1600 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 1601 } 1602 1603 if (rdev->family == CHIP_RV100 || 1604 rdev->family == CHIP_RS100 || 1605 rdev->family == CHIP_RS200) { 1606 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 1607 } 1608 } 1609 1610 /* Wait for vertical sync on primary CRTC */ 1611 void r100_gpu_wait_for_vsync(struct radeon_device *rdev) 1612 { 1613 uint32_t crtc_gen_cntl, tmp; 1614 int i; 1615 1616 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 1617 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 1618 !(crtc_gen_cntl & RADEON_CRTC_EN)) { 1619 return; 1620 } 1621 /* Clear the CRTC_VBLANK_SAVE bit */ 1622 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 1623 for (i = 0; i < rdev->usec_timeout; i++) { 1624 tmp = RREG32(RADEON_CRTC_STATUS); 1625 if (tmp & RADEON_CRTC_VBLANK_SAVE) { 1626 return; 1627 } 1628 DRM_UDELAY(1); 1629 } 1630 } 1631 1632 /* Wait for vertical sync on secondary CRTC */ 1633 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) 1634 { 1635 uint32_t crtc2_gen_cntl, tmp; 1636 int i; 1637 1638 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1639 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 1640 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 1641 return; 1642 1643 /* Clear the CRTC_VBLANK_SAVE bit */ 1644 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 1645 for (i = 0; i < rdev->usec_timeout; i++) { 1646 tmp = RREG32(RADEON_CRTC2_STATUS); 1647 if (tmp & RADEON_CRTC2_VBLANK_SAVE) { 1648 return; 1649 } 1650 DRM_UDELAY(1); 1651 } 1652 } 1653 1654 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 1655 { 1656 unsigned i; 1657 uint32_t tmp; 1658 1659 for (i = 0; i < rdev->usec_timeout; i++) { 1660 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 1661 if (tmp >= n) { 1662 return 0; 1663 } 1664 DRM_UDELAY(1); 1665 } 1666 return -1; 1667 } 1668 1669 int r100_gui_wait_for_idle(struct radeon_device *rdev) 1670 { 1671 unsigned i; 1672 uint32_t tmp; 1673 1674 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 1675 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 1676 " Bad things might happen.\n"); 1677 } 1678 for (i = 0; i < rdev->usec_timeout; i++) { 1679 tmp = RREG32(RADEON_RBBM_STATUS); 1680 if (!(tmp & (1 << 31))) { 1681 return 0; 1682 } 1683 DRM_UDELAY(1); 1684 } 1685 return -1; 1686 } 1687 1688 int r100_mc_wait_for_idle(struct radeon_device *rdev) 1689 { 1690 unsigned i; 1691 uint32_t tmp; 1692 1693 for (i = 0; i < rdev->usec_timeout; i++) { 1694 /* read MC_STATUS */ 1695 tmp = RREG32(0x0150); 1696 if (tmp & (1 << 2)) { 1697 return 0; 1698 } 1699 DRM_UDELAY(1); 1700 } 1701 return -1; 1702 } 1703 1704 void r100_gpu_init(struct radeon_device *rdev) 1705 { 1706 /* TODO: anythings to do here ? pipes ? */ 1707 r100_hdp_reset(rdev); 1708 } 1709 1710 void r100_hdp_flush(struct radeon_device *rdev) 1711 { 1712 u32 tmp; 1713 tmp = RREG32(RADEON_HOST_PATH_CNTL); 1714 tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE; 1715 WREG32(RADEON_HOST_PATH_CNTL, tmp); 1716 } 1717 1718 void r100_hdp_reset(struct radeon_device *rdev) 1719 { 1720 uint32_t tmp; 1721 1722 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL; 1723 tmp |= (7 << 28); 1724 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); 1725 (void)RREG32(RADEON_HOST_PATH_CNTL); 1726 udelay(200); 1727 WREG32(RADEON_RBBM_SOFT_RESET, 0); 1728 WREG32(RADEON_HOST_PATH_CNTL, tmp); 1729 (void)RREG32(RADEON_HOST_PATH_CNTL); 1730 } 1731 1732 int r100_rb2d_reset(struct radeon_device *rdev) 1733 { 1734 uint32_t tmp; 1735 int i; 1736 1737 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2); 1738 (void)RREG32(RADEON_RBBM_SOFT_RESET); 1739 udelay(200); 1740 WREG32(RADEON_RBBM_SOFT_RESET, 0); 1741 /* Wait to prevent race in RBBM_STATUS */ 1742 mdelay(1); 1743 for (i = 0; i < rdev->usec_timeout; i++) { 1744 tmp = RREG32(RADEON_RBBM_STATUS); 1745 if (!(tmp & (1 << 26))) { 1746 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n", 1747 tmp); 1748 return 0; 1749 } 1750 DRM_UDELAY(1); 1751 } 1752 tmp = RREG32(RADEON_RBBM_STATUS); 1753 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp); 1754 return -1; 1755 } 1756 1757 int r100_gpu_reset(struct radeon_device *rdev) 1758 { 1759 uint32_t status; 1760 1761 /* reset order likely matter */ 1762 status = RREG32(RADEON_RBBM_STATUS); 1763 /* reset HDP */ 1764 r100_hdp_reset(rdev); 1765 /* reset rb2d */ 1766 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { 1767 r100_rb2d_reset(rdev); 1768 } 1769 /* TODO: reset 3D engine */ 1770 /* reset CP */ 1771 status = RREG32(RADEON_RBBM_STATUS); 1772 if (status & (1 << 16)) { 1773 r100_cp_reset(rdev); 1774 } 1775 /* Check if GPU is idle */ 1776 status = RREG32(RADEON_RBBM_STATUS); 1777 if (status & (1 << 31)) { 1778 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); 1779 return -1; 1780 } 1781 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); 1782 return 0; 1783 } 1784 1785 void r100_set_common_regs(struct radeon_device *rdev) 1786 { 1787 /* set these so they don't interfere with anything */ 1788 WREG32(RADEON_OV0_SCALE_CNTL, 0); 1789 WREG32(RADEON_SUBPIC_CNTL, 0); 1790 WREG32(RADEON_VIPH_CONTROL, 0); 1791 WREG32(RADEON_I2C_CNTL_1, 0); 1792 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 1793 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 1794 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 1795 } 1796 1797 /* 1798 * VRAM info 1799 */ 1800 static void r100_vram_get_type(struct radeon_device *rdev) 1801 { 1802 uint32_t tmp; 1803 1804 rdev->mc.vram_is_ddr = false; 1805 if (rdev->flags & RADEON_IS_IGP) 1806 rdev->mc.vram_is_ddr = true; 1807 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 1808 rdev->mc.vram_is_ddr = true; 1809 if ((rdev->family == CHIP_RV100) || 1810 (rdev->family == CHIP_RS100) || 1811 (rdev->family == CHIP_RS200)) { 1812 tmp = RREG32(RADEON_MEM_CNTL); 1813 if (tmp & RV100_HALF_MODE) { 1814 rdev->mc.vram_width = 32; 1815 } else { 1816 rdev->mc.vram_width = 64; 1817 } 1818 if (rdev->flags & RADEON_SINGLE_CRTC) { 1819 rdev->mc.vram_width /= 4; 1820 rdev->mc.vram_is_ddr = true; 1821 } 1822 } else if (rdev->family <= CHIP_RV280) { 1823 tmp = RREG32(RADEON_MEM_CNTL); 1824 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 1825 rdev->mc.vram_width = 128; 1826 } else { 1827 rdev->mc.vram_width = 64; 1828 } 1829 } else { 1830 /* newer IGPs */ 1831 rdev->mc.vram_width = 128; 1832 } 1833 } 1834 1835 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 1836 { 1837 u32 aper_size; 1838 u8 byte; 1839 1840 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 1841 1842 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 1843 * that is has the 2nd generation multifunction PCI interface 1844 */ 1845 if (rdev->family == CHIP_RV280 || 1846 rdev->family >= CHIP_RV350) { 1847 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 1848 ~RADEON_HDP_APER_CNTL); 1849 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 1850 return aper_size * 2; 1851 } 1852 1853 /* Older cards have all sorts of funny issues to deal with. First 1854 * check if it's a multifunction card by reading the PCI config 1855 * header type... Limit those to one aperture size 1856 */ 1857 pci_read_config_byte(rdev->pdev, 0xe, &byte); 1858 if (byte & 0x80) { 1859 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 1860 DRM_INFO("Limiting VRAM to one aperture\n"); 1861 return aper_size; 1862 } 1863 1864 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 1865 * have set it up. We don't write this as it's broken on some ASICs but 1866 * we expect the BIOS to have done the right thing (might be too optimistic...) 1867 */ 1868 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 1869 return aper_size * 2; 1870 return aper_size; 1871 } 1872 1873 void r100_vram_init_sizes(struct radeon_device *rdev) 1874 { 1875 u64 config_aper_size; 1876 u32 accessible; 1877 1878 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 1879 1880 if (rdev->flags & RADEON_IS_IGP) { 1881 uint32_t tom; 1882 /* read NB_TOM to get the amount of ram stolen for the GPU */ 1883 tom = RREG32(RADEON_NB_TOM); 1884 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 1885 /* for IGPs we need to keep VRAM where it was put by the BIOS */ 1886 rdev->mc.vram_location = (tom & 0xffff) << 16; 1887 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 1888 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 1889 } else { 1890 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 1891 /* Some production boards of m6 will report 0 1892 * if it's 8 MB 1893 */ 1894 if (rdev->mc.real_vram_size == 0) { 1895 rdev->mc.real_vram_size = 8192 * 1024; 1896 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 1897 } 1898 /* let driver place VRAM */ 1899 rdev->mc.vram_location = 0xFFFFFFFFUL; 1900 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 1901 * Novell bug 204882 + along with lots of ubuntu ones */ 1902 if (config_aper_size > rdev->mc.real_vram_size) 1903 rdev->mc.mc_vram_size = config_aper_size; 1904 else 1905 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 1906 } 1907 1908 /* work out accessible VRAM */ 1909 accessible = r100_get_accessible_vram(rdev); 1910 1911 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 1912 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 1913 1914 if (accessible > rdev->mc.aper_size) 1915 accessible = rdev->mc.aper_size; 1916 1917 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) 1918 rdev->mc.mc_vram_size = rdev->mc.aper_size; 1919 1920 if (rdev->mc.real_vram_size > rdev->mc.aper_size) 1921 rdev->mc.real_vram_size = rdev->mc.aper_size; 1922 } 1923 1924 void r100_vga_set_state(struct radeon_device *rdev, bool state) 1925 { 1926 uint32_t temp; 1927 1928 temp = RREG32(RADEON_CONFIG_CNTL); 1929 if (state == false) { 1930 temp &= ~(1<<8); 1931 temp |= (1<<9); 1932 } else { 1933 temp &= ~(1<<9); 1934 } 1935 WREG32(RADEON_CONFIG_CNTL, temp); 1936 } 1937 1938 void r100_vram_info(struct radeon_device *rdev) 1939 { 1940 r100_vram_get_type(rdev); 1941 1942 r100_vram_init_sizes(rdev); 1943 } 1944 1945 1946 /* 1947 * Indirect registers accessor 1948 */ 1949 void r100_pll_errata_after_index(struct radeon_device *rdev) 1950 { 1951 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) { 1952 return; 1953 } 1954 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 1955 (void)RREG32(RADEON_CRTC_GEN_CNTL); 1956 } 1957 1958 static void r100_pll_errata_after_data(struct radeon_device *rdev) 1959 { 1960 /* This workarounds is necessary on RV100, RS100 and RS200 chips 1961 * or the chip could hang on a subsequent access 1962 */ 1963 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 1964 udelay(5000); 1965 } 1966 1967 /* This function is required to workaround a hardware bug in some (all?) 1968 * revisions of the R300. This workaround should be called after every 1969 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 1970 * may not be correct. 1971 */ 1972 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 1973 uint32_t save, tmp; 1974 1975 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 1976 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 1977 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 1978 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 1979 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 1980 } 1981 } 1982 1983 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 1984 { 1985 uint32_t data; 1986 1987 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 1988 r100_pll_errata_after_index(rdev); 1989 data = RREG32(RADEON_CLOCK_CNTL_DATA); 1990 r100_pll_errata_after_data(rdev); 1991 return data; 1992 } 1993 1994 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1995 { 1996 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 1997 r100_pll_errata_after_index(rdev); 1998 WREG32(RADEON_CLOCK_CNTL_DATA, v); 1999 r100_pll_errata_after_data(rdev); 2000 } 2001 2002 void r100_set_safe_registers(struct radeon_device *rdev) 2003 { 2004 if (ASIC_IS_RN50(rdev)) { 2005 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2006 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2007 } else if (rdev->family < CHIP_R200) { 2008 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2009 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2010 } else { 2011 r200_set_safe_registers(rdev); 2012 } 2013 } 2014 2015 /* 2016 * Debugfs info 2017 */ 2018 #if defined(CONFIG_DEBUG_FS) 2019 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 2020 { 2021 struct drm_info_node *node = (struct drm_info_node *) m->private; 2022 struct drm_device *dev = node->minor->dev; 2023 struct radeon_device *rdev = dev->dev_private; 2024 uint32_t reg, value; 2025 unsigned i; 2026 2027 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 2028 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 2029 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2030 for (i = 0; i < 64; i++) { 2031 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 2032 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 2033 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 2034 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 2035 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 2036 } 2037 return 0; 2038 } 2039 2040 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 2041 { 2042 struct drm_info_node *node = (struct drm_info_node *) m->private; 2043 struct drm_device *dev = node->minor->dev; 2044 struct radeon_device *rdev = dev->dev_private; 2045 uint32_t rdp, wdp; 2046 unsigned count, i, j; 2047 2048 radeon_ring_free_size(rdev); 2049 rdp = RREG32(RADEON_CP_RB_RPTR); 2050 wdp = RREG32(RADEON_CP_RB_WPTR); 2051 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; 2052 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2053 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2054 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2055 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); 2056 seq_printf(m, "%u dwords in ring\n", count); 2057 for (j = 0; j <= count; j++) { 2058 i = (rdp + j) & rdev->cp.ptr_mask; 2059 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); 2060 } 2061 return 0; 2062 } 2063 2064 2065 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 2066 { 2067 struct drm_info_node *node = (struct drm_info_node *) m->private; 2068 struct drm_device *dev = node->minor->dev; 2069 struct radeon_device *rdev = dev->dev_private; 2070 uint32_t csq_stat, csq2_stat, tmp; 2071 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 2072 unsigned i; 2073 2074 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2075 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 2076 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 2077 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 2078 r_rptr = (csq_stat >> 0) & 0x3ff; 2079 r_wptr = (csq_stat >> 10) & 0x3ff; 2080 ib1_rptr = (csq_stat >> 20) & 0x3ff; 2081 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 2082 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 2083 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 2084 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 2085 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 2086 seq_printf(m, "Ring rptr %u\n", r_rptr); 2087 seq_printf(m, "Ring wptr %u\n", r_wptr); 2088 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 2089 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 2090 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 2091 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 2092 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 2093 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 2094 seq_printf(m, "Ring fifo:\n"); 2095 for (i = 0; i < 256; i++) { 2096 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2097 tmp = RREG32(RADEON_CP_CSQ_DATA); 2098 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 2099 } 2100 seq_printf(m, "Indirect1 fifo:\n"); 2101 for (i = 256; i <= 512; i++) { 2102 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2103 tmp = RREG32(RADEON_CP_CSQ_DATA); 2104 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 2105 } 2106 seq_printf(m, "Indirect2 fifo:\n"); 2107 for (i = 640; i < ib1_wptr; i++) { 2108 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 2109 tmp = RREG32(RADEON_CP_CSQ_DATA); 2110 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 2111 } 2112 return 0; 2113 } 2114 2115 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 2116 { 2117 struct drm_info_node *node = (struct drm_info_node *) m->private; 2118 struct drm_device *dev = node->minor->dev; 2119 struct radeon_device *rdev = dev->dev_private; 2120 uint32_t tmp; 2121 2122 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 2123 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 2124 tmp = RREG32(RADEON_MC_FB_LOCATION); 2125 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 2126 tmp = RREG32(RADEON_BUS_CNTL); 2127 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 2128 tmp = RREG32(RADEON_MC_AGP_LOCATION); 2129 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 2130 tmp = RREG32(RADEON_AGP_BASE); 2131 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 2132 tmp = RREG32(RADEON_HOST_PATH_CNTL); 2133 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 2134 tmp = RREG32(0x01D0); 2135 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 2136 tmp = RREG32(RADEON_AIC_LO_ADDR); 2137 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 2138 tmp = RREG32(RADEON_AIC_HI_ADDR); 2139 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 2140 tmp = RREG32(0x01E4); 2141 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 2142 return 0; 2143 } 2144 2145 static struct drm_info_list r100_debugfs_rbbm_list[] = { 2146 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 2147 }; 2148 2149 static struct drm_info_list r100_debugfs_cp_list[] = { 2150 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 2151 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 2152 }; 2153 2154 static struct drm_info_list r100_debugfs_mc_info_list[] = { 2155 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 2156 }; 2157 #endif 2158 2159 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 2160 { 2161 #if defined(CONFIG_DEBUG_FS) 2162 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 2163 #else 2164 return 0; 2165 #endif 2166 } 2167 2168 int r100_debugfs_cp_init(struct radeon_device *rdev) 2169 { 2170 #if defined(CONFIG_DEBUG_FS) 2171 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 2172 #else 2173 return 0; 2174 #endif 2175 } 2176 2177 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 2178 { 2179 #if defined(CONFIG_DEBUG_FS) 2180 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 2181 #else 2182 return 0; 2183 #endif 2184 } 2185 2186 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 2187 uint32_t tiling_flags, uint32_t pitch, 2188 uint32_t offset, uint32_t obj_size) 2189 { 2190 int surf_index = reg * 16; 2191 int flags = 0; 2192 2193 /* r100/r200 divide by 16 */ 2194 if (rdev->family < CHIP_R300) 2195 flags = pitch / 16; 2196 else 2197 flags = pitch / 8; 2198 2199 if (rdev->family <= CHIP_RS200) { 2200 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2201 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 2202 flags |= RADEON_SURF_TILE_COLOR_BOTH; 2203 if (tiling_flags & RADEON_TILING_MACRO) 2204 flags |= RADEON_SURF_TILE_COLOR_MACRO; 2205 } else if (rdev->family <= CHIP_RV280) { 2206 if (tiling_flags & (RADEON_TILING_MACRO)) 2207 flags |= R200_SURF_TILE_COLOR_MACRO; 2208 if (tiling_flags & RADEON_TILING_MICRO) 2209 flags |= R200_SURF_TILE_COLOR_MICRO; 2210 } else { 2211 if (tiling_flags & RADEON_TILING_MACRO) 2212 flags |= R300_SURF_TILE_MACRO; 2213 if (tiling_flags & RADEON_TILING_MICRO) 2214 flags |= R300_SURF_TILE_MICRO; 2215 } 2216 2217 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 2218 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 2219 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 2220 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 2221 2222 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 2223 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 2224 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 2225 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 2226 return 0; 2227 } 2228 2229 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 2230 { 2231 int surf_index = reg * 16; 2232 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 2233 } 2234 2235 void r100_bandwidth_update(struct radeon_device *rdev) 2236 { 2237 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 2238 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 2239 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 2240 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 2241 fixed20_12 memtcas_ff[8] = { 2242 fixed_init(1), 2243 fixed_init(2), 2244 fixed_init(3), 2245 fixed_init(0), 2246 fixed_init_half(1), 2247 fixed_init_half(2), 2248 fixed_init(0), 2249 }; 2250 fixed20_12 memtcas_rs480_ff[8] = { 2251 fixed_init(0), 2252 fixed_init(1), 2253 fixed_init(2), 2254 fixed_init(3), 2255 fixed_init(0), 2256 fixed_init_half(1), 2257 fixed_init_half(2), 2258 fixed_init_half(3), 2259 }; 2260 fixed20_12 memtcas2_ff[8] = { 2261 fixed_init(0), 2262 fixed_init(1), 2263 fixed_init(2), 2264 fixed_init(3), 2265 fixed_init(4), 2266 fixed_init(5), 2267 fixed_init(6), 2268 fixed_init(7), 2269 }; 2270 fixed20_12 memtrbs[8] = { 2271 fixed_init(1), 2272 fixed_init_half(1), 2273 fixed_init(2), 2274 fixed_init_half(2), 2275 fixed_init(3), 2276 fixed_init_half(3), 2277 fixed_init(4), 2278 fixed_init_half(4) 2279 }; 2280 fixed20_12 memtrbs_r4xx[8] = { 2281 fixed_init(4), 2282 fixed_init(5), 2283 fixed_init(6), 2284 fixed_init(7), 2285 fixed_init(8), 2286 fixed_init(9), 2287 fixed_init(10), 2288 fixed_init(11) 2289 }; 2290 fixed20_12 min_mem_eff; 2291 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 2292 fixed20_12 cur_latency_mclk, cur_latency_sclk; 2293 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 2294 disp_drain_rate2, read_return_rate; 2295 fixed20_12 time_disp1_drop_priority; 2296 int c; 2297 int cur_size = 16; /* in octawords */ 2298 int critical_point = 0, critical_point2; 2299 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 2300 int stop_req, max_stop_req; 2301 struct drm_display_mode *mode1 = NULL; 2302 struct drm_display_mode *mode2 = NULL; 2303 uint32_t pixel_bytes1 = 0; 2304 uint32_t pixel_bytes2 = 0; 2305 2306 if (rdev->mode_info.crtcs[0]->base.enabled) { 2307 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2308 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2309 } 2310 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 2311 if (rdev->mode_info.crtcs[1]->base.enabled) { 2312 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 2313 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; 2314 } 2315 } 2316 2317 min_mem_eff.full = rfixed_const_8(0); 2318 /* get modes */ 2319 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 2320 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 2321 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 2322 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 2323 /* check crtc enables */ 2324 if (mode2) 2325 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 2326 if (mode1) 2327 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 2328 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 2329 } 2330 2331 /* 2332 * determine is there is enough bw for current mode 2333 */ 2334 mclk_ff.full = rfixed_const(rdev->clock.default_mclk); 2335 temp_ff.full = rfixed_const(100); 2336 mclk_ff.full = rfixed_div(mclk_ff, temp_ff); 2337 sclk_ff.full = rfixed_const(rdev->clock.default_sclk); 2338 sclk_ff.full = rfixed_div(sclk_ff, temp_ff); 2339 2340 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 2341 temp_ff.full = rfixed_const(temp); 2342 mem_bw.full = rfixed_mul(mclk_ff, temp_ff); 2343 2344 pix_clk.full = 0; 2345 pix_clk2.full = 0; 2346 peak_disp_bw.full = 0; 2347 if (mode1) { 2348 temp_ff.full = rfixed_const(1000); 2349 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ 2350 pix_clk.full = rfixed_div(pix_clk, temp_ff); 2351 temp_ff.full = rfixed_const(pixel_bytes1); 2352 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); 2353 } 2354 if (mode2) { 2355 temp_ff.full = rfixed_const(1000); 2356 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ 2357 pix_clk2.full = rfixed_div(pix_clk2, temp_ff); 2358 temp_ff.full = rfixed_const(pixel_bytes2); 2359 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); 2360 } 2361 2362 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); 2363 if (peak_disp_bw.full >= mem_bw.full) { 2364 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 2365 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 2366 } 2367 2368 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 2369 temp = RREG32(RADEON_MEM_TIMING_CNTL); 2370 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 2371 mem_trcd = ((temp >> 2) & 0x3) + 1; 2372 mem_trp = ((temp & 0x3)) + 1; 2373 mem_tras = ((temp & 0x70) >> 4) + 1; 2374 } else if (rdev->family == CHIP_R300 || 2375 rdev->family == CHIP_R350) { /* r300, r350 */ 2376 mem_trcd = (temp & 0x7) + 1; 2377 mem_trp = ((temp >> 8) & 0x7) + 1; 2378 mem_tras = ((temp >> 11) & 0xf) + 4; 2379 } else if (rdev->family == CHIP_RV350 || 2380 rdev->family <= CHIP_RV380) { 2381 /* rv3x0 */ 2382 mem_trcd = (temp & 0x7) + 3; 2383 mem_trp = ((temp >> 8) & 0x7) + 3; 2384 mem_tras = ((temp >> 11) & 0xf) + 6; 2385 } else if (rdev->family == CHIP_R420 || 2386 rdev->family == CHIP_R423 || 2387 rdev->family == CHIP_RV410) { 2388 /* r4xx */ 2389 mem_trcd = (temp & 0xf) + 3; 2390 if (mem_trcd > 15) 2391 mem_trcd = 15; 2392 mem_trp = ((temp >> 8) & 0xf) + 3; 2393 if (mem_trp > 15) 2394 mem_trp = 15; 2395 mem_tras = ((temp >> 12) & 0x1f) + 6; 2396 if (mem_tras > 31) 2397 mem_tras = 31; 2398 } else { /* RV200, R200 */ 2399 mem_trcd = (temp & 0x7) + 1; 2400 mem_trp = ((temp >> 8) & 0x7) + 1; 2401 mem_tras = ((temp >> 12) & 0xf) + 4; 2402 } 2403 /* convert to FF */ 2404 trcd_ff.full = rfixed_const(mem_trcd); 2405 trp_ff.full = rfixed_const(mem_trp); 2406 tras_ff.full = rfixed_const(mem_tras); 2407 2408 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 2409 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 2410 data = (temp & (7 << 20)) >> 20; 2411 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 2412 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 2413 tcas_ff = memtcas_rs480_ff[data]; 2414 else 2415 tcas_ff = memtcas_ff[data]; 2416 } else 2417 tcas_ff = memtcas2_ff[data]; 2418 2419 if (rdev->family == CHIP_RS400 || 2420 rdev->family == CHIP_RS480) { 2421 /* extra cas latency stored in bits 23-25 0-4 clocks */ 2422 data = (temp >> 23) & 0x7; 2423 if (data < 5) 2424 tcas_ff.full += rfixed_const(data); 2425 } 2426 2427 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2428 /* on the R300, Tcas is included in Trbs. 2429 */ 2430 temp = RREG32(RADEON_MEM_CNTL); 2431 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 2432 if (data == 1) { 2433 if (R300_MEM_USE_CD_CH_ONLY & temp) { 2434 temp = RREG32(R300_MC_IND_INDEX); 2435 temp &= ~R300_MC_IND_ADDR_MASK; 2436 temp |= R300_MC_READ_CNTL_CD_mcind; 2437 WREG32(R300_MC_IND_INDEX, temp); 2438 temp = RREG32(R300_MC_IND_DATA); 2439 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 2440 } else { 2441 temp = RREG32(R300_MC_READ_CNTL_AB); 2442 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2443 } 2444 } else { 2445 temp = RREG32(R300_MC_READ_CNTL_AB); 2446 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 2447 } 2448 if (rdev->family == CHIP_RV410 || 2449 rdev->family == CHIP_R420 || 2450 rdev->family == CHIP_R423) 2451 trbs_ff = memtrbs_r4xx[data]; 2452 else 2453 trbs_ff = memtrbs[data]; 2454 tcas_ff.full += trbs_ff.full; 2455 } 2456 2457 sclk_eff_ff.full = sclk_ff.full; 2458 2459 if (rdev->flags & RADEON_IS_AGP) { 2460 fixed20_12 agpmode_ff; 2461 agpmode_ff.full = rfixed_const(radeon_agpmode); 2462 temp_ff.full = rfixed_const_666(16); 2463 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff); 2464 } 2465 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 2466 2467 if (ASIC_IS_R300(rdev)) { 2468 sclk_delay_ff.full = rfixed_const(250); 2469 } else { 2470 if ((rdev->family == CHIP_RV100) || 2471 rdev->flags & RADEON_IS_IGP) { 2472 if (rdev->mc.vram_is_ddr) 2473 sclk_delay_ff.full = rfixed_const(41); 2474 else 2475 sclk_delay_ff.full = rfixed_const(33); 2476 } else { 2477 if (rdev->mc.vram_width == 128) 2478 sclk_delay_ff.full = rfixed_const(57); 2479 else 2480 sclk_delay_ff.full = rfixed_const(41); 2481 } 2482 } 2483 2484 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff); 2485 2486 if (rdev->mc.vram_is_ddr) { 2487 if (rdev->mc.vram_width == 32) { 2488 k1.full = rfixed_const(40); 2489 c = 3; 2490 } else { 2491 k1.full = rfixed_const(20); 2492 c = 1; 2493 } 2494 } else { 2495 k1.full = rfixed_const(40); 2496 c = 3; 2497 } 2498 2499 temp_ff.full = rfixed_const(2); 2500 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff); 2501 temp_ff.full = rfixed_const(c); 2502 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff); 2503 temp_ff.full = rfixed_const(4); 2504 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff); 2505 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff); 2506 mc_latency_mclk.full += k1.full; 2507 2508 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff); 2509 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff); 2510 2511 /* 2512 HW cursor time assuming worst case of full size colour cursor. 2513 */ 2514 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 2515 temp_ff.full += trcd_ff.full; 2516 if (temp_ff.full < tras_ff.full) 2517 temp_ff.full = tras_ff.full; 2518 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff); 2519 2520 temp_ff.full = rfixed_const(cur_size); 2521 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff); 2522 /* 2523 Find the total latency for the display data. 2524 */ 2525 disp_latency_overhead.full = rfixed_const(8); 2526 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); 2527 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 2528 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 2529 2530 if (mc_latency_mclk.full > mc_latency_sclk.full) 2531 disp_latency.full = mc_latency_mclk.full; 2532 else 2533 disp_latency.full = mc_latency_sclk.full; 2534 2535 /* setup Max GRPH_STOP_REQ default value */ 2536 if (ASIC_IS_RV100(rdev)) 2537 max_stop_req = 0x5c; 2538 else 2539 max_stop_req = 0x7c; 2540 2541 if (mode1) { 2542 /* CRTC1 2543 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 2544 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 2545 */ 2546 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 2547 2548 if (stop_req > max_stop_req) 2549 stop_req = max_stop_req; 2550 2551 /* 2552 Find the drain rate of the display buffer. 2553 */ 2554 temp_ff.full = rfixed_const((16/pixel_bytes1)); 2555 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff); 2556 2557 /* 2558 Find the critical point of the display buffer. 2559 */ 2560 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency); 2561 crit_point_ff.full += rfixed_const_half(0); 2562 2563 critical_point = rfixed_trunc(crit_point_ff); 2564 2565 if (rdev->disp_priority == 2) { 2566 critical_point = 0; 2567 } 2568 2569 /* 2570 The critical point should never be above max_stop_req-4. Setting 2571 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 2572 */ 2573 if (max_stop_req - critical_point < 4) 2574 critical_point = 0; 2575 2576 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 2577 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 2578 critical_point = 0x10; 2579 } 2580 2581 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 2582 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 2583 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 2584 temp &= ~(RADEON_GRPH_START_REQ_MASK); 2585 if ((rdev->family == CHIP_R350) && 2586 (stop_req > 0x15)) { 2587 stop_req -= 0x10; 2588 } 2589 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 2590 temp |= RADEON_GRPH_BUFFER_SIZE; 2591 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 2592 RADEON_GRPH_CRITICAL_AT_SOF | 2593 RADEON_GRPH_STOP_CNTL); 2594 /* 2595 Write the result into the register. 2596 */ 2597 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 2598 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 2599 2600 #if 0 2601 if ((rdev->family == CHIP_RS400) || 2602 (rdev->family == CHIP_RS480)) { 2603 /* attempt to program RS400 disp regs correctly ??? */ 2604 temp = RREG32(RS400_DISP1_REG_CNTL); 2605 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 2606 RS400_DISP1_STOP_REQ_LEVEL_MASK); 2607 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 2608 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 2609 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 2610 temp = RREG32(RS400_DMIF_MEM_CNTL1); 2611 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 2612 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 2613 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 2614 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 2615 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 2616 } 2617 #endif 2618 2619 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", 2620 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 2621 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 2622 } 2623 2624 if (mode2) { 2625 u32 grph2_cntl; 2626 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 2627 2628 if (stop_req > max_stop_req) 2629 stop_req = max_stop_req; 2630 2631 /* 2632 Find the drain rate of the display buffer. 2633 */ 2634 temp_ff.full = rfixed_const((16/pixel_bytes2)); 2635 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff); 2636 2637 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 2638 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 2639 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 2640 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 2641 if ((rdev->family == CHIP_R350) && 2642 (stop_req > 0x15)) { 2643 stop_req -= 0x10; 2644 } 2645 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 2646 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 2647 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 2648 RADEON_GRPH_CRITICAL_AT_SOF | 2649 RADEON_GRPH_STOP_CNTL); 2650 2651 if ((rdev->family == CHIP_RS100) || 2652 (rdev->family == CHIP_RS200)) 2653 critical_point2 = 0; 2654 else { 2655 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 2656 temp_ff.full = rfixed_const(temp); 2657 temp_ff.full = rfixed_mul(mclk_ff, temp_ff); 2658 if (sclk_ff.full < temp_ff.full) 2659 temp_ff.full = sclk_ff.full; 2660 2661 read_return_rate.full = temp_ff.full; 2662 2663 if (mode1) { 2664 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 2665 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff); 2666 } else { 2667 time_disp1_drop_priority.full = 0; 2668 } 2669 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 2670 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2); 2671 crit_point_ff.full += rfixed_const_half(0); 2672 2673 critical_point2 = rfixed_trunc(crit_point_ff); 2674 2675 if (rdev->disp_priority == 2) { 2676 critical_point2 = 0; 2677 } 2678 2679 if (max_stop_req - critical_point2 < 4) 2680 critical_point2 = 0; 2681 2682 } 2683 2684 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 2685 /* some R300 cards have problem with this set to 0 */ 2686 critical_point2 = 0x10; 2687 } 2688 2689 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 2690 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 2691 2692 if ((rdev->family == CHIP_RS400) || 2693 (rdev->family == CHIP_RS480)) { 2694 #if 0 2695 /* attempt to program RS400 disp2 regs correctly ??? */ 2696 temp = RREG32(RS400_DISP2_REQ_CNTL1); 2697 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 2698 RS400_DISP2_STOP_REQ_LEVEL_MASK); 2699 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 2700 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 2701 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 2702 temp = RREG32(RS400_DISP2_REQ_CNTL2); 2703 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 2704 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 2705 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 2706 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 2707 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 2708 #endif 2709 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 2710 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 2711 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 2712 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 2713 } 2714 2715 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", 2716 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 2717 } 2718 } 2719 2720 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2721 { 2722 DRM_ERROR("pitch %d\n", t->pitch); 2723 DRM_ERROR("use_pitch %d\n", t->use_pitch); 2724 DRM_ERROR("width %d\n", t->width); 2725 DRM_ERROR("width_11 %d\n", t->width_11); 2726 DRM_ERROR("height %d\n", t->height); 2727 DRM_ERROR("height_11 %d\n", t->height_11); 2728 DRM_ERROR("num levels %d\n", t->num_levels); 2729 DRM_ERROR("depth %d\n", t->txdepth); 2730 DRM_ERROR("bpp %d\n", t->cpp); 2731 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2732 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2733 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2734 } 2735 2736 static int r100_cs_track_cube(struct radeon_device *rdev, 2737 struct r100_cs_track *track, unsigned idx) 2738 { 2739 unsigned face, w, h; 2740 struct radeon_bo *cube_robj; 2741 unsigned long size; 2742 2743 for (face = 0; face < 5; face++) { 2744 cube_robj = track->textures[idx].cube_info[face].robj; 2745 w = track->textures[idx].cube_info[face].width; 2746 h = track->textures[idx].cube_info[face].height; 2747 2748 size = w * h; 2749 size *= track->textures[idx].cpp; 2750 2751 size += track->textures[idx].cube_info[face].offset; 2752 2753 if (size > radeon_bo_size(cube_robj)) { 2754 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2755 size, radeon_bo_size(cube_robj)); 2756 r100_cs_track_texture_print(&track->textures[idx]); 2757 return -1; 2758 } 2759 } 2760 return 0; 2761 } 2762 2763 static int r100_cs_track_texture_check(struct radeon_device *rdev, 2764 struct r100_cs_track *track) 2765 { 2766 struct radeon_bo *robj; 2767 unsigned long size; 2768 unsigned u, i, w, h; 2769 int ret; 2770 2771 for (u = 0; u < track->num_texture; u++) { 2772 if (!track->textures[u].enabled) 2773 continue; 2774 robj = track->textures[u].robj; 2775 if (robj == NULL) { 2776 DRM_ERROR("No texture bound to unit %u\n", u); 2777 return -EINVAL; 2778 } 2779 size = 0; 2780 for (i = 0; i <= track->textures[u].num_levels; i++) { 2781 if (track->textures[u].use_pitch) { 2782 if (rdev->family < CHIP_R300) 2783 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2784 else 2785 w = track->textures[u].pitch / (1 << i); 2786 } else { 2787 w = track->textures[u].width; 2788 if (rdev->family >= CHIP_RV515) 2789 w |= track->textures[u].width_11; 2790 w = w / (1 << i); 2791 if (track->textures[u].roundup_w) 2792 w = roundup_pow_of_two(w); 2793 } 2794 h = track->textures[u].height; 2795 if (rdev->family >= CHIP_RV515) 2796 h |= track->textures[u].height_11; 2797 h = h / (1 << i); 2798 if (track->textures[u].roundup_h) 2799 h = roundup_pow_of_two(h); 2800 size += w * h; 2801 } 2802 size *= track->textures[u].cpp; 2803 switch (track->textures[u].tex_coord_type) { 2804 case 0: 2805 break; 2806 case 1: 2807 size *= (1 << track->textures[u].txdepth); 2808 break; 2809 case 2: 2810 if (track->separate_cube) { 2811 ret = r100_cs_track_cube(rdev, track, u); 2812 if (ret) 2813 return ret; 2814 } else 2815 size *= 6; 2816 break; 2817 default: 2818 DRM_ERROR("Invalid texture coordinate type %u for unit " 2819 "%u\n", track->textures[u].tex_coord_type, u); 2820 return -EINVAL; 2821 } 2822 if (size > radeon_bo_size(robj)) { 2823 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2824 "%lu\n", u, size, radeon_bo_size(robj)); 2825 r100_cs_track_texture_print(&track->textures[u]); 2826 return -EINVAL; 2827 } 2828 } 2829 return 0; 2830 } 2831 2832 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2833 { 2834 unsigned i; 2835 unsigned long size; 2836 unsigned prim_walk; 2837 unsigned nverts; 2838 2839 for (i = 0; i < track->num_cb; i++) { 2840 if (track->cb[i].robj == NULL) { 2841 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2842 return -EINVAL; 2843 } 2844 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2845 size += track->cb[i].offset; 2846 if (size > radeon_bo_size(track->cb[i].robj)) { 2847 DRM_ERROR("[drm] Buffer too small for color buffer %d " 2848 "(need %lu have %lu) !\n", i, size, 2849 radeon_bo_size(track->cb[i].robj)); 2850 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2851 i, track->cb[i].pitch, track->cb[i].cpp, 2852 track->cb[i].offset, track->maxy); 2853 return -EINVAL; 2854 } 2855 } 2856 if (track->z_enabled) { 2857 if (track->zb.robj == NULL) { 2858 DRM_ERROR("[drm] No buffer for z buffer !\n"); 2859 return -EINVAL; 2860 } 2861 size = track->zb.pitch * track->zb.cpp * track->maxy; 2862 size += track->zb.offset; 2863 if (size > radeon_bo_size(track->zb.robj)) { 2864 DRM_ERROR("[drm] Buffer too small for z buffer " 2865 "(need %lu have %lu) !\n", size, 2866 radeon_bo_size(track->zb.robj)); 2867 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2868 track->zb.pitch, track->zb.cpp, 2869 track->zb.offset, track->maxy); 2870 return -EINVAL; 2871 } 2872 } 2873 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2874 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2875 switch (prim_walk) { 2876 case 1: 2877 for (i = 0; i < track->num_arrays; i++) { 2878 size = track->arrays[i].esize * track->max_indx * 4; 2879 if (track->arrays[i].robj == NULL) { 2880 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2881 "bound\n", prim_walk, i); 2882 return -EINVAL; 2883 } 2884 if (size > radeon_bo_size(track->arrays[i].robj)) { 2885 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2886 "need %lu dwords have %lu dwords\n", 2887 prim_walk, i, size >> 2, 2888 radeon_bo_size(track->arrays[i].robj) 2889 >> 2); 2890 DRM_ERROR("Max indices %u\n", track->max_indx); 2891 return -EINVAL; 2892 } 2893 } 2894 break; 2895 case 2: 2896 for (i = 0; i < track->num_arrays; i++) { 2897 size = track->arrays[i].esize * (nverts - 1) * 4; 2898 if (track->arrays[i].robj == NULL) { 2899 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2900 "bound\n", prim_walk, i); 2901 return -EINVAL; 2902 } 2903 if (size > radeon_bo_size(track->arrays[i].robj)) { 2904 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2905 "need %lu dwords have %lu dwords\n", 2906 prim_walk, i, size >> 2, 2907 radeon_bo_size(track->arrays[i].robj) 2908 >> 2); 2909 return -EINVAL; 2910 } 2911 } 2912 break; 2913 case 3: 2914 size = track->vtx_size * nverts; 2915 if (size != track->immd_dwords) { 2916 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2917 track->immd_dwords, size); 2918 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2919 nverts, track->vtx_size); 2920 return -EINVAL; 2921 } 2922 break; 2923 default: 2924 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2925 prim_walk); 2926 return -EINVAL; 2927 } 2928 return r100_cs_track_texture_check(rdev, track); 2929 } 2930 2931 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2932 { 2933 unsigned i, face; 2934 2935 if (rdev->family < CHIP_R300) { 2936 track->num_cb = 1; 2937 if (rdev->family <= CHIP_RS200) 2938 track->num_texture = 3; 2939 else 2940 track->num_texture = 6; 2941 track->maxy = 2048; 2942 track->separate_cube = 1; 2943 } else { 2944 track->num_cb = 4; 2945 track->num_texture = 16; 2946 track->maxy = 4096; 2947 track->separate_cube = 0; 2948 } 2949 2950 for (i = 0; i < track->num_cb; i++) { 2951 track->cb[i].robj = NULL; 2952 track->cb[i].pitch = 8192; 2953 track->cb[i].cpp = 16; 2954 track->cb[i].offset = 0; 2955 } 2956 track->z_enabled = true; 2957 track->zb.robj = NULL; 2958 track->zb.pitch = 8192; 2959 track->zb.cpp = 4; 2960 track->zb.offset = 0; 2961 track->vtx_size = 0x7F; 2962 track->immd_dwords = 0xFFFFFFFFUL; 2963 track->num_arrays = 11; 2964 track->max_indx = 0x00FFFFFFUL; 2965 for (i = 0; i < track->num_arrays; i++) { 2966 track->arrays[i].robj = NULL; 2967 track->arrays[i].esize = 0x7F; 2968 } 2969 for (i = 0; i < track->num_texture; i++) { 2970 track->textures[i].pitch = 16536; 2971 track->textures[i].width = 16536; 2972 track->textures[i].height = 16536; 2973 track->textures[i].width_11 = 1 << 11; 2974 track->textures[i].height_11 = 1 << 11; 2975 track->textures[i].num_levels = 12; 2976 if (rdev->family <= CHIP_RS200) { 2977 track->textures[i].tex_coord_type = 0; 2978 track->textures[i].txdepth = 0; 2979 } else { 2980 track->textures[i].txdepth = 16; 2981 track->textures[i].tex_coord_type = 1; 2982 } 2983 track->textures[i].cpp = 64; 2984 track->textures[i].robj = NULL; 2985 /* CS IB emission code makes sure texture unit are disabled */ 2986 track->textures[i].enabled = false; 2987 track->textures[i].roundup_w = true; 2988 track->textures[i].roundup_h = true; 2989 if (track->separate_cube) 2990 for (face = 0; face < 5; face++) { 2991 track->textures[i].cube_info[face].robj = NULL; 2992 track->textures[i].cube_info[face].width = 16536; 2993 track->textures[i].cube_info[face].height = 16536; 2994 track->textures[i].cube_info[face].offset = 0; 2995 } 2996 } 2997 } 2998 2999 int r100_ring_test(struct radeon_device *rdev) 3000 { 3001 uint32_t scratch; 3002 uint32_t tmp = 0; 3003 unsigned i; 3004 int r; 3005 3006 r = radeon_scratch_get(rdev, &scratch); 3007 if (r) { 3008 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3009 return r; 3010 } 3011 WREG32(scratch, 0xCAFEDEAD); 3012 r = radeon_ring_lock(rdev, 2); 3013 if (r) { 3014 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3015 radeon_scratch_free(rdev, scratch); 3016 return r; 3017 } 3018 radeon_ring_write(rdev, PACKET0(scratch, 0)); 3019 radeon_ring_write(rdev, 0xDEADBEEF); 3020 radeon_ring_unlock_commit(rdev); 3021 for (i = 0; i < rdev->usec_timeout; i++) { 3022 tmp = RREG32(scratch); 3023 if (tmp == 0xDEADBEEF) { 3024 break; 3025 } 3026 DRM_UDELAY(1); 3027 } 3028 if (i < rdev->usec_timeout) { 3029 DRM_INFO("ring test succeeded in %d usecs\n", i); 3030 } else { 3031 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", 3032 scratch, tmp); 3033 r = -EINVAL; 3034 } 3035 radeon_scratch_free(rdev, scratch); 3036 return r; 3037 } 3038 3039 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3040 { 3041 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); 3042 radeon_ring_write(rdev, ib->gpu_addr); 3043 radeon_ring_write(rdev, ib->length_dw); 3044 } 3045 3046 int r100_ib_test(struct radeon_device *rdev) 3047 { 3048 struct radeon_ib *ib; 3049 uint32_t scratch; 3050 uint32_t tmp = 0; 3051 unsigned i; 3052 int r; 3053 3054 r = radeon_scratch_get(rdev, &scratch); 3055 if (r) { 3056 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3057 return r; 3058 } 3059 WREG32(scratch, 0xCAFEDEAD); 3060 r = radeon_ib_get(rdev, &ib); 3061 if (r) { 3062 return r; 3063 } 3064 ib->ptr[0] = PACKET0(scratch, 0); 3065 ib->ptr[1] = 0xDEADBEEF; 3066 ib->ptr[2] = PACKET2(0); 3067 ib->ptr[3] = PACKET2(0); 3068 ib->ptr[4] = PACKET2(0); 3069 ib->ptr[5] = PACKET2(0); 3070 ib->ptr[6] = PACKET2(0); 3071 ib->ptr[7] = PACKET2(0); 3072 ib->length_dw = 8; 3073 r = radeon_ib_schedule(rdev, ib); 3074 if (r) { 3075 radeon_scratch_free(rdev, scratch); 3076 radeon_ib_free(rdev, &ib); 3077 return r; 3078 } 3079 r = radeon_fence_wait(ib->fence, false); 3080 if (r) { 3081 return r; 3082 } 3083 for (i = 0; i < rdev->usec_timeout; i++) { 3084 tmp = RREG32(scratch); 3085 if (tmp == 0xDEADBEEF) { 3086 break; 3087 } 3088 DRM_UDELAY(1); 3089 } 3090 if (i < rdev->usec_timeout) { 3091 DRM_INFO("ib test succeeded in %u usecs\n", i); 3092 } else { 3093 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", 3094 scratch, tmp); 3095 r = -EINVAL; 3096 } 3097 radeon_scratch_free(rdev, scratch); 3098 radeon_ib_free(rdev, &ib); 3099 return r; 3100 } 3101 3102 void r100_ib_fini(struct radeon_device *rdev) 3103 { 3104 radeon_ib_pool_fini(rdev); 3105 } 3106 3107 int r100_ib_init(struct radeon_device *rdev) 3108 { 3109 int r; 3110 3111 r = radeon_ib_pool_init(rdev); 3112 if (r) { 3113 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r); 3114 r100_ib_fini(rdev); 3115 return r; 3116 } 3117 r = r100_ib_test(rdev); 3118 if (r) { 3119 dev_err(rdev->dev, "failled testing IB (%d).\n", r); 3120 r100_ib_fini(rdev); 3121 return r; 3122 } 3123 return 0; 3124 } 3125 3126 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3127 { 3128 /* Shutdown CP we shouldn't need to do that but better be safe than 3129 * sorry 3130 */ 3131 rdev->cp.ready = false; 3132 WREG32(R_000740_CP_CSQ_CNTL, 0); 3133 3134 /* Save few CRTC registers */ 3135 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3136 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3137 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3138 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3139 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3140 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3141 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3142 } 3143 3144 /* Disable VGA aperture access */ 3145 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3146 /* Disable cursor, overlay, crtc */ 3147 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3148 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3149 S_000054_CRTC_DISPLAY_DIS(1)); 3150 WREG32(R_000050_CRTC_GEN_CNTL, 3151 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3152 S_000050_CRTC_DISP_REQ_EN_B(1)); 3153 WREG32(R_000420_OV0_SCALE_CNTL, 3154 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3155 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3156 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3157 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3158 S_000360_CUR2_LOCK(1)); 3159 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3160 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3161 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3162 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3163 WREG32(R_000360_CUR2_OFFSET, 3164 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3165 } 3166 } 3167 3168 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3169 { 3170 /* Update base address for crtc */ 3171 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location); 3172 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3173 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, 3174 rdev->mc.vram_location); 3175 } 3176 /* Restore CRTC registers */ 3177 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3178 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3179 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3180 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3181 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3182 } 3183 } 3184 3185 void r100_vga_render_disable(struct radeon_device *rdev) 3186 { 3187 u32 tmp; 3188 3189 tmp = RREG8(R_0003C2_GENMO_WT); 3190 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3191 } 3192 3193 static void r100_debugfs(struct radeon_device *rdev) 3194 { 3195 int r; 3196 3197 r = r100_debugfs_mc_info_init(rdev); 3198 if (r) 3199 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3200 } 3201 3202 static void r100_mc_program(struct radeon_device *rdev) 3203 { 3204 struct r100_mc_save save; 3205 3206 /* Stops all mc clients */ 3207 r100_mc_stop(rdev, &save); 3208 if (rdev->flags & RADEON_IS_AGP) { 3209 WREG32(R_00014C_MC_AGP_LOCATION, 3210 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3211 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3212 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 3213 if (rdev->family > CHIP_RV200) 3214 WREG32(R_00015C_AGP_BASE_2, 3215 upper_32_bits(rdev->mc.agp_base) & 0xff); 3216 } else { 3217 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3218 WREG32(R_000170_AGP_BASE, 0); 3219 if (rdev->family > CHIP_RV200) 3220 WREG32(R_00015C_AGP_BASE_2, 0); 3221 } 3222 /* Wait for mc idle */ 3223 if (r100_mc_wait_for_idle(rdev)) 3224 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3225 /* Program MC, should be a 32bits limited address space */ 3226 WREG32(R_000148_MC_FB_LOCATION, 3227 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3228 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3229 r100_mc_resume(rdev, &save); 3230 } 3231 3232 void r100_clock_startup(struct radeon_device *rdev) 3233 { 3234 u32 tmp; 3235 3236 if (radeon_dynclks != -1 && radeon_dynclks) 3237 radeon_legacy_set_clock_gating(rdev, 1); 3238 /* We need to force on some of the block */ 3239 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3240 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3241 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3242 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3243 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3244 } 3245 3246 static int r100_startup(struct radeon_device *rdev) 3247 { 3248 int r; 3249 3250 /* set common regs */ 3251 r100_set_common_regs(rdev); 3252 /* program mc */ 3253 r100_mc_program(rdev); 3254 /* Resume clock */ 3255 r100_clock_startup(rdev); 3256 /* Initialize GPU configuration (# pipes, ...) */ 3257 r100_gpu_init(rdev); 3258 /* Initialize GART (initialize after TTM so we can allocate 3259 * memory through TTM but finalize after TTM) */ 3260 r100_enable_bm(rdev); 3261 if (rdev->flags & RADEON_IS_PCI) { 3262 r = r100_pci_gart_enable(rdev); 3263 if (r) 3264 return r; 3265 } 3266 /* Enable IRQ */ 3267 r100_irq_set(rdev); 3268 /* 1M ring buffer */ 3269 r = r100_cp_init(rdev, 1024 * 1024); 3270 if (r) { 3271 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 3272 return r; 3273 } 3274 r = r100_wb_init(rdev); 3275 if (r) 3276 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 3277 r = r100_ib_init(rdev); 3278 if (r) { 3279 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 3280 return r; 3281 } 3282 return 0; 3283 } 3284 3285 int r100_resume(struct radeon_device *rdev) 3286 { 3287 /* Make sur GART are not working */ 3288 if (rdev->flags & RADEON_IS_PCI) 3289 r100_pci_gart_disable(rdev); 3290 /* Resume clock before doing reset */ 3291 r100_clock_startup(rdev); 3292 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3293 if (radeon_gpu_reset(rdev)) { 3294 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3295 RREG32(R_000E40_RBBM_STATUS), 3296 RREG32(R_0007C0_CP_STAT)); 3297 } 3298 /* post */ 3299 radeon_combios_asic_init(rdev->ddev); 3300 /* Resume clock after posting */ 3301 r100_clock_startup(rdev); 3302 /* Initialize surface registers */ 3303 radeon_surface_init(rdev); 3304 return r100_startup(rdev); 3305 } 3306 3307 int r100_suspend(struct radeon_device *rdev) 3308 { 3309 r100_cp_disable(rdev); 3310 r100_wb_disable(rdev); 3311 r100_irq_disable(rdev); 3312 if (rdev->flags & RADEON_IS_PCI) 3313 r100_pci_gart_disable(rdev); 3314 return 0; 3315 } 3316 3317 void r100_fini(struct radeon_device *rdev) 3318 { 3319 r100_suspend(rdev); 3320 r100_cp_fini(rdev); 3321 r100_wb_fini(rdev); 3322 r100_ib_fini(rdev); 3323 radeon_gem_fini(rdev); 3324 if (rdev->flags & RADEON_IS_PCI) 3325 r100_pci_gart_fini(rdev); 3326 radeon_irq_kms_fini(rdev); 3327 radeon_fence_driver_fini(rdev); 3328 radeon_bo_fini(rdev); 3329 radeon_atombios_fini(rdev); 3330 kfree(rdev->bios); 3331 rdev->bios = NULL; 3332 } 3333 3334 int r100_mc_init(struct radeon_device *rdev) 3335 { 3336 int r; 3337 u32 tmp; 3338 3339 /* Setup GPU memory space */ 3340 rdev->mc.vram_location = 0xFFFFFFFFUL; 3341 rdev->mc.gtt_location = 0xFFFFFFFFUL; 3342 if (rdev->flags & RADEON_IS_IGP) { 3343 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM)); 3344 rdev->mc.vram_location = tmp << 16; 3345 } 3346 if (rdev->flags & RADEON_IS_AGP) { 3347 r = radeon_agp_init(rdev); 3348 if (r) { 3349 printk(KERN_WARNING "[drm] Disabling AGP\n"); 3350 rdev->flags &= ~RADEON_IS_AGP; 3351 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 3352 } else { 3353 rdev->mc.gtt_location = rdev->mc.agp_base; 3354 } 3355 } 3356 r = radeon_mc_setup(rdev); 3357 if (r) 3358 return r; 3359 return 0; 3360 } 3361 3362 int r100_init(struct radeon_device *rdev) 3363 { 3364 int r; 3365 3366 /* Register debugfs file specific to this group of asics */ 3367 r100_debugfs(rdev); 3368 /* Disable VGA */ 3369 r100_vga_render_disable(rdev); 3370 /* Initialize scratch registers */ 3371 radeon_scratch_init(rdev); 3372 /* Initialize surface registers */ 3373 radeon_surface_init(rdev); 3374 /* TODO: disable VGA need to use VGA request */ 3375 /* BIOS*/ 3376 if (!radeon_get_bios(rdev)) { 3377 if (ASIC_IS_AVIVO(rdev)) 3378 return -EINVAL; 3379 } 3380 if (rdev->is_atom_bios) { 3381 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 3382 return -EINVAL; 3383 } else { 3384 r = radeon_combios_init(rdev); 3385 if (r) 3386 return r; 3387 } 3388 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 3389 if (radeon_gpu_reset(rdev)) { 3390 dev_warn(rdev->dev, 3391 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 3392 RREG32(R_000E40_RBBM_STATUS), 3393 RREG32(R_0007C0_CP_STAT)); 3394 } 3395 /* check if cards are posted or not */ 3396 if (radeon_boot_test_post_card(rdev) == false) 3397 return -EINVAL; 3398 /* Set asic errata */ 3399 r100_errata(rdev); 3400 /* Initialize clocks */ 3401 radeon_get_clock_info(rdev->ddev); 3402 /* Get vram informations */ 3403 r100_vram_info(rdev); 3404 /* Initialize memory controller (also test AGP) */ 3405 r = r100_mc_init(rdev); 3406 if (r) 3407 return r; 3408 /* Fence driver */ 3409 r = radeon_fence_driver_init(rdev); 3410 if (r) 3411 return r; 3412 r = radeon_irq_kms_init(rdev); 3413 if (r) 3414 return r; 3415 /* Memory manager */ 3416 r = radeon_bo_init(rdev); 3417 if (r) 3418 return r; 3419 if (rdev->flags & RADEON_IS_PCI) { 3420 r = r100_pci_gart_init(rdev); 3421 if (r) 3422 return r; 3423 } 3424 r100_set_safe_registers(rdev); 3425 rdev->accel_working = true; 3426 r = r100_startup(rdev); 3427 if (r) { 3428 /* Somethings want wront with the accel init stop accel */ 3429 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 3430 r100_suspend(rdev); 3431 r100_cp_fini(rdev); 3432 r100_wb_fini(rdev); 3433 r100_ib_fini(rdev); 3434 if (rdev->flags & RADEON_IS_PCI) 3435 r100_pci_gart_fini(rdev); 3436 radeon_irq_kms_fini(rdev); 3437 rdev->accel_working = false; 3438 } 3439 return 0; 3440 } 3441