handlers.c (ca1579f6c6085ecb1838d9ee052e535682cc0e73) handlers.c (75e64ff2c2f5ce1ae5b47b2f372fe5b9dc99f5a9)
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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1361
1362 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1363}
1364
1365static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1366 void *p_data, unsigned int bytes)
1367{
1368 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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1361
1362 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1363}
1364
1365static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1366 void *p_data, unsigned int bytes)
1367{
1368 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1369 i915_reg_t reg = {.reg = offset};
1369 u32 v = *(u32 *)p_data;
1370
1370
1371 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
1372 return intel_vgpu_default_mmio_write(vgpu,
1373 offset, p_data, bytes);
1374
1371 switch (offset) {
1372 case 0x4ddc:
1375 switch (offset) {
1376 case 0x4ddc:
1373 vgpu_vreg(vgpu, offset) = 0x8000003c;
1374 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */
1375 I915_WRITE(reg, vgpu_vreg(vgpu, offset));
1377 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1378 vgpu_vreg(vgpu, offset) = v & ~(1 << 31);
1376 break;
1377 case 0x42080:
1379 break;
1380 case 0x42080:
1378 vgpu_vreg(vgpu, offset) = 0x8000;
1379 /* WaCompressedResourceDisplayNewHashMode:skl */
1380 I915_WRITE(reg, vgpu_vreg(vgpu, offset));
1381 /* bypass WaCompressedResourceDisplayNewHashMode */
1382 vgpu_vreg(vgpu, offset) = v & ~(1 << 15);
1381 break;
1383 break;
1384 case 0xe194:
1385 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1386 vgpu_vreg(vgpu, offset) = v & ~(1 << 8);
1387 break;
1388 case 0x7014:
1389 /* bypass WaCompressedResourceSamplerPbeMediaNewHashMode */
1390 vgpu_vreg(vgpu, offset) = v & ~(1 << 13);
1391 break;
1382 default:
1383 return -EINVAL;
1384 }
1385
1386 return 0;
1387}
1388
1389static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,

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1629 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1630 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1631 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1632 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1633 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1634 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1635 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1636 NULL, NULL);
1392 default:
1393 return -EINVAL;
1394 }
1395
1396 return 0;
1397}
1398
1399static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,

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1639 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1640 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1641 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1642 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1643 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1644 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1645 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1646 NULL, NULL);
1637 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1647 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1648 skl_misc_ctl_write);
1638 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
1639 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
1640 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
1641 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL);
1642 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL);
1643 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL);
1644 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL);
1645 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

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1889
1890 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1891 dp_aux_ch_ctl_mmio_write);
1892 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1893 dp_aux_ch_ctl_mmio_write);
1894 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1895 dp_aux_ch_ctl_mmio_write);
1896
1649 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
1650 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
1651 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
1652 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL);
1653 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL);
1654 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL);
1655 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL);
1656 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

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1900
1901 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1902 dp_aux_ch_ctl_mmio_write);
1903 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1904 dp_aux_ch_ctl_mmio_write);
1905 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1906 dp_aux_ch_ctl_mmio_write);
1907
1897 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write);
1908 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
1898
1899 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
1900 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
1901
1902 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1903 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
1904 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
1905 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);

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2563
2564 MMIO_D(0x110000, D_BDW_PLUS);
2565
2566 MMIO_D(0x48400, D_BDW_PLUS);
2567
2568 MMIO_D(0x6e570, D_BDW_PLUS);
2569 MMIO_D(0x65f10, D_BDW_PLUS);
2570
1909
1910 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
1911 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
1912
1913 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1914 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
1915 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
1916 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);

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2574
2575 MMIO_D(0x110000, D_BDW_PLUS);
2576
2577 MMIO_D(0x48400, D_BDW_PLUS);
2578
2579 MMIO_D(0x6e570, D_BDW_PLUS);
2580 MMIO_D(0x65f10, D_BDW_PLUS);
2581
2571 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2582 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
2583 skl_misc_ctl_write);
2572 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2573 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2574 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2575
2576 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL);
2577
2578 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2579 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

--- 455 unchanged lines hidden --- 		2584 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2585 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2586 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2587
2588 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL);
2589
2590 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2591 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

--- 455 unchanged lines hidden ---