dma.h (cd60cd96137f6cb3ea82cace9225626619e7a52d) dma.h (dd4645ebb7d100bb04ba38ec58b499cbe95322fa)
1/*
2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *

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57 IOAT_MSI,
58 IOAT_INTX
59};
60
61/**
62 * struct ioatdma_device - internal representation of a IOAT device
63 * @pdev: PCI-Express device
64 * @reg_base: MMIO register space base address
1/*
2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *

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57 IOAT_MSI,
58 IOAT_INTX
59};
60
61/**
62 * struct ioatdma_device - internal representation of a IOAT device
63 * @pdev: PCI-Express device
64 * @reg_base: MMIO register space base address
65 * @dma_pool: for allocating DMA descriptors
66 * @completion_pool: DMA buffers for completion ops
67 * @sed_hw_pool: DMA super descriptor pools
68 * @dma_dev: embedded struct dma_device
69 * @version: version of ioatdma device
70 * @msix_entries: irq handlers
71 * @idx: per channel data
72 * @dca: direct cache access context
73 * @irq_mode: interrupt mode (INTX, MSI, MSIX)
74 * @cap: read DMA capabilities register
75 */
76struct ioatdma_device {
77 struct pci_dev *pdev;
78 void __iomem *reg_base;
65 * @completion_pool: DMA buffers for completion ops
66 * @sed_hw_pool: DMA super descriptor pools
67 * @dma_dev: embedded struct dma_device
68 * @version: version of ioatdma device
69 * @msix_entries: irq handlers
70 * @idx: per channel data
71 * @dca: direct cache access context
72 * @irq_mode: interrupt mode (INTX, MSI, MSIX)
73 * @cap: read DMA capabilities register
74 */
75struct ioatdma_device {
76 struct pci_dev *pdev;
77 void __iomem *reg_base;
79 struct dma_pool *dma_pool;
80 struct dma_pool *completion_pool;
81#define MAX_SED_POOLS 5
82 struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
83 struct dma_device dma_dev;
84 u8 version;
85#define IOAT_MAX_CHANS 4
86 struct msix_entry msix_entries[IOAT_MAX_CHANS];
87 struct ioatdma_chan *idx[IOAT_MAX_CHANS];
88 struct dca_provider *dca;
89 enum ioat_irq_mode irq_mode;
90 u32 cap;
91};
92
78 struct dma_pool *completion_pool;
79#define MAX_SED_POOLS 5
80 struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
81 struct dma_device dma_dev;
82 u8 version;
83#define IOAT_MAX_CHANS 4
84 struct msix_entry msix_entries[IOAT_MAX_CHANS];
85 struct ioatdma_chan *idx[IOAT_MAX_CHANS];
86 struct dca_provider *dca;
87 enum ioat_irq_mode irq_mode;
88 u32 cap;
89};
90
91struct ioat_descs {
92 void *virt;
93 dma_addr_t hw;
94};
95
93struct ioatdma_chan {
94 struct dma_chan dma_chan;
95 void __iomem *reg_base;
96 dma_addr_t last_completion;
97 spinlock_t cleanup_lock;
98 unsigned long state;
99 #define IOAT_CHAN_DOWN 0
100 #define IOAT_COMPLETION_ACK 1

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127 u16 head;
128 u16 issued;
129 u16 tail;
130 u16 dmacount;
131 u16 alloc_order;
132 u16 produce;
133 struct ioat_ring_ent **ring;
134 spinlock_t prep_lock;
96struct ioatdma_chan {
97 struct dma_chan dma_chan;
98 void __iomem *reg_base;
99 dma_addr_t last_completion;
100 spinlock_t cleanup_lock;
101 unsigned long state;
102 #define IOAT_CHAN_DOWN 0
103 #define IOAT_COMPLETION_ACK 1

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130 u16 head;
131 u16 issued;
132 u16 tail;
133 u16 dmacount;
134 u16 alloc_order;
135 u16 produce;
136 struct ioat_ring_ent **ring;
137 spinlock_t prep_lock;
138 struct ioat_descs descs[2];
139 int desc_chunks;
135};
136
137struct ioat_sysfs_entry {
138 struct attribute attr;
139 ssize_t (*show)(struct dma_chan *, char *);
140};
141
142/**

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296
297/* channel was fatally programmed */
298static inline bool is_ioat_bug(unsigned long err)
299{
300 return !!err;
301}
302
303#define IOAT_MAX_ORDER 16
140};
141
142struct ioat_sysfs_entry {
143 struct attribute attr;
144 ssize_t (*show)(struct dma_chan *, char *);
145};
146
147/**

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301
302/* channel was fatally programmed */
303static inline bool is_ioat_bug(unsigned long err)
304{
305 return !!err;
306}
307
308#define IOAT_MAX_ORDER 16
309#define IOAT_MAX_DESCS 65536
310#define IOAT_DESCS_PER_2M 32768
304
305static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan)
306{
307 return 1 << ioat_chan->alloc_order;
308}
309
310/* count of descriptors in flight with the engine */
311static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan)

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312static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan)
313{
314 return 1 << ioat_chan->alloc_order;
315}
316
317/* count of descriptors in flight with the engine */
318static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan)

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