1 /* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called COPYING. 16 */ 17 #ifndef IOATDMA_H 18 #define IOATDMA_H 19 20 #include <linux/dmaengine.h> 21 #include <linux/init.h> 22 #include <linux/dmapool.h> 23 #include <linux/cache.h> 24 #include <linux/pci_ids.h> 25 #include <linux/circ_buf.h> 26 #include <linux/interrupt.h> 27 #include "registers.h" 28 #include "hw.h" 29 30 #define IOAT_DMA_VERSION "4.00" 31 32 #define IOAT_DMA_DCA_ANY_CPU ~0 33 34 #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, dma_dev) 35 #define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev) 36 #define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev) 37 38 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80) 39 40 /* ioat hardware assumes at least two sources for raid operations */ 41 #define src_cnt_to_sw(x) ((x) + 2) 42 #define src_cnt_to_hw(x) ((x) - 2) 43 #define ndest_to_sw(x) ((x) + 1) 44 #define ndest_to_hw(x) ((x) - 1) 45 #define src16_cnt_to_sw(x) ((x) + 9) 46 #define src16_cnt_to_hw(x) ((x) - 9) 47 48 /* 49 * workaround for IOAT ver.3.0 null descriptor issue 50 * (channel returns error when size is 0) 51 */ 52 #define NULL_DESC_BUFFER_SIZE 1 53 54 enum ioat_irq_mode { 55 IOAT_NOIRQ = 0, 56 IOAT_MSIX, 57 IOAT_MSI, 58 IOAT_INTX 59 }; 60 61 /** 62 * struct ioatdma_device - internal representation of a IOAT device 63 * @pdev: PCI-Express device 64 * @reg_base: MMIO register space base address 65 * @dma_pool: for allocating DMA descriptors 66 * @completion_pool: DMA buffers for completion ops 67 * @sed_hw_pool: DMA super descriptor pools 68 * @dma_dev: embedded struct dma_device 69 * @version: version of ioatdma device 70 * @msix_entries: irq handlers 71 * @idx: per channel data 72 * @dca: direct cache access context 73 * @irq_mode: interrupt mode (INTX, MSI, MSIX) 74 * @cap: read DMA capabilities register 75 */ 76 struct ioatdma_device { 77 struct pci_dev *pdev; 78 void __iomem *reg_base; 79 struct dma_pool *dma_pool; 80 struct dma_pool *completion_pool; 81 #define MAX_SED_POOLS 5 82 struct dma_pool *sed_hw_pool[MAX_SED_POOLS]; 83 struct dma_device dma_dev; 84 u8 version; 85 #define IOAT_MAX_CHANS 4 86 struct msix_entry msix_entries[IOAT_MAX_CHANS]; 87 struct ioatdma_chan *idx[IOAT_MAX_CHANS]; 88 struct dca_provider *dca; 89 enum ioat_irq_mode irq_mode; 90 u32 cap; 91 }; 92 93 struct ioatdma_chan { 94 struct dma_chan dma_chan; 95 void __iomem *reg_base; 96 dma_addr_t last_completion; 97 spinlock_t cleanup_lock; 98 unsigned long state; 99 #define IOAT_CHAN_DOWN 0 100 #define IOAT_COMPLETION_ACK 1 101 #define IOAT_RESET_PENDING 2 102 #define IOAT_KOBJ_INIT_FAIL 3 103 #define IOAT_RUN 5 104 #define IOAT_CHAN_ACTIVE 6 105 struct timer_list timer; 106 #define COMPLETION_TIMEOUT msecs_to_jiffies(100) 107 #define IDLE_TIMEOUT msecs_to_jiffies(2000) 108 #define RESET_DELAY msecs_to_jiffies(100) 109 struct ioatdma_device *ioat_dma; 110 dma_addr_t completion_dma; 111 u64 *completion; 112 struct tasklet_struct cleanup_task; 113 struct kobject kobj; 114 115 /* ioat v2 / v3 channel attributes 116 * @xfercap_log; log2 of channel max transfer length (for fast division) 117 * @head: allocated index 118 * @issued: hardware notification point 119 * @tail: cleanup index 120 * @dmacount: identical to 'head' except for occasionally resetting to zero 121 * @alloc_order: log2 of the number of allocated descriptors 122 * @produce: number of descriptors to produce at submit time 123 * @ring: software ring buffer implementation of hardware ring 124 * @prep_lock: serializes descriptor preparation (producers) 125 */ 126 size_t xfercap_log; 127 u16 head; 128 u16 issued; 129 u16 tail; 130 u16 dmacount; 131 u16 alloc_order; 132 u16 produce; 133 struct ioat_ring_ent **ring; 134 spinlock_t prep_lock; 135 }; 136 137 struct ioat_sysfs_entry { 138 struct attribute attr; 139 ssize_t (*show)(struct dma_chan *, char *); 140 }; 141 142 /** 143 * struct ioat_sed_ent - wrapper around super extended hardware descriptor 144 * @hw: hardware SED 145 * @dma: dma address for the SED 146 * @parent: point to the dma descriptor that's the parent 147 * @hw_pool: descriptor pool index 148 */ 149 struct ioat_sed_ent { 150 struct ioat_sed_raw_descriptor *hw; 151 dma_addr_t dma; 152 struct ioat_ring_ent *parent; 153 unsigned int hw_pool; 154 }; 155 156 /** 157 * struct ioat_ring_ent - wrapper around hardware descriptor 158 * @hw: hardware DMA descriptor (for memcpy) 159 * @xor: hardware xor descriptor 160 * @xor_ex: hardware xor extension descriptor 161 * @pq: hardware pq descriptor 162 * @pq_ex: hardware pq extension descriptor 163 * @pqu: hardware pq update descriptor 164 * @raw: hardware raw (un-typed) descriptor 165 * @txd: the generic software descriptor for all engines 166 * @len: total transaction length for unmap 167 * @result: asynchronous result of validate operations 168 * @id: identifier for debug 169 * @sed: pointer to super extended descriptor sw desc 170 */ 171 172 struct ioat_ring_ent { 173 union { 174 struct ioat_dma_descriptor *hw; 175 struct ioat_xor_descriptor *xor; 176 struct ioat_xor_ext_descriptor *xor_ex; 177 struct ioat_pq_descriptor *pq; 178 struct ioat_pq_ext_descriptor *pq_ex; 179 struct ioat_pq_update_descriptor *pqu; 180 struct ioat_raw_descriptor *raw; 181 }; 182 size_t len; 183 struct dma_async_tx_descriptor txd; 184 enum sum_check_flags *result; 185 #ifdef DEBUG 186 int id; 187 #endif 188 struct ioat_sed_ent *sed; 189 }; 190 191 extern const struct sysfs_ops ioat_sysfs_ops; 192 extern struct ioat_sysfs_entry ioat_version_attr; 193 extern struct ioat_sysfs_entry ioat_cap_attr; 194 extern int ioat_pending_level; 195 extern int ioat_ring_alloc_order; 196 extern struct kobj_type ioat_ktype; 197 extern struct kmem_cache *ioat_cache; 198 extern int ioat_ring_max_alloc_order; 199 extern struct kmem_cache *ioat_sed_cache; 200 201 static inline struct ioatdma_chan *to_ioat_chan(struct dma_chan *c) 202 { 203 return container_of(c, struct ioatdma_chan, dma_chan); 204 } 205 206 /* wrapper around hardware descriptor format + additional software fields */ 207 #ifdef DEBUG 208 #define set_desc_id(desc, i) ((desc)->id = (i)) 209 #define desc_id(desc) ((desc)->id) 210 #else 211 #define set_desc_id(desc, i) 212 #define desc_id(desc) (0) 213 #endif 214 215 static inline void 216 __dump_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_dma_descriptor *hw, 217 struct dma_async_tx_descriptor *tx, int id) 218 { 219 struct device *dev = to_dev(ioat_chan); 220 221 dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x" 222 " ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id, 223 (unsigned long long) tx->phys, 224 (unsigned long long) hw->next, tx->cookie, tx->flags, 225 hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write); 226 } 227 228 #define dump_desc_dbg(c, d) \ 229 ({ if (d) __dump_desc_dbg(c, d->hw, &d->txd, desc_id(d)); 0; }) 230 231 static inline struct ioatdma_chan * 232 ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index) 233 { 234 return ioat_dma->idx[index]; 235 } 236 237 static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan) 238 { 239 return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET); 240 } 241 242 static inline u64 ioat_chansts_to_addr(u64 status) 243 { 244 return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; 245 } 246 247 static inline u32 ioat_chanerr(struct ioatdma_chan *ioat_chan) 248 { 249 return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); 250 } 251 252 static inline void ioat_suspend(struct ioatdma_chan *ioat_chan) 253 { 254 u8 ver = ioat_chan->ioat_dma->version; 255 256 writeb(IOAT_CHANCMD_SUSPEND, 257 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 258 } 259 260 static inline void ioat_reset(struct ioatdma_chan *ioat_chan) 261 { 262 u8 ver = ioat_chan->ioat_dma->version; 263 264 writeb(IOAT_CHANCMD_RESET, 265 ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 266 } 267 268 static inline bool ioat_reset_pending(struct ioatdma_chan *ioat_chan) 269 { 270 u8 ver = ioat_chan->ioat_dma->version; 271 u8 cmd; 272 273 cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); 274 return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET; 275 } 276 277 static inline bool is_ioat_active(unsigned long status) 278 { 279 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE); 280 } 281 282 static inline bool is_ioat_idle(unsigned long status) 283 { 284 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE); 285 } 286 287 static inline bool is_ioat_halted(unsigned long status) 288 { 289 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED); 290 } 291 292 static inline bool is_ioat_suspended(unsigned long status) 293 { 294 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED); 295 } 296 297 /* channel was fatally programmed */ 298 static inline bool is_ioat_bug(unsigned long err) 299 { 300 return !!err; 301 } 302 303 #define IOAT_MAX_ORDER 16 304 305 static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan) 306 { 307 return 1 << ioat_chan->alloc_order; 308 } 309 310 /* count of descriptors in flight with the engine */ 311 static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan) 312 { 313 return CIRC_CNT(ioat_chan->head, ioat_chan->tail, 314 ioat_ring_size(ioat_chan)); 315 } 316 317 /* count of descriptors pending submission to hardware */ 318 static inline u16 ioat_ring_pending(struct ioatdma_chan *ioat_chan) 319 { 320 return CIRC_CNT(ioat_chan->head, ioat_chan->issued, 321 ioat_ring_size(ioat_chan)); 322 } 323 324 static inline u32 ioat_ring_space(struct ioatdma_chan *ioat_chan) 325 { 326 return ioat_ring_size(ioat_chan) - ioat_ring_active(ioat_chan); 327 } 328 329 static inline u16 330 ioat_xferlen_to_descs(struct ioatdma_chan *ioat_chan, size_t len) 331 { 332 u16 num_descs = len >> ioat_chan->xfercap_log; 333 334 num_descs += !!(len & ((1 << ioat_chan->xfercap_log) - 1)); 335 return num_descs; 336 } 337 338 static inline struct ioat_ring_ent * 339 ioat_get_ring_ent(struct ioatdma_chan *ioat_chan, u16 idx) 340 { 341 return ioat_chan->ring[idx & (ioat_ring_size(ioat_chan) - 1)]; 342 } 343 344 static inline void 345 ioat_set_chainaddr(struct ioatdma_chan *ioat_chan, u64 addr) 346 { 347 writel(addr & 0x00000000FFFFFFFF, 348 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); 349 writel(addr >> 32, 350 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); 351 } 352 353 /* IOAT Prep functions */ 354 struct dma_async_tx_descriptor * 355 ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, 356 dma_addr_t dma_src, size_t len, unsigned long flags); 357 struct dma_async_tx_descriptor * 358 ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags); 359 struct dma_async_tx_descriptor * 360 ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, 361 unsigned int src_cnt, size_t len, unsigned long flags); 362 struct dma_async_tx_descriptor * 363 ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, 364 unsigned int src_cnt, size_t len, 365 enum sum_check_flags *result, unsigned long flags); 366 struct dma_async_tx_descriptor * 367 ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, 368 unsigned int src_cnt, const unsigned char *scf, size_t len, 369 unsigned long flags); 370 struct dma_async_tx_descriptor * 371 ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, 372 unsigned int src_cnt, const unsigned char *scf, size_t len, 373 enum sum_check_flags *pqres, unsigned long flags); 374 struct dma_async_tx_descriptor * 375 ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, 376 unsigned int src_cnt, size_t len, unsigned long flags); 377 struct dma_async_tx_descriptor * 378 ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, 379 unsigned int src_cnt, size_t len, 380 enum sum_check_flags *result, unsigned long flags); 381 382 /* IOAT Operation functions */ 383 irqreturn_t ioat_dma_do_interrupt(int irq, void *data); 384 irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data); 385 struct ioat_ring_ent ** 386 ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags); 387 void ioat_start_null_desc(struct ioatdma_chan *ioat_chan); 388 void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan); 389 int ioat_reset_hw(struct ioatdma_chan *ioat_chan); 390 enum dma_status 391 ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie, 392 struct dma_tx_state *txstate); 393 void ioat_cleanup_event(unsigned long data); 394 void ioat_timer_event(unsigned long data); 395 int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs); 396 void ioat_issue_pending(struct dma_chan *chan); 397 void ioat_timer_event(unsigned long data); 398 399 /* IOAT Init functions */ 400 bool is_bwd_ioat(struct pci_dev *pdev); 401 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase); 402 void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type); 403 void ioat_kobject_del(struct ioatdma_device *ioat_dma); 404 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma); 405 void ioat_stop(struct ioatdma_chan *ioat_chan); 406 #endif /* IOATDMA_H */ 407