| clk.h (139fd30943c3c8ed76d0ce08ff711cfff3b118ec) | clk.h (6b301a059eb2ebed1b12a900e3b21a38e48dd410) |
|---|---|
| 1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT --- 228 unchanged lines hidden (view full) --- 237 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the 238 * base register. 239 * TEGRA_PLL_BYPASS - PLL has bypass bit 240 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring 241 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv 242 * it may be more accurate (especially if SDM present) 243 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This 244 * flag indicated that it is PLLMB. | 1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT --- 228 unchanged lines hidden (view full) --- 237 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the 238 * base register. 239 * TEGRA_PLL_BYPASS - PLL has bypass bit 240 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring 241 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv 242 * it may be more accurate (especially if SDM present) 243 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This 244 * flag indicated that it is PLLMB. |
| 245 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output |
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| 245 */ 246struct tegra_clk_pll_params { 247 unsigned long input_min; 248 unsigned long input_max; 249 unsigned long cf_min; 250 unsigned long cf_max; 251 unsigned long vco_min; 252 unsigned long vco_max; --- 49 unchanged lines hidden (view full) --- 302#define TEGRA_PLLM BIT(5) 303#define TEGRA_PLL_FIXED BIT(6) 304#define TEGRA_PLLE_CONFIGURE BIT(7) 305#define TEGRA_PLL_LOCK_MISC BIT(8) 306#define TEGRA_PLL_BYPASS BIT(9) 307#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) 308#define TEGRA_MDIV_NEW BIT(11) 309#define TEGRA_PLLMB BIT(12) | 246 */ 247struct tegra_clk_pll_params { 248 unsigned long input_min; 249 unsigned long input_max; 250 unsigned long cf_min; 251 unsigned long cf_max; 252 unsigned long vco_min; 253 unsigned long vco_max; --- 49 unchanged lines hidden (view full) --- 303#define TEGRA_PLLM BIT(5) 304#define TEGRA_PLL_FIXED BIT(6) 305#define TEGRA_PLLE_CONFIGURE BIT(7) 306#define TEGRA_PLL_LOCK_MISC BIT(8) 307#define TEGRA_PLL_BYPASS BIT(9) 308#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) 309#define TEGRA_MDIV_NEW BIT(11) 310#define TEGRA_PLLMB BIT(12) |
| 311#define TEGRA_PLL_VCO_OUT BIT(13) |
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| 310 311/** 312 * struct tegra_clk_pll - Tegra PLL clock 313 * 314 * @hw: handle between common and hardware-specifix interfaces 315 * @clk_base: address of CAR controller 316 * @pmc: address of PMC, required to read override bits 317 * @lock: register lock --- 443 unchanged lines hidden (view full) --- 761void tegra114_clock_tune_cpu_trimmers_init(void); 762void tegra114_clock_assert_dfll_dvco_reset(void); 763void tegra114_clock_deassert_dfll_dvco_reset(void); 764 765typedef void (*tegra_clk_apply_init_table_func)(void); 766extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 767int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); 768u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); | 312 313/** 314 * struct tegra_clk_pll - Tegra PLL clock 315 * 316 * @hw: handle between common and hardware-specifix interfaces 317 * @clk_base: address of CAR controller 318 * @pmc: address of PMC, required to read override bits 319 * @lock: register lock --- 443 unchanged lines hidden (view full) --- 763void tegra114_clock_tune_cpu_trimmers_init(void); 764void tegra114_clock_assert_dfll_dvco_reset(void); 765void tegra114_clock_deassert_dfll_dvco_reset(void); 766 767typedef void (*tegra_clk_apply_init_table_func)(void); 768extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 769int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); 770u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); |
| 771int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div); |
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| 769 770#endif /* TEGRA_CLK_H */ | 772 773#endif /* TEGRA_CLK_H */ |