1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __TEGRA_CLK_H 18 #define __TEGRA_CLK_H 19 20 #include <linux/clk-provider.h> 21 #include <linux/clkdev.h> 22 23 /** 24 * struct tegra_clk_sync_source - external clock source from codec 25 * 26 * @hw: handle between common and hardware-specific interfaces 27 * @rate: input frequency from source 28 * @max_rate: max rate allowed 29 */ 30 struct tegra_clk_sync_source { 31 struct clk_hw hw; 32 unsigned long rate; 33 unsigned long max_rate; 34 }; 35 36 #define to_clk_sync_source(_hw) \ 37 container_of(_hw, struct tegra_clk_sync_source, hw) 38 39 extern const struct clk_ops tegra_clk_sync_source_ops; 40 extern int *periph_clk_enb_refcnt; 41 42 struct clk *tegra_clk_register_sync_source(const char *name, 43 unsigned long fixed_rate, unsigned long max_rate); 44 45 /** 46 * struct tegra_clk_frac_div - fractional divider clock 47 * 48 * @hw: handle between common and hardware-specific interfaces 49 * @reg: register containing divider 50 * @flags: hardware-specific flags 51 * @shift: shift to the divider bit field 52 * @width: width of the divider bit field 53 * @frac_width: width of the fractional bit field 54 * @lock: register lock 55 * 56 * Flags: 57 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 58 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 59 * flag indicates that this divider is for fixed rate PLL. 60 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when 61 * fraction bit is set. This flags indicates to calculate divider for which 62 * fracton bit will be zero. 63 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is 64 * set when divider value is not 0. This flags indicates that the divider 65 * is for UART module. 66 */ 67 struct tegra_clk_frac_div { 68 struct clk_hw hw; 69 void __iomem *reg; 70 u8 flags; 71 u8 shift; 72 u8 width; 73 u8 frac_width; 74 spinlock_t *lock; 75 }; 76 77 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) 78 79 #define TEGRA_DIVIDER_ROUND_UP BIT(0) 80 #define TEGRA_DIVIDER_FIXED BIT(1) 81 #define TEGRA_DIVIDER_INT BIT(2) 82 #define TEGRA_DIVIDER_UART BIT(3) 83 84 extern const struct clk_ops tegra_clk_frac_div_ops; 85 struct clk *tegra_clk_register_divider(const char *name, 86 const char *parent_name, void __iomem *reg, 87 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, 88 u8 frac_width, spinlock_t *lock); 89 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, 90 void __iomem *reg, spinlock_t *lock); 91 92 /* 93 * Tegra PLL: 94 * 95 * In general, there are 3 requirements for each PLL 96 * that SW needs to be comply with. 97 * (1) Input frequency range (REF). 98 * (2) Comparison frequency range (CF). CF = REF/DIVM. 99 * (3) VCO frequency range (VCO). VCO = CF * DIVN. 100 * 101 * The final PLL output frequency (FO) = VCO >> DIVP. 102 */ 103 104 /** 105 * struct tegra_clk_pll_freq_table - PLL frequecy table 106 * 107 * @input_rate: input rate from source 108 * @output_rate: output rate from PLL for the input rate 109 * @n: feedback divider 110 * @m: input divider 111 * @p: post divider 112 * @cpcon: charge pump current 113 * @sdm_data: fraction divider setting (0 = disabled) 114 */ 115 struct tegra_clk_pll_freq_table { 116 unsigned long input_rate; 117 unsigned long output_rate; 118 u32 n; 119 u16 m; 120 u8 p; 121 u8 cpcon; 122 u16 sdm_data; 123 }; 124 125 /** 126 * struct pdiv_map - map post divider to hw value 127 * 128 * @pdiv: post divider 129 * @hw_val: value to be written to the PLL hw 130 */ 131 struct pdiv_map { 132 u8 pdiv; 133 u8 hw_val; 134 }; 135 136 /** 137 * struct div_nmp - offset and width of m,n and p fields 138 * 139 * @divn_shift: shift to the feedback divider bit field 140 * @divn_width: width of the feedback divider bit field 141 * @divm_shift: shift to the input divider bit field 142 * @divm_width: width of the input divider bit field 143 * @divp_shift: shift to the post divider bit field 144 * @divp_width: width of the post divider bit field 145 * @override_divn_shift: shift to the feedback divider bitfield in override reg 146 * @override_divm_shift: shift to the input divider bitfield in override reg 147 * @override_divp_shift: shift to the post divider bitfield in override reg 148 */ 149 struct div_nmp { 150 u8 divn_shift; 151 u8 divn_width; 152 u8 divm_shift; 153 u8 divm_width; 154 u8 divp_shift; 155 u8 divp_width; 156 u8 override_divn_shift; 157 u8 override_divm_shift; 158 u8 override_divp_shift; 159 }; 160 161 #define MAX_PLL_MISC_REG_COUNT 6 162 163 struct tegra_clk_pll; 164 165 /** 166 * struct tegra_clk_pll_params - PLL parameters 167 * 168 * @input_min: Minimum input frequency 169 * @input_max: Maximum input frequency 170 * @cf_min: Minimum comparison frequency 171 * @cf_max: Maximum comparison frequency 172 * @vco_min: Minimum VCO frequency 173 * @vco_max: Maximum VCO frequency 174 * @base_reg: PLL base reg offset 175 * @misc_reg: PLL misc reg offset 176 * @lock_reg: PLL lock reg offset 177 * @lock_mask: Bitmask for PLL lock status 178 * @lock_enable_bit_idx: Bit index to enable PLL lock 179 * @iddq_reg: PLL IDDQ register offset 180 * @iddq_bit_idx: Bit index to enable PLL IDDQ 181 * @reset_reg: Register offset of where RESET bit is 182 * @reset_bit_idx: Shift of reset bit in reset_reg 183 * @sdm_din_reg: Register offset where SDM settings are 184 * @sdm_din_mask: Mask of SDM divider bits 185 * @sdm_ctrl_reg: Register offset where SDM enable is 186 * @sdm_ctrl_en_mask: Mask of SDM enable bit 187 * @ssc_ctrl_reg: Register offset where SSC settings are 188 * @ssc_ctrl_en_mask: Mask of SSC enable bit 189 * @aux_reg: AUX register offset 190 * @dyn_ramp_reg: Dynamic ramp control register offset 191 * @ext_misc_reg: Miscellaneous control register offsets 192 * @pmc_divnm_reg: n, m divider PMC override register offset (PLLM) 193 * @pmc_divp_reg: p divider PMC override register offset (PLLM) 194 * @flags: PLL flags 195 * @stepa_shift: Dynamic ramp step A field shift 196 * @stepb_shift: Dynamic ramp step B field shift 197 * @lock_delay: Delay in us if PLL lock is not used 198 * @max_p: maximum value for the p divider 199 * @defaults_set: Boolean signaling all reg defaults for PLL set. 200 * @pdiv_tohw: mapping of p divider to register values 201 * @div_nmp: offsets and widths on n, m and p fields 202 * @freq_table: array of frequencies supported by PLL 203 * @fixed_rate: PLL rate if it is fixed 204 * @mdiv_default: Default value for fixed mdiv for this PLL 205 * @round_p_to_pdiv: Callback used to round p to the closed pdiv 206 * @set_gain: Callback to adjust N div for SDM enabled 207 * PLL's based on fractional divider value. 208 * @calc_rate: Callback used to change how out of table 209 * rates (dividers and multipler) are calculated. 210 * @adjust_vco: Callback to adjust the programming range of the 211 * divider range (if SDM is present) 212 * @set_defaults: Callback which will try to initialize PLL 213 * registers to sane default values. This is first 214 * tried during PLL registration, but if the PLL 215 * is already enabled, it will be done the first 216 * time the rate is changed while the PLL is 217 * disabled. 218 * @dyn_ramp: Callback which can be used to define a custom 219 * dynamic ramp function for a given PLL. 220 * 221 * Flags: 222 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for 223 * PLL locking. If not set it will use lock_delay value to wait. 224 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs 225 * to be programmed to change output frequency of the PLL. 226 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs 227 * to be programmed to change output frequency of the PLL. 228 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs 229 * to be programmed to change output frequency of the PLL. 230 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated 231 * that it is PLLU and invert post divider value. 232 * TEGRA_PLLM - PLLM has additional override settings in PMC. This 233 * flag indicates that it is PLLM and use override settings. 234 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 235 * of some plls. 236 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 237 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the 238 * base register. 239 * TEGRA_PLL_BYPASS - PLL has bypass bit 240 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring 241 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv 242 * it may be more accurate (especially if SDM present) 243 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This 244 * flag indicated that it is PLLMB. 245 */ 246 struct tegra_clk_pll_params { 247 unsigned long input_min; 248 unsigned long input_max; 249 unsigned long cf_min; 250 unsigned long cf_max; 251 unsigned long vco_min; 252 unsigned long vco_max; 253 254 u32 base_reg; 255 u32 misc_reg; 256 u32 lock_reg; 257 u32 lock_mask; 258 u32 lock_enable_bit_idx; 259 u32 iddq_reg; 260 u32 iddq_bit_idx; 261 u32 reset_reg; 262 u32 reset_bit_idx; 263 u32 sdm_din_reg; 264 u32 sdm_din_mask; 265 u32 sdm_ctrl_reg; 266 u32 sdm_ctrl_en_mask; 267 u32 ssc_ctrl_reg; 268 u32 ssc_ctrl_en_mask; 269 u32 aux_reg; 270 u32 dyn_ramp_reg; 271 u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT]; 272 u32 pmc_divnm_reg; 273 u32 pmc_divp_reg; 274 u32 flags; 275 int stepa_shift; 276 int stepb_shift; 277 int lock_delay; 278 int max_p; 279 bool defaults_set; 280 const struct pdiv_map *pdiv_tohw; 281 struct div_nmp *div_nmp; 282 struct tegra_clk_pll_freq_table *freq_table; 283 unsigned long fixed_rate; 284 u16 mdiv_default; 285 u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv); 286 void (*set_gain)(struct tegra_clk_pll_freq_table *cfg); 287 int (*calc_rate)(struct clk_hw *hw, 288 struct tegra_clk_pll_freq_table *cfg, 289 unsigned long rate, unsigned long parent_rate); 290 unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params, 291 unsigned long parent_rate); 292 void (*set_defaults)(struct tegra_clk_pll *pll); 293 int (*dyn_ramp)(struct tegra_clk_pll *pll, 294 struct tegra_clk_pll_freq_table *cfg); 295 }; 296 297 #define TEGRA_PLL_USE_LOCK BIT(0) 298 #define TEGRA_PLL_HAS_CPCON BIT(1) 299 #define TEGRA_PLL_SET_LFCON BIT(2) 300 #define TEGRA_PLL_SET_DCCON BIT(3) 301 #define TEGRA_PLLU BIT(4) 302 #define TEGRA_PLLM BIT(5) 303 #define TEGRA_PLL_FIXED BIT(6) 304 #define TEGRA_PLLE_CONFIGURE BIT(7) 305 #define TEGRA_PLL_LOCK_MISC BIT(8) 306 #define TEGRA_PLL_BYPASS BIT(9) 307 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) 308 #define TEGRA_MDIV_NEW BIT(11) 309 #define TEGRA_PLLMB BIT(12) 310 311 /** 312 * struct tegra_clk_pll - Tegra PLL clock 313 * 314 * @hw: handle between common and hardware-specifix interfaces 315 * @clk_base: address of CAR controller 316 * @pmc: address of PMC, required to read override bits 317 * @lock: register lock 318 * @params: PLL parameters 319 */ 320 struct tegra_clk_pll { 321 struct clk_hw hw; 322 void __iomem *clk_base; 323 void __iomem *pmc; 324 spinlock_t *lock; 325 struct tegra_clk_pll_params *params; 326 }; 327 328 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) 329 330 /** 331 * struct tegra_audio_clk_info - Tegra Audio Clk Information 332 * 333 * @name: name for the audio pll 334 * @pll_params: pll_params for audio pll 335 * @clk_id: clk_ids for the audio pll 336 * @parent: name of the parent of the audio pll 337 */ 338 struct tegra_audio_clk_info { 339 char *name; 340 struct tegra_clk_pll_params *pll_params; 341 int clk_id; 342 char *parent; 343 }; 344 345 extern const struct clk_ops tegra_clk_pll_ops; 346 extern const struct clk_ops tegra_clk_plle_ops; 347 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 348 void __iomem *clk_base, void __iomem *pmc, 349 unsigned long flags, struct tegra_clk_pll_params *pll_params, 350 spinlock_t *lock); 351 352 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 353 void __iomem *clk_base, void __iomem *pmc, 354 unsigned long flags, struct tegra_clk_pll_params *pll_params, 355 spinlock_t *lock); 356 357 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 358 void __iomem *clk_base, void __iomem *pmc, 359 unsigned long flags, 360 struct tegra_clk_pll_params *pll_params, 361 spinlock_t *lock); 362 363 struct clk *tegra_clk_register_pllxc_tegra210(const char *name, 364 const char *parent_name, void __iomem *clk_base, 365 void __iomem *pmc, unsigned long flags, 366 struct tegra_clk_pll_params *pll_params, 367 spinlock_t *lock); 368 369 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 370 void __iomem *clk_base, void __iomem *pmc, 371 unsigned long flags, 372 struct tegra_clk_pll_params *pll_params, 373 spinlock_t *lock); 374 375 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 376 void __iomem *clk_base, void __iomem *pmc, 377 unsigned long flags, 378 struct tegra_clk_pll_params *pll_params, 379 spinlock_t *lock); 380 381 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 382 void __iomem *clk_base, void __iomem *pmc, 383 unsigned long flags, 384 struct tegra_clk_pll_params *pll_params, 385 spinlock_t *lock, unsigned long parent_rate); 386 387 struct clk *tegra_clk_register_plle_tegra114(const char *name, 388 const char *parent_name, 389 void __iomem *clk_base, unsigned long flags, 390 struct tegra_clk_pll_params *pll_params, 391 spinlock_t *lock); 392 393 struct clk *tegra_clk_register_plle_tegra210(const char *name, 394 const char *parent_name, 395 void __iomem *clk_base, unsigned long flags, 396 struct tegra_clk_pll_params *pll_params, 397 spinlock_t *lock); 398 399 struct clk *tegra_clk_register_pllc_tegra210(const char *name, 400 const char *parent_name, void __iomem *clk_base, 401 void __iomem *pmc, unsigned long flags, 402 struct tegra_clk_pll_params *pll_params, 403 spinlock_t *lock); 404 405 struct clk *tegra_clk_register_pllss_tegra210(const char *name, 406 const char *parent_name, void __iomem *clk_base, 407 unsigned long flags, 408 struct tegra_clk_pll_params *pll_params, 409 spinlock_t *lock); 410 411 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 412 void __iomem *clk_base, unsigned long flags, 413 struct tegra_clk_pll_params *pll_params, 414 spinlock_t *lock); 415 416 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, 417 void __iomem *clk_base, void __iomem *pmc, 418 unsigned long flags, 419 struct tegra_clk_pll_params *pll_params, 420 spinlock_t *lock); 421 422 /** 423 * struct tegra_clk_pll_out - PLL divider down clock 424 * 425 * @hw: handle between common and hardware-specific interfaces 426 * @reg: register containing the PLL divider 427 * @enb_bit_idx: bit to enable/disable PLL divider 428 * @rst_bit_idx: bit to reset PLL divider 429 * @lock: register lock 430 * @flags: hardware-specific flags 431 */ 432 struct tegra_clk_pll_out { 433 struct clk_hw hw; 434 void __iomem *reg; 435 u8 enb_bit_idx; 436 u8 rst_bit_idx; 437 spinlock_t *lock; 438 u8 flags; 439 }; 440 441 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) 442 443 extern const struct clk_ops tegra_clk_pll_out_ops; 444 struct clk *tegra_clk_register_pll_out(const char *name, 445 const char *parent_name, void __iomem *reg, u8 enb_bit_idx, 446 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, 447 spinlock_t *lock); 448 449 /** 450 * struct tegra_clk_periph_regs - Registers controlling peripheral clock 451 * 452 * @enb_reg: read the enable status 453 * @enb_set_reg: write 1 to enable clock 454 * @enb_clr_reg: write 1 to disable clock 455 * @rst_reg: read the reset status 456 * @rst_set_reg: write 1 to assert the reset of peripheral 457 * @rst_clr_reg: write 1 to deassert the reset of peripheral 458 */ 459 struct tegra_clk_periph_regs { 460 u32 enb_reg; 461 u32 enb_set_reg; 462 u32 enb_clr_reg; 463 u32 rst_reg; 464 u32 rst_set_reg; 465 u32 rst_clr_reg; 466 }; 467 468 /** 469 * struct tegra_clk_periph_gate - peripheral gate clock 470 * 471 * @magic: magic number to validate type 472 * @hw: handle between common and hardware-specific interfaces 473 * @clk_base: address of CAR controller 474 * @regs: Registers to control the peripheral 475 * @flags: hardware-specific flags 476 * @clk_num: Clock number 477 * @enable_refcnt: array to maintain reference count of the clock 478 * 479 * Flags: 480 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed 481 * for this module. 482 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module 483 * after clock enable and driver for the module is responsible for 484 * doing reset. 485 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 486 * bus to flush the write operation in apb bus. This flag indicates 487 * that this peripheral is in apb bus. 488 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug 489 */ 490 struct tegra_clk_periph_gate { 491 u32 magic; 492 struct clk_hw hw; 493 void __iomem *clk_base; 494 u8 flags; 495 int clk_num; 496 int *enable_refcnt; 497 struct tegra_clk_periph_regs *regs; 498 }; 499 500 #define to_clk_periph_gate(_hw) \ 501 container_of(_hw, struct tegra_clk_periph_gate, hw) 502 503 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 504 505 #define TEGRA_PERIPH_NO_RESET BIT(0) 506 #define TEGRA_PERIPH_MANUAL_RESET BIT(1) 507 #define TEGRA_PERIPH_ON_APB BIT(2) 508 #define TEGRA_PERIPH_WAR_1005168 BIT(3) 509 #define TEGRA_PERIPH_NO_DIV BIT(4) 510 #define TEGRA_PERIPH_NO_GATE BIT(5) 511 512 extern const struct clk_ops tegra_clk_periph_gate_ops; 513 struct clk *tegra_clk_register_periph_gate(const char *name, 514 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 515 unsigned long flags, int clk_num, int *enable_refcnt); 516 517 /** 518 * struct clk-periph - peripheral clock 519 * 520 * @magic: magic number to validate type 521 * @hw: handle between common and hardware-specific interfaces 522 * @mux: mux clock 523 * @divider: divider clock 524 * @gate: gate clock 525 * @mux_ops: mux clock ops 526 * @div_ops: divider clock ops 527 * @gate_ops: gate clock ops 528 */ 529 struct tegra_clk_periph { 530 u32 magic; 531 struct clk_hw hw; 532 struct clk_mux mux; 533 struct tegra_clk_frac_div divider; 534 struct tegra_clk_periph_gate gate; 535 536 const struct clk_ops *mux_ops; 537 const struct clk_ops *div_ops; 538 const struct clk_ops *gate_ops; 539 }; 540 541 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) 542 543 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 544 545 extern const struct clk_ops tegra_clk_periph_ops; 546 struct clk *tegra_clk_register_periph(const char *name, 547 const char **parent_names, int num_parents, 548 struct tegra_clk_periph *periph, void __iomem *clk_base, 549 u32 offset, unsigned long flags); 550 struct clk *tegra_clk_register_periph_nodiv(const char *name, 551 const char **parent_names, int num_parents, 552 struct tegra_clk_periph *periph, void __iomem *clk_base, 553 u32 offset); 554 555 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 556 _div_shift, _div_width, _div_frac_width, \ 557 _div_flags, _clk_num,\ 558 _gate_flags, _table, _lock) \ 559 { \ 560 .mux = { \ 561 .flags = _mux_flags, \ 562 .shift = _mux_shift, \ 563 .mask = _mux_mask, \ 564 .table = _table, \ 565 .lock = _lock, \ 566 }, \ 567 .divider = { \ 568 .flags = _div_flags, \ 569 .shift = _div_shift, \ 570 .width = _div_width, \ 571 .frac_width = _div_frac_width, \ 572 .lock = _lock, \ 573 }, \ 574 .gate = { \ 575 .flags = _gate_flags, \ 576 .clk_num = _clk_num, \ 577 }, \ 578 .mux_ops = &clk_mux_ops, \ 579 .div_ops = &tegra_clk_frac_div_ops, \ 580 .gate_ops = &tegra_clk_periph_gate_ops, \ 581 } 582 583 struct tegra_periph_init_data { 584 const char *name; 585 int clk_id; 586 union { 587 const char **parent_names; 588 const char *parent_name; 589 } p; 590 int num_parents; 591 struct tegra_clk_periph periph; 592 u32 offset; 593 const char *con_id; 594 const char *dev_id; 595 unsigned long flags; 596 }; 597 598 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 599 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 600 _div_width, _div_frac_width, _div_flags, \ 601 _clk_num, _gate_flags, _clk_id, _table, \ 602 _flags, _lock) \ 603 { \ 604 .name = _name, \ 605 .clk_id = _clk_id, \ 606 .p.parent_names = _parent_names, \ 607 .num_parents = ARRAY_SIZE(_parent_names), \ 608 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 609 _mux_flags, _div_shift, \ 610 _div_width, _div_frac_width, \ 611 _div_flags, _clk_num, \ 612 _gate_flags, _table, _lock), \ 613 .offset = _offset, \ 614 .con_id = _con_id, \ 615 .dev_id = _dev_id, \ 616 .flags = _flags \ 617 } 618 619 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 620 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 621 _div_width, _div_frac_width, _div_flags, \ 622 _clk_num, _gate_flags, _clk_id) \ 623 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 624 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 625 _div_shift, _div_width, _div_frac_width, _div_flags, \ 626 _clk_num, _gate_flags, _clk_id,\ 627 NULL, 0, NULL) 628 629 /** 630 * struct clk_super_mux - super clock 631 * 632 * @hw: handle between common and hardware-specific interfaces 633 * @reg: register controlling multiplexer 634 * @width: width of the multiplexer bit field 635 * @flags: hardware-specific flags 636 * @div2_index: bit controlling divide-by-2 637 * @pllx_index: PLLX index in the parent list 638 * @lock: register lock 639 * 640 * Flags: 641 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates 642 * that this is LP cluster clock. 643 */ 644 struct tegra_clk_super_mux { 645 struct clk_hw hw; 646 void __iomem *reg; 647 u8 width; 648 u8 flags; 649 u8 div2_index; 650 u8 pllx_index; 651 spinlock_t *lock; 652 }; 653 654 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) 655 656 #define TEGRA_DIVIDER_2 BIT(0) 657 658 extern const struct clk_ops tegra_clk_super_ops; 659 struct clk *tegra_clk_register_super_mux(const char *name, 660 const char **parent_names, u8 num_parents, 661 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 662 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 663 664 /** 665 * struct clk_init_table - clock initialization table 666 * @clk_id: clock id as mentioned in device tree bindings 667 * @parent_id: parent clock id as mentioned in device tree bindings 668 * @rate: rate to set 669 * @state: enable/disable 670 */ 671 struct tegra_clk_init_table { 672 unsigned int clk_id; 673 unsigned int parent_id; 674 unsigned long rate; 675 int state; 676 }; 677 678 /** 679 * struct clk_duplicate - duplicate clocks 680 * @clk_id: clock id as mentioned in device tree bindings 681 * @lookup: duplicate lookup entry for the clock 682 */ 683 struct tegra_clk_duplicate { 684 int clk_id; 685 struct clk_lookup lookup; 686 }; 687 688 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ 689 { \ 690 .clk_id = _clk_id, \ 691 .lookup = { \ 692 .dev_id = _dev, \ 693 .con_id = _con, \ 694 }, \ 695 } 696 697 struct tegra_clk { 698 int dt_id; 699 bool present; 700 }; 701 702 struct tegra_devclk { 703 int dt_id; 704 char *dev_id; 705 char *con_id; 706 }; 707 708 void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long), 709 int (*deassert)(unsigned long)); 710 711 void tegra_init_from_table(struct tegra_clk_init_table *tbl, 712 struct clk *clks[], int clk_max); 713 714 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 715 struct clk *clks[], int clk_max); 716 717 struct tegra_clk_periph_regs *get_reg_bank(int clkid); 718 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); 719 720 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); 721 722 void tegra_add_of_provider(struct device_node *np); 723 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); 724 725 void tegra_audio_clk_init(void __iomem *clk_base, 726 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 727 struct tegra_audio_clk_info *audio_info, 728 unsigned int num_plls); 729 730 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, 731 struct tegra_clk *tegra_clks, 732 struct tegra_clk_pll_params *pll_params); 733 734 void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks); 735 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); 736 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, 737 unsigned long *input_freqs, unsigned int num, 738 unsigned int clk_m_div, unsigned long *osc_freq, 739 unsigned long *pll_ref_freq); 740 void tegra_super_clk_gen4_init(void __iomem *clk_base, 741 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 742 struct tegra_clk_pll_params *pll_params); 743 void tegra_super_clk_gen5_init(void __iomem *clk_base, 744 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 745 struct tegra_clk_pll_params *pll_params); 746 747 #ifdef CONFIG_TEGRA_CLK_EMC 748 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, 749 spinlock_t *lock); 750 #else 751 static inline struct clk *tegra_clk_register_emc(void __iomem *base, 752 struct device_node *np, 753 spinlock_t *lock) 754 { 755 return NULL; 756 } 757 #endif 758 759 void tegra114_clock_tune_cpu_trimmers_high(void); 760 void tegra114_clock_tune_cpu_trimmers_low(void); 761 void tegra114_clock_tune_cpu_trimmers_init(void); 762 void tegra114_clock_assert_dfll_dvco_reset(void); 763 void tegra114_clock_deassert_dfll_dvco_reset(void); 764 765 typedef void (*tegra_clk_apply_init_table_func)(void); 766 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 767 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll); 768 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate); 769 770 #endif /* TEGRA_CLK_H */ 771