clk-exynos5433.c (06d2f9dfa663367e8cc1690d7e5ce4113e5dbcc1) clk-exynos5433.c (2a1808a6c00fb6d75ebfa596add57638b9290926)
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *

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240
241PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
242 "oscclk", "ioclk_spdif_extclk", };
243PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
244 "mout_aud_pll_user_t",};
245PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
246 "mout_aud_pll_user_t",};
247
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *

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240
241PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
242 "oscclk", "ioclk_spdif_extclk", };
243PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
244 "mout_aud_pll_user_t",};
245PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
246 "mout_aud_pll_user_t",};
247
248PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
249
248static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
249 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
250};
251
252static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
253 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
254 FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
255 FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),

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390 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
391 MUX_SEL_TOP_PERIC1, 16, 1),
392 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
393 MUX_SEL_TOP_PERIC1, 12, 2),
394 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
395 MUX_SEL_TOP_PERIC1, 4, 2),
396 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
397 MUX_SEL_TOP_PERIC1, 0, 2),
250static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
251 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
252};
253
254static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
255 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
256 FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
257 FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),

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392 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
393 MUX_SEL_TOP_PERIC1, 16, 1),
394 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
395 MUX_SEL_TOP_PERIC1, 12, 2),
396 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
397 MUX_SEL_TOP_PERIC1, 4, 2),
398 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
399 MUX_SEL_TOP_PERIC1, 0, 2),
400
401 /* MUX_SEL_TOP_DISP */
402 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
403 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
398};
399
400static struct samsung_div_clock top_div_clks[] __initdata = {
401 /* DIV_TOP1 */
402 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
403 DIV_TOP1, 28, 3),
404 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
405 DIV_TOP1, 24, 3),

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1355 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1356 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1357 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1358 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1359 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1360 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1361 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1362 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
404};
405
406static struct samsung_div_clock top_div_clks[] __initdata = {
407 /* DIV_TOP1 */
408 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
409 DIV_TOP1, 28, 3),
410 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
411 DIV_TOP1, 24, 3),

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1361 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1362 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1363 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1364 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1365 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1366 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1367 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1368 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1369
1370 /* ENABLE_SCLK_TOP_DISP */
1371 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
1372 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
1373 CLK_IGNORE_UNUSED, 0),
1363};
1364
1365static struct samsung_cmu_info mif_cmu_info __initdata = {
1366 .pll_clks = mif_pll_clks,
1367 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1368 .mux_clks = mif_mux_clks,
1369 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1370 .div_clks = mif_div_clks,

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2017
2018static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2019{
2020 samsung_cmu_register_one(np, &g2d_cmu_info);
2021}
2022
2023CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2024 exynos5433_cmu_g2d_init);
1374};
1375
1376static struct samsung_cmu_info mif_cmu_info __initdata = {
1377 .pll_clks = mif_pll_clks,
1378 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1379 .mux_clks = mif_mux_clks,
1380 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1381 .div_clks = mif_div_clks,

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2028
2029static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2030{
2031 samsung_cmu_register_one(np, &g2d_cmu_info);
2032}
2033
2034CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2035 exynos5433_cmu_g2d_init);
2036
2037/*
2038 * Register offset definitions for CMU_DISP
2039 */
2040#define DISP_PLL_LOCK 0x0000
2041#define DISP_PLL_CON0 0x0100
2042#define DISP_PLL_CON1 0x0104
2043#define DISP_PLL_FREQ_DET 0x0108
2044#define MUX_SEL_DISP0 0x0200
2045#define MUX_SEL_DISP1 0x0204
2046#define MUX_SEL_DISP2 0x0208
2047#define MUX_SEL_DISP3 0x020c
2048#define MUX_SEL_DISP4 0x0210
2049#define MUX_ENABLE_DISP0 0x0300
2050#define MUX_ENABLE_DISP1 0x0304
2051#define MUX_ENABLE_DISP2 0x0308
2052#define MUX_ENABLE_DISP3 0x030c
2053#define MUX_ENABLE_DISP4 0x0310
2054#define MUX_STAT_DISP0 0x0400
2055#define MUX_STAT_DISP1 0x0404
2056#define MUX_STAT_DISP2 0x0408
2057#define MUX_STAT_DISP3 0x040c
2058#define MUX_STAT_DISP4 0x0410
2059#define MUX_IGNORE_DISP2 0x0508
2060#define DIV_DISP 0x0600
2061#define DIV_DISP_PLL_FREQ_DET 0x0604
2062#define DIV_STAT_DISP 0x0700
2063#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2064#define ENABLE_ACLK_DISP0 0x0800
2065#define ENABLE_ACLK_DISP1 0x0804
2066#define ENABLE_PCLK_DISP 0x0900
2067#define ENABLE_SCLK_DISP 0x0a00
2068#define ENABLE_IP_DISP0 0x0b00
2069#define ENABLE_IP_DISP1 0x0b04
2070#define CLKOUT_CMU_DISP 0x0c00
2071#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2072
2073static unsigned long disp_clk_regs[] __initdata = {
2074 DISP_PLL_LOCK,
2075 DISP_PLL_CON0,
2076 DISP_PLL_CON1,
2077 DISP_PLL_FREQ_DET,
2078 MUX_SEL_DISP0,
2079 MUX_SEL_DISP1,
2080 MUX_SEL_DISP2,
2081 MUX_SEL_DISP3,
2082 MUX_SEL_DISP4,
2083 MUX_ENABLE_DISP0,
2084 MUX_ENABLE_DISP1,
2085 MUX_ENABLE_DISP2,
2086 MUX_ENABLE_DISP3,
2087 MUX_ENABLE_DISP4,
2088 MUX_STAT_DISP0,
2089 MUX_STAT_DISP1,
2090 MUX_STAT_DISP2,
2091 MUX_STAT_DISP3,
2092 MUX_STAT_DISP4,
2093 MUX_IGNORE_DISP2,
2094 DIV_DISP,
2095 DIV_DISP_PLL_FREQ_DET,
2096 DIV_STAT_DISP,
2097 DIV_STAT_DISP_PLL_FREQ_DET,
2098 ENABLE_ACLK_DISP0,
2099 ENABLE_ACLK_DISP1,
2100 ENABLE_PCLK_DISP,
2101 ENABLE_SCLK_DISP,
2102 ENABLE_IP_DISP0,
2103 ENABLE_IP_DISP1,
2104 CLKOUT_CMU_DISP,
2105 CLKOUT_CMU_DISP_DIV_STAT,
2106};
2107
2108/* list of all parent clock list */
2109PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2110PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2111PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2112PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2113PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2114 "sclk_decon_tv_eclk_disp", };
2115PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2116 "sclk_decon_vclk_disp", };
2117PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2118 "sclk_decon_eclk_disp", };
2119PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2120 "sclk_decon_tv_vclk_disp", };
2121PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2122
2123PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2124 "phyclk_mipidphy1_bitclkdiv8_phy", };
2125PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2126 "phyclk_mipidphy1_rxclkesc0_phy", };
2127PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2128 "phyclk_mipidphy0_bitclkdiv8_phy", };
2129PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2130 "phyclk_mipidphy0_rxclkesc0_phy", };
2131PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2132 "phyclk_hdmiphy_tmds_clko_phy", };
2133PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2134 "phyclk_hdmiphy_pixel_clko_phy", };
2135
2136PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2137 "mout_sclk_dsim0_user", };
2138PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2139 "mout_sclk_decon_tv_eclk_user", };
2140PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2141 "mout_sclk_decon_vclk_user", };
2142PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2143 "mout_sclk_decon_eclk_user", };
2144
2145PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2146 "mout_sclk_dsim1_user", };
2147PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2148 "mout_phyclk_hdmiphy_pixel_clko_user",
2149 "mout_sclk_decon_tv_vclk_b_disp", };
2150PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2151 "mout_sclk_decon_tv_vclk_user", };
2152
2153static struct samsung_pll_clock disp_pll_clks[] __initdata = {
2154 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2155 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2156};
2157
2158static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
2159 /*
2160 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2161 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2162 * and sclk_decon_{vclk|tv_vclk}.
2163 */
2164 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2165 1, 2, 0),
2166 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2167 1, 2, 0),
2168};
2169
2170static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
2171 /* PHY clocks from MIPI_DPHY1 */
2172 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2173 188000000),
2174 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2175 100000000),
2176 /* PHY clocks from MIPI_DPHY0 */
2177 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2178 188000000),
2179 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2180 100000000),
2181 /* PHY clocks from HDMI_PHY */
2182 FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
2183 FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
2184};
2185
2186static struct samsung_mux_clock disp_mux_clks[] __initdata = {
2187 /* MUX_SEL_DISP0 */
2188 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2189 0, 1),
2190
2191 /* MUX_SEL_DISP1 */
2192 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2193 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2194 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2195 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2196 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2197 MUX_SEL_DISP1, 20, 1),
2198 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2199 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2200 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2201 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2202 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2203 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2204 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2205 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2206 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2207 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2208
2209 /* MUX_SEL_DISP2 */
2210 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2211 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2212 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2213 20, 1),
2214 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2215 "mout_phyclk_mipidphy1_rxclkesc0_user",
2216 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2217 16, 1),
2218 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2219 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2220 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2221 12, 1),
2222 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2223 "mout_phyclk_mipidphy0_rxclkesc0_user",
2224 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2225 8, 1),
2226 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2227 "mout_phyclk_hdmiphy_tmds_clko_user",
2228 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2229 4, 1),
2230 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2231 "mout_phyclk_hdmiphy_pixel_clko_user",
2232 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2233 0, 1),
2234
2235 /* MUX_SEL_DISP3 */
2236 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2237 MUX_SEL_DISP3, 12, 1),
2238 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2239 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2240 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2241 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2242 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2243 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2244
2245 /* MUX_SEL_DISP4 */
2246 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2247 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2248 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2249 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2250 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2251 "mout_sclk_decon_tv_vclk_c_disp",
2252 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2253 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2254 "mout_sclk_decon_tv_vclk_b_disp",
2255 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2256 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2257 "mout_sclk_decon_tv_vclk_a_disp",
2258 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2259};
2260
2261static struct samsung_div_clock disp_div_clks[] __initdata = {
2262 /* DIV_DISP */
2263 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2264 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2265 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2266 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2267 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2268 DIV_DISP, 16, 3),
2269 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2270 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2271 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2272 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2273 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2274 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2275 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2276 DIV_DISP, 0, 2),
2277};
2278
2279static struct samsung_gate_clock disp_gate_clks[] __initdata = {
2280 /* ENABLE_ACLK_DISP0 */
2281 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2282 ENABLE_ACLK_DISP0, 2, 0, 0),
2283 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2284 ENABLE_ACLK_DISP0, 0, 0, 0),
2285
2286 /* ENABLE_ACLK_DISP1 */
2287 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2288 ENABLE_ACLK_DISP1, 25, 0, 0),
2289 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2290 ENABLE_ACLK_DISP1, 24, 0, 0),
2291 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2292 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2293 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2294 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2295 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2296 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2297 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2298 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2299 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2300 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2301 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2302 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2303 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2304 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2305 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2306 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2307 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2308 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2309 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2310 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2311 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2312 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2313 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2314 "div_pclk_disp", ENABLE_ACLK_DISP1,
2315 12, CLK_IGNORE_UNUSED, 0),
2316 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2317 "div_pclk_disp", ENABLE_ACLK_DISP1,
2318 11, CLK_IGNORE_UNUSED, 0),
2319 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2320 "div_pclk_disp", ENABLE_ACLK_DISP1,
2321 10, CLK_IGNORE_UNUSED, 0),
2322 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2323 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2324 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2325 ENABLE_ACLK_DISP1, 7, 0, 0),
2326 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2327 ENABLE_ACLK_DISP1, 6, 0, 0),
2328 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2329 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2330 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2331 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2332 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2333 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2334 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2335 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2336 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2337 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2338 CLK_IGNORE_UNUSED, 0),
2339 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2340 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2341 0, CLK_IGNORE_UNUSED, 0),
2342
2343 /* ENABLE_PCLK_DISP */
2344 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2345 ENABLE_PCLK_DISP, 23, 0, 0),
2346 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2347 ENABLE_PCLK_DISP, 22, 0, 0),
2348 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2349 ENABLE_PCLK_DISP, 21, 0, 0),
2350 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2351 ENABLE_PCLK_DISP, 20, 0, 0),
2352 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2353 ENABLE_PCLK_DISP, 19, 0, 0),
2354 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2355 ENABLE_PCLK_DISP, 18, 0, 0),
2356 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2357 ENABLE_PCLK_DISP, 17, 0, 0),
2358 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2359 ENABLE_PCLK_DISP, 16, 0, 0),
2360 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2361 ENABLE_PCLK_DISP, 15, 0, 0),
2362 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2363 ENABLE_PCLK_DISP, 14, 0, 0),
2364 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2365 ENABLE_PCLK_DISP, 13, 0, 0),
2366 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2367 ENABLE_PCLK_DISP, 12, 0, 0),
2368 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2369 ENABLE_PCLK_DISP, 11, 0, 0),
2370 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2371 ENABLE_PCLK_DISP, 10, 0, 0),
2372 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2373 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2374 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2375 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2376 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2377 ENABLE_PCLK_DISP, 7, 0, 0),
2378 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2379 ENABLE_PCLK_DISP, 6, 0, 0),
2380 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2381 ENABLE_PCLK_DISP, 5, 0, 0),
2382 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2383 ENABLE_PCLK_DISP, 3, 0, 0),
2384 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2385 ENABLE_PCLK_DISP, 2, 0, 0),
2386 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2387 ENABLE_PCLK_DISP, 1, 0, 0),
2388
2389 /* ENABLE_SCLK_DISP */
2390 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2391 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2392 ENABLE_SCLK_DISP, 26, 0, 0),
2393 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2394 "mout_phyclk_mipidphy1_rxclkesc0_user",
2395 ENABLE_SCLK_DISP, 25, 0, 0),
2396 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2397 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2398 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2399 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2400 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2401 ENABLE_SCLK_DISP, 22, 0, 0),
2402 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2403 "div_sclk_decon_tv_vclk_disp",
2404 ENABLE_SCLK_DISP, 21, 0, 0),
2405 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2406 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2407 ENABLE_SCLK_DISP, 15, 0, 0),
2408 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2409 "mout_phyclk_mipidphy0_rxclkesc0_user",
2410 ENABLE_SCLK_DISP, 14, 0, 0),
2411 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2412 "mout_phyclk_hdmiphy_tmds_clko_user",
2413 ENABLE_SCLK_DISP, 13, 0, 0),
2414 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2415 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2416 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2417 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2418 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2419 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2420 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2421 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2422 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2423 ENABLE_SCLK_DISP, 7, 0, 0),
2424 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2425 ENABLE_SCLK_DISP, 6, 0, 0),
2426 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2427 ENABLE_SCLK_DISP, 5, 0, 0),
2428 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2429 "div_sclk_decon_tv_eclk_disp",
2430 ENABLE_SCLK_DISP, 4, 0, 0),
2431 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2432 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2433 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2434 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2435};
2436
2437static struct samsung_cmu_info disp_cmu_info __initdata = {
2438 .pll_clks = disp_pll_clks,
2439 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2440 .mux_clks = disp_mux_clks,
2441 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2442 .div_clks = disp_div_clks,
2443 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2444 .gate_clks = disp_gate_clks,
2445 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2446 .fixed_clks = disp_fixed_clks,
2447 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2448 .fixed_factor_clks = disp_fixed_factor_clks,
2449 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2450 .nr_clk_ids = DISP_NR_CLK,
2451 .clk_regs = disp_clk_regs,
2452 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2453};
2454
2455static void __init exynos5433_cmu_disp_init(struct device_node *np)
2456{
2457 samsung_cmu_register_one(np, &disp_cmu_info);
2458}
2459
2460CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2461 exynos5433_cmu_disp_init);