1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Common Clock Framework support for Exynos5443 SoC. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/clk-provider.h> 15 #include <linux/of.h> 16 17 #include <dt-bindings/clock/exynos5433.h> 18 19 #include "clk.h" 20 #include "clk-pll.h" 21 22 /* 23 * Register offset definitions for CMU_TOP 24 */ 25 #define ISP_PLL_LOCK 0x0000 26 #define AUD_PLL_LOCK 0x0004 27 #define ISP_PLL_CON0 0x0100 28 #define ISP_PLL_CON1 0x0104 29 #define ISP_PLL_FREQ_DET 0x0108 30 #define AUD_PLL_CON0 0x0110 31 #define AUD_PLL_CON1 0x0114 32 #define AUD_PLL_CON2 0x0118 33 #define AUD_PLL_FREQ_DET 0x011c 34 #define MUX_SEL_TOP0 0x0200 35 #define MUX_SEL_TOP1 0x0204 36 #define MUX_SEL_TOP2 0x0208 37 #define MUX_SEL_TOP3 0x020c 38 #define MUX_SEL_TOP4 0x0210 39 #define MUX_SEL_TOP_MSCL 0x0220 40 #define MUX_SEL_TOP_CAM1 0x0224 41 #define MUX_SEL_TOP_DISP 0x0228 42 #define MUX_SEL_TOP_FSYS0 0x0230 43 #define MUX_SEL_TOP_FSYS1 0x0234 44 #define MUX_SEL_TOP_PERIC0 0x0238 45 #define MUX_SEL_TOP_PERIC1 0x023c 46 #define MUX_ENABLE_TOP0 0x0300 47 #define MUX_ENABLE_TOP1 0x0304 48 #define MUX_ENABLE_TOP2 0x0308 49 #define MUX_ENABLE_TOP3 0x030c 50 #define MUX_ENABLE_TOP4 0x0310 51 #define MUX_ENABLE_TOP_MSCL 0x0320 52 #define MUX_ENABLE_TOP_CAM1 0x0324 53 #define MUX_ENABLE_TOP_DISP 0x0328 54 #define MUX_ENABLE_TOP_FSYS0 0x0330 55 #define MUX_ENABLE_TOP_FSYS1 0x0334 56 #define MUX_ENABLE_TOP_PERIC0 0x0338 57 #define MUX_ENABLE_TOP_PERIC1 0x033c 58 #define MUX_STAT_TOP0 0x0400 59 #define MUX_STAT_TOP1 0x0404 60 #define MUX_STAT_TOP2 0x0408 61 #define MUX_STAT_TOP3 0x040c 62 #define MUX_STAT_TOP4 0x0410 63 #define MUX_STAT_TOP_MSCL 0x0420 64 #define MUX_STAT_TOP_CAM1 0x0424 65 #define MUX_STAT_TOP_FSYS0 0x0430 66 #define MUX_STAT_TOP_FSYS1 0x0434 67 #define MUX_STAT_TOP_PERIC0 0x0438 68 #define MUX_STAT_TOP_PERIC1 0x043c 69 #define DIV_TOP0 0x0600 70 #define DIV_TOP1 0x0604 71 #define DIV_TOP2 0x0608 72 #define DIV_TOP3 0x060c 73 #define DIV_TOP4 0x0610 74 #define DIV_TOP_MSCL 0x0618 75 #define DIV_TOP_CAM10 0x061c 76 #define DIV_TOP_CAM11 0x0620 77 #define DIV_TOP_FSYS0 0x062c 78 #define DIV_TOP_FSYS1 0x0630 79 #define DIV_TOP_FSYS2 0x0634 80 #define DIV_TOP_PERIC0 0x0638 81 #define DIV_TOP_PERIC1 0x063c 82 #define DIV_TOP_PERIC2 0x0640 83 #define DIV_TOP_PERIC3 0x0644 84 #define DIV_TOP_PERIC4 0x0648 85 #define DIV_TOP_PLL_FREQ_DET 0x064c 86 #define DIV_STAT_TOP0 0x0700 87 #define DIV_STAT_TOP1 0x0704 88 #define DIV_STAT_TOP2 0x0708 89 #define DIV_STAT_TOP3 0x070c 90 #define DIV_STAT_TOP4 0x0710 91 #define DIV_STAT_TOP_MSCL 0x0718 92 #define DIV_STAT_TOP_CAM10 0x071c 93 #define DIV_STAT_TOP_CAM11 0x0720 94 #define DIV_STAT_TOP_FSYS0 0x072c 95 #define DIV_STAT_TOP_FSYS1 0x0730 96 #define DIV_STAT_TOP_FSYS2 0x0734 97 #define DIV_STAT_TOP_PERIC0 0x0738 98 #define DIV_STAT_TOP_PERIC1 0x073c 99 #define DIV_STAT_TOP_PERIC2 0x0740 100 #define DIV_STAT_TOP_PERIC3 0x0744 101 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c 102 #define ENABLE_ACLK_TOP 0x0800 103 #define ENABLE_SCLK_TOP 0x0a00 104 #define ENABLE_SCLK_TOP_MSCL 0x0a04 105 #define ENABLE_SCLK_TOP_CAM1 0x0a08 106 #define ENABLE_SCLK_TOP_DISP 0x0a0c 107 #define ENABLE_SCLK_TOP_FSYS 0x0a10 108 #define ENABLE_SCLK_TOP_PERIC 0x0a14 109 #define ENABLE_IP_TOP 0x0b00 110 #define ENABLE_CMU_TOP 0x0c00 111 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04 112 113 static unsigned long top_clk_regs[] __initdata = { 114 ISP_PLL_LOCK, 115 AUD_PLL_LOCK, 116 ISP_PLL_CON0, 117 ISP_PLL_CON1, 118 ISP_PLL_FREQ_DET, 119 AUD_PLL_CON0, 120 AUD_PLL_CON1, 121 AUD_PLL_CON2, 122 AUD_PLL_FREQ_DET, 123 MUX_SEL_TOP0, 124 MUX_SEL_TOP1, 125 MUX_SEL_TOP2, 126 MUX_SEL_TOP3, 127 MUX_SEL_TOP4, 128 MUX_SEL_TOP_MSCL, 129 MUX_SEL_TOP_CAM1, 130 MUX_SEL_TOP_DISP, 131 MUX_SEL_TOP_FSYS0, 132 MUX_SEL_TOP_FSYS1, 133 MUX_SEL_TOP_PERIC0, 134 MUX_SEL_TOP_PERIC1, 135 MUX_ENABLE_TOP0, 136 MUX_ENABLE_TOP1, 137 MUX_ENABLE_TOP2, 138 MUX_ENABLE_TOP3, 139 MUX_ENABLE_TOP4, 140 MUX_ENABLE_TOP_MSCL, 141 MUX_ENABLE_TOP_CAM1, 142 MUX_ENABLE_TOP_DISP, 143 MUX_ENABLE_TOP_FSYS0, 144 MUX_ENABLE_TOP_FSYS1, 145 MUX_ENABLE_TOP_PERIC0, 146 MUX_ENABLE_TOP_PERIC1, 147 MUX_STAT_TOP0, 148 MUX_STAT_TOP1, 149 MUX_STAT_TOP2, 150 MUX_STAT_TOP3, 151 MUX_STAT_TOP4, 152 MUX_STAT_TOP_MSCL, 153 MUX_STAT_TOP_CAM1, 154 MUX_STAT_TOP_FSYS0, 155 MUX_STAT_TOP_FSYS1, 156 MUX_STAT_TOP_PERIC0, 157 MUX_STAT_TOP_PERIC1, 158 DIV_TOP0, 159 DIV_TOP1, 160 DIV_TOP2, 161 DIV_TOP3, 162 DIV_TOP4, 163 DIV_TOP_MSCL, 164 DIV_TOP_CAM10, 165 DIV_TOP_CAM11, 166 DIV_TOP_FSYS0, 167 DIV_TOP_FSYS1, 168 DIV_TOP_FSYS2, 169 DIV_TOP_PERIC0, 170 DIV_TOP_PERIC1, 171 DIV_TOP_PERIC2, 172 DIV_TOP_PERIC3, 173 DIV_TOP_PERIC4, 174 DIV_TOP_PLL_FREQ_DET, 175 DIV_STAT_TOP0, 176 DIV_STAT_TOP1, 177 DIV_STAT_TOP2, 178 DIV_STAT_TOP3, 179 DIV_STAT_TOP4, 180 DIV_STAT_TOP_MSCL, 181 DIV_STAT_TOP_CAM10, 182 DIV_STAT_TOP_CAM11, 183 DIV_STAT_TOP_FSYS0, 184 DIV_STAT_TOP_FSYS1, 185 DIV_STAT_TOP_FSYS2, 186 DIV_STAT_TOP_PERIC0, 187 DIV_STAT_TOP_PERIC1, 188 DIV_STAT_TOP_PERIC2, 189 DIV_STAT_TOP_PERIC3, 190 DIV_STAT_TOP_PLL_FREQ_DET, 191 ENABLE_ACLK_TOP, 192 ENABLE_SCLK_TOP, 193 ENABLE_SCLK_TOP_MSCL, 194 ENABLE_SCLK_TOP_CAM1, 195 ENABLE_SCLK_TOP_DISP, 196 ENABLE_SCLK_TOP_FSYS, 197 ENABLE_SCLK_TOP_PERIC, 198 ENABLE_IP_TOP, 199 ENABLE_CMU_TOP, 200 ENABLE_CMU_TOP_DIV_STAT, 201 }; 202 203 /* list of all parent clock list */ 204 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; 205 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; 206 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", }; 207 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", }; 208 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", }; 209 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", }; 210 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", }; 211 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", }; 212 213 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",}; 214 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",}; 215 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a", 216 "mout_mfc_pll_user", }; 217 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", }; 218 219 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b", 220 "mout_mphy_pll_user", }; 221 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a", 222 "mout_bus_pll_user", }; 223 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", }; 224 225 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user", 226 "mout_mphy_pll_user", }; 227 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a", 228 "mout_mphy_pll_user", }; 229 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a", 230 "mout_mphy_pll_user", }; 231 232 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",}; 233 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", }; 234 235 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",}; 236 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",}; 237 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", }; 238 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",}; 239 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", }; 240 241 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1", 242 "oscclk", "ioclk_spdif_extclk", }; 243 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk", 244 "mout_aud_pll_user_t",}; 245 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", 246 "mout_aud_pll_user_t",}; 247 248 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; 249 250 static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = { 251 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), 252 }; 253 254 static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = { 255 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ 256 FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000), 257 FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000), 258 /* Xi2s1SDI input clock for SPDIF */ 259 FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000), 260 /* XspiCLK[4:0] input clock for SPI */ 261 FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000), 262 FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000), 263 FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000), 264 FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000), 265 FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000), 266 /* Xi2s1SCLK input clock for I2S1_BCLK */ 267 FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), 268 }; 269 270 static struct samsung_mux_clock top_mux_clks[] __initdata = { 271 /* MUX_SEL_TOP0 */ 272 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, 273 4, 1), 274 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0, 275 0, 1), 276 277 /* MUX_SEL_TOP1 */ 278 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t", 279 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1), 280 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p, 281 MUX_SEL_TOP1, 8, 1), 282 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p, 283 MUX_SEL_TOP1, 4, 1), 284 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p, 285 MUX_SEL_TOP1, 0, 1), 286 287 /* MUX_SEL_TOP2 */ 288 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400", 289 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1), 290 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333", 291 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1), 292 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b", 293 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1), 294 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a", 295 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1), 296 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400", 297 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1), 298 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400", 299 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1), 300 301 /* MUX_SEL_TOP3 */ 302 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400", 303 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1), 304 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b", 305 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1), 306 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a", 307 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1), 308 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", 309 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1), 310 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b", 311 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1), 312 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a", 313 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1), 314 315 /* MUX_SEL_TOP4 */ 316 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c", 317 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1), 318 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b", 319 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1), 320 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a", 321 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1), 322 323 /* MUX_SEL_TOP_MSCL */ 324 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p, 325 MUX_SEL_TOP_MSCL, 8, 1), 326 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p, 327 MUX_SEL_TOP_MSCL, 4, 1), 328 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p, 329 MUX_SEL_TOP_MSCL, 0, 1), 330 331 /* MUX_SEL_TOP_CAM1 */ 332 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2", 333 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1), 334 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1", 335 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1), 336 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0", 337 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1), 338 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart", 339 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1), 340 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1", 341 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1), 342 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0", 343 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1), 344 345 /* MUX_SEL_TOP_FSYS0 */ 346 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p, 347 MUX_SEL_TOP_FSYS0, 28, 1), 348 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p, 349 MUX_SEL_TOP_FSYS0, 24, 1), 350 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p, 351 MUX_SEL_TOP_FSYS0, 20, 1), 352 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p, 353 MUX_SEL_TOP_FSYS0, 16, 1), 354 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p, 355 MUX_SEL_TOP_FSYS0, 12, 1), 356 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p, 357 MUX_SEL_TOP_FSYS0, 8, 1), 358 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p, 359 MUX_SEL_TOP_FSYS0, 4, 1), 360 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p, 361 MUX_SEL_TOP_FSYS0, 0, 1), 362 363 /* MUX_SEL_TOP_FSYS1 */ 364 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p, 365 MUX_SEL_TOP_FSYS1, 12, 1), 366 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro", 367 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1), 368 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30", 369 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1), 370 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30", 371 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1), 372 373 /* MUX_SEL_TOP_PERIC0 */ 374 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p, 375 MUX_SEL_TOP_PERIC0, 28, 1), 376 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p, 377 MUX_SEL_TOP_PERIC0, 24, 1), 378 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p, 379 MUX_SEL_TOP_PERIC0, 20, 1), 380 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p, 381 MUX_SEL_TOP_PERIC0, 16, 1), 382 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p, 383 MUX_SEL_TOP_PERIC0, 12, 1), 384 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p, 385 MUX_SEL_TOP_PERIC0, 8, 1), 386 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p, 387 MUX_SEL_TOP_PERIC0, 4, 1), 388 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p, 389 MUX_SEL_TOP_PERIC0, 0, 1), 390 391 /* MUX_SEL_TOP_PERIC1 */ 392 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p, 393 MUX_SEL_TOP_PERIC1, 16, 1), 394 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, 395 MUX_SEL_TOP_PERIC1, 12, 2), 396 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p, 397 MUX_SEL_TOP_PERIC1, 4, 2), 398 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p, 399 MUX_SEL_TOP_PERIC1, 0, 2), 400 401 /* MUX_SEL_TOP_DISP */ 402 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", 403 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), 404 }; 405 406 static struct samsung_div_clock top_div_clks[] __initdata = { 407 /* DIV_TOP1 */ 408 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333", 409 DIV_TOP1, 28, 3), 410 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333", 411 DIV_TOP1, 24, 3), 412 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400", 413 DIV_TOP1, 20, 3), 414 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c", 415 DIV_TOP1, 12, 3), 416 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user", 417 DIV_TOP1, 8, 3), 418 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b", 419 DIV_TOP1, 0, 3), 420 421 /* DIV_TOP2 */ 422 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user", 423 DIV_TOP2, 0, 3), 424 425 /* DIV_TOP3 */ 426 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266", 427 "mout_bus_pll_user", DIV_TOP3, 24, 3), 428 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200", 429 "mout_bus_pll_user", DIV_TOP3, 20, 3), 430 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266", 431 "mout_bus_pll_user", DIV_TOP3, 16, 3), 432 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b", 433 "div_aclk_peric_66_a", DIV_TOP3, 12, 3), 434 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a", 435 "mout_bus_pll_user", DIV_TOP3, 8, 3), 436 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b", 437 "div_aclk_peris_66_a", DIV_TOP3, 4, 3), 438 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a", 439 "mout_bus_pll_user", DIV_TOP3, 0, 3), 440 441 /* DIV_TOP_FSYS0 */ 442 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a", 443 DIV_TOP_FSYS0, 16, 8), 444 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b", 445 DIV_TOP_FSYS0, 12, 4), 446 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a", 447 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0), 448 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d", 449 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0), 450 451 /* DIV_TOP_FSYS1 */ 452 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a", 453 DIV_TOP_FSYS1, 4, 8), 454 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b", 455 DIV_TOP_FSYS1, 0, 4), 456 457 /* DIV_TOP_PERIC0 */ 458 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a", 459 DIV_TOP_PERIC0, 16, 8), 460 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1", 461 DIV_TOP_PERIC0, 12, 4), 462 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a", 463 DIV_TOP_PERIC0, 4, 8), 464 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0", 465 DIV_TOP_PERIC0, 0, 4), 466 467 /* DIV_TOP_PERIC1 */ 468 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a", 469 DIV_TOP_PERIC1, 4, 8), 470 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2", 471 DIV_TOP_PERIC1, 0, 4), 472 473 /* DIV_TOP_PERIC2 */ 474 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2", 475 DIV_TOP_PERIC2, 8, 4), 476 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0", 477 DIV_TOP_PERIC2, 4, 4), 478 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1", 479 DIV_TOP_PERIC2, 0, 4), 480 481 /* DIV_TOP_PERIC3 */ 482 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1", 483 DIV_TOP_PERIC3, 16, 6), 484 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1", 485 DIV_TOP_PERIC3, 8, 8), 486 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1", 487 DIV_TOP_PERIC3, 4, 4), 488 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0", 489 DIV_TOP_PERIC3, 0, 4), 490 491 /* DIV_TOP_PERIC4 */ 492 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a", 493 DIV_TOP_PERIC4, 16, 8), 494 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4", 495 DIV_TOP_PERIC4, 12, 4), 496 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a", 497 DIV_TOP_PERIC4, 4, 8), 498 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3", 499 DIV_TOP_PERIC4, 0, 4), 500 }; 501 502 static struct samsung_gate_clock top_gate_clks[] __initdata = { 503 /* ENABLE_ACLK_TOP */ 504 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b", 505 ENABLE_ACLK_TOP, 22, 506 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 507 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b", 508 ENABLE_ACLK_TOP, 21, 509 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 510 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200", 511 ENABLE_ACLK_TOP, 18, 512 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 513 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", 514 ENABLE_ACLK_TOP, 2, 515 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 516 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400", 517 ENABLE_ACLK_TOP, 0, 518 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 519 520 /* ENABLE_SCLK_TOP_FSYS */ 521 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", 522 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), 523 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", 524 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0), 525 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b", 526 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0), 527 528 /* ENABLE_SCLK_TOP_PERIC */ 529 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b", 530 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0), 531 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b", 532 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0), 533 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif", 534 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0), 535 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1", 536 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0), 537 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", 538 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), 539 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", 540 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0), 541 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", 542 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0), 543 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", 544 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0), 545 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", 546 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), 547 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", 548 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0), 549 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b", 550 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0), 551 552 /* MUX_ENABLE_TOP_PERIC1 */ 553 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus", 554 MUX_ENABLE_TOP_PERIC1, 16, 0, 0), 555 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1", 556 MUX_ENABLE_TOP_PERIC1, 4, 0, 0), 557 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0", 558 MUX_ENABLE_TOP_PERIC1, 0, 0, 0), 559 }; 560 561 /* 562 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL 563 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL 564 */ 565 static struct samsung_pll_rate_table exynos5443_pll_rates[] = { 566 PLL_35XX_RATE(2500000000U, 625, 6, 0), 567 PLL_35XX_RATE(2400000000U, 500, 5, 0), 568 PLL_35XX_RATE(2300000000U, 575, 6, 0), 569 PLL_35XX_RATE(2200000000U, 550, 6, 0), 570 PLL_35XX_RATE(2100000000U, 350, 4, 0), 571 PLL_35XX_RATE(2000000000U, 500, 6, 0), 572 PLL_35XX_RATE(1900000000U, 475, 6, 0), 573 PLL_35XX_RATE(1800000000U, 375, 5, 0), 574 PLL_35XX_RATE(1700000000U, 425, 6, 0), 575 PLL_35XX_RATE(1600000000U, 400, 6, 0), 576 PLL_35XX_RATE(1500000000U, 250, 4, 0), 577 PLL_35XX_RATE(1400000000U, 350, 6, 0), 578 PLL_35XX_RATE(1332000000U, 222, 4, 0), 579 PLL_35XX_RATE(1300000000U, 325, 6, 0), 580 PLL_35XX_RATE(1200000000U, 500, 5, 1), 581 PLL_35XX_RATE(1100000000U, 550, 6, 1), 582 PLL_35XX_RATE(1086000000U, 362, 4, 1), 583 PLL_35XX_RATE(1066000000U, 533, 6, 1), 584 PLL_35XX_RATE(1000000000U, 500, 6, 1), 585 PLL_35XX_RATE(933000000U, 311, 4, 1), 586 PLL_35XX_RATE(921000000U, 307, 4, 1), 587 PLL_35XX_RATE(900000000U, 375, 5, 1), 588 PLL_35XX_RATE(825000000U, 275, 4, 1), 589 PLL_35XX_RATE(800000000U, 400, 6, 1), 590 PLL_35XX_RATE(733000000U, 733, 12, 1), 591 PLL_35XX_RATE(700000000U, 360, 6, 1), 592 PLL_35XX_RATE(667000000U, 222, 4, 1), 593 PLL_35XX_RATE(633000000U, 211, 4, 1), 594 PLL_35XX_RATE(600000000U, 500, 5, 2), 595 PLL_35XX_RATE(552000000U, 460, 5, 2), 596 PLL_35XX_RATE(550000000U, 550, 6, 2), 597 PLL_35XX_RATE(543000000U, 362, 4, 2), 598 PLL_35XX_RATE(533000000U, 533, 6, 2), 599 PLL_35XX_RATE(500000000U, 500, 6, 2), 600 PLL_35XX_RATE(444000000U, 370, 5, 2), 601 PLL_35XX_RATE(420000000U, 350, 5, 2), 602 PLL_35XX_RATE(400000000U, 400, 6, 2), 603 PLL_35XX_RATE(350000000U, 360, 6, 2), 604 PLL_35XX_RATE(333000000U, 222, 4, 2), 605 PLL_35XX_RATE(300000000U, 500, 5, 3), 606 PLL_35XX_RATE(266000000U, 532, 6, 3), 607 PLL_35XX_RATE(200000000U, 400, 6, 3), 608 PLL_35XX_RATE(166000000U, 332, 6, 3), 609 PLL_35XX_RATE(160000000U, 320, 6, 3), 610 PLL_35XX_RATE(133000000U, 552, 6, 4), 611 PLL_35XX_RATE(100000000U, 400, 6, 4), 612 { /* sentinel */ } 613 }; 614 615 /* AUD_PLL */ 616 static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { 617 PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 618 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), 619 PLL_36XX_RATE(384000000U, 128, 2, 2, 0), 620 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), 621 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), 622 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), 623 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), 624 PLL_36XX_RATE(288000000U, 96, 1, 3, 0), 625 PLL_36XX_RATE(252000000U, 84, 1, 3, 0), 626 { /* sentinel */ } 627 }; 628 629 static struct samsung_pll_clock top_pll_clks[] __initdata = { 630 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", 631 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates), 632 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 633 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates), 634 }; 635 636 static struct samsung_cmu_info top_cmu_info __initdata = { 637 .pll_clks = top_pll_clks, 638 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 639 .mux_clks = top_mux_clks, 640 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 641 .div_clks = top_div_clks, 642 .nr_div_clks = ARRAY_SIZE(top_div_clks), 643 .gate_clks = top_gate_clks, 644 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 645 .fixed_clks = top_fixed_clks, 646 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), 647 .fixed_factor_clks = top_fixed_factor_clks, 648 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), 649 .nr_clk_ids = TOP_NR_CLK, 650 .clk_regs = top_clk_regs, 651 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 652 }; 653 654 static void __init exynos5433_cmu_top_init(struct device_node *np) 655 { 656 samsung_cmu_register_one(np, &top_cmu_info); 657 } 658 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", 659 exynos5433_cmu_top_init); 660 661 /* 662 * Register offset definitions for CMU_CPIF 663 */ 664 #define MPHY_PLL_LOCK 0x0000 665 #define MPHY_PLL_CON0 0x0100 666 #define MPHY_PLL_CON1 0x0104 667 #define MPHY_PLL_FREQ_DET 0x010c 668 #define MUX_SEL_CPIF0 0x0200 669 #define DIV_CPIF 0x0600 670 #define ENABLE_SCLK_CPIF 0x0a00 671 672 static unsigned long cpif_clk_regs[] __initdata = { 673 MPHY_PLL_LOCK, 674 MPHY_PLL_CON0, 675 MPHY_PLL_CON1, 676 MPHY_PLL_FREQ_DET, 677 MUX_SEL_CPIF0, 678 ENABLE_SCLK_CPIF, 679 }; 680 681 /* list of all parent clock list */ 682 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; 683 684 static struct samsung_pll_clock cpif_pll_clks[] __initdata = { 685 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", 686 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates), 687 }; 688 689 static struct samsung_mux_clock cpif_mux_clks[] __initdata = { 690 /* MUX_SEL_CPIF0 */ 691 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, 692 0, 1), 693 }; 694 695 static struct samsung_div_clock cpif_div_clks[] __initdata = { 696 /* DIV_CPIF */ 697 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, 698 0, 6), 699 }; 700 701 static struct samsung_gate_clock cpif_gate_clks[] __initdata = { 702 /* ENABLE_SCLK_CPIF */ 703 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", 704 ENABLE_SCLK_CPIF, 9, 0, 0), 705 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", 706 ENABLE_SCLK_CPIF, 4, 0, 0), 707 }; 708 709 static struct samsung_cmu_info cpif_cmu_info __initdata = { 710 .pll_clks = cpif_pll_clks, 711 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), 712 .mux_clks = cpif_mux_clks, 713 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks), 714 .div_clks = cpif_div_clks, 715 .nr_div_clks = ARRAY_SIZE(cpif_div_clks), 716 .gate_clks = cpif_gate_clks, 717 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), 718 .nr_clk_ids = CPIF_NR_CLK, 719 .clk_regs = cpif_clk_regs, 720 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), 721 }; 722 723 static void __init exynos5433_cmu_cpif_init(struct device_node *np) 724 { 725 samsung_cmu_register_one(np, &cpif_cmu_info); 726 } 727 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", 728 exynos5433_cmu_cpif_init); 729 730 /* 731 * Register offset definitions for CMU_MIF 732 */ 733 #define MEM0_PLL_LOCK 0x0000 734 #define MEM1_PLL_LOCK 0x0004 735 #define BUS_PLL_LOCK 0x0008 736 #define MFC_PLL_LOCK 0x000c 737 #define MEM0_PLL_CON0 0x0100 738 #define MEM0_PLL_CON1 0x0104 739 #define MEM0_PLL_FREQ_DET 0x010c 740 #define MEM1_PLL_CON0 0x0110 741 #define MEM1_PLL_CON1 0x0114 742 #define MEM1_PLL_FREQ_DET 0x011c 743 #define BUS_PLL_CON0 0x0120 744 #define BUS_PLL_CON1 0x0124 745 #define BUS_PLL_FREQ_DET 0x012c 746 #define MFC_PLL_CON0 0x0130 747 #define MFC_PLL_CON1 0x0134 748 #define MFC_PLL_FREQ_DET 0x013c 749 #define MUX_SEL_MIF0 0x0200 750 #define MUX_SEL_MIF1 0x0204 751 #define MUX_SEL_MIF2 0x0208 752 #define MUX_SEL_MIF3 0x020c 753 #define MUX_SEL_MIF4 0x0210 754 #define MUX_SEL_MIF5 0x0214 755 #define MUX_SEL_MIF6 0x0218 756 #define MUX_SEL_MIF7 0x021c 757 #define MUX_ENABLE_MIF0 0x0300 758 #define MUX_ENABLE_MIF1 0x0304 759 #define MUX_ENABLE_MIF2 0x0308 760 #define MUX_ENABLE_MIF3 0x030c 761 #define MUX_ENABLE_MIF4 0x0310 762 #define MUX_ENABLE_MIF5 0x0314 763 #define MUX_ENABLE_MIF6 0x0318 764 #define MUX_ENABLE_MIF7 0x031c 765 #define MUX_STAT_MIF0 0x0400 766 #define MUX_STAT_MIF1 0x0404 767 #define MUX_STAT_MIF2 0x0408 768 #define MUX_STAT_MIF3 0x040c 769 #define MUX_STAT_MIF4 0x0410 770 #define MUX_STAT_MIF5 0x0414 771 #define MUX_STAT_MIF6 0x0418 772 #define MUX_STAT_MIF7 0x041c 773 #define DIV_MIF1 0x0604 774 #define DIV_MIF2 0x0608 775 #define DIV_MIF3 0x060c 776 #define DIV_MIF4 0x0610 777 #define DIV_MIF5 0x0614 778 #define DIV_MIF_PLL_FREQ_DET 0x0618 779 #define DIV_STAT_MIF1 0x0704 780 #define DIV_STAT_MIF2 0x0708 781 #define DIV_STAT_MIF3 0x070c 782 #define DIV_STAT_MIF4 0x0710 783 #define DIV_STAT_MIF5 0x0714 784 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718 785 #define ENABLE_ACLK_MIF0 0x0800 786 #define ENABLE_ACLK_MIF1 0x0804 787 #define ENABLE_ACLK_MIF2 0x0808 788 #define ENABLE_ACLK_MIF3 0x080c 789 #define ENABLE_PCLK_MIF 0x0900 790 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904 791 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908 792 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c 793 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910 794 #define ENABLE_SCLK_MIF 0x0a00 795 #define ENABLE_IP_MIF0 0x0b00 796 #define ENABLE_IP_MIF1 0x0b04 797 #define ENABLE_IP_MIF2 0x0b08 798 #define ENABLE_IP_MIF3 0x0b0c 799 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10 800 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14 801 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18 802 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c 803 #define CLKOUT_CMU_MIF 0x0c00 804 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 805 #define DREX_FREQ_CTRL0 0x1000 806 #define DREX_FREQ_CTRL1 0x1004 807 #define PAUSE 0x1008 808 #define DDRPHY_LOCK_CTRL 0x100c 809 810 static unsigned long mif_clk_regs[] __initdata = { 811 MEM0_PLL_LOCK, 812 MEM1_PLL_LOCK, 813 BUS_PLL_LOCK, 814 MFC_PLL_LOCK, 815 MEM0_PLL_CON0, 816 MEM0_PLL_CON1, 817 MEM0_PLL_FREQ_DET, 818 MEM1_PLL_CON0, 819 MEM1_PLL_CON1, 820 MEM1_PLL_FREQ_DET, 821 BUS_PLL_CON0, 822 BUS_PLL_CON1, 823 BUS_PLL_FREQ_DET, 824 MFC_PLL_CON0, 825 MFC_PLL_CON1, 826 MFC_PLL_FREQ_DET, 827 MUX_SEL_MIF0, 828 MUX_SEL_MIF1, 829 MUX_SEL_MIF2, 830 MUX_SEL_MIF3, 831 MUX_SEL_MIF4, 832 MUX_SEL_MIF5, 833 MUX_SEL_MIF6, 834 MUX_SEL_MIF7, 835 MUX_ENABLE_MIF0, 836 MUX_ENABLE_MIF1, 837 MUX_ENABLE_MIF2, 838 MUX_ENABLE_MIF3, 839 MUX_ENABLE_MIF4, 840 MUX_ENABLE_MIF5, 841 MUX_ENABLE_MIF6, 842 MUX_ENABLE_MIF7, 843 MUX_STAT_MIF0, 844 MUX_STAT_MIF1, 845 MUX_STAT_MIF2, 846 MUX_STAT_MIF3, 847 MUX_STAT_MIF4, 848 MUX_STAT_MIF5, 849 MUX_STAT_MIF6, 850 MUX_STAT_MIF7, 851 DIV_MIF1, 852 DIV_MIF2, 853 DIV_MIF3, 854 DIV_MIF4, 855 DIV_MIF5, 856 DIV_MIF_PLL_FREQ_DET, 857 DIV_STAT_MIF1, 858 DIV_STAT_MIF2, 859 DIV_STAT_MIF3, 860 DIV_STAT_MIF4, 861 DIV_STAT_MIF5, 862 DIV_STAT_MIF_PLL_FREQ_DET, 863 ENABLE_ACLK_MIF0, 864 ENABLE_ACLK_MIF1, 865 ENABLE_ACLK_MIF2, 866 ENABLE_ACLK_MIF3, 867 ENABLE_PCLK_MIF, 868 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 869 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 870 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 871 ENABLE_PCLK_MIF_SECURE_RTC, 872 ENABLE_SCLK_MIF, 873 ENABLE_IP_MIF0, 874 ENABLE_IP_MIF1, 875 ENABLE_IP_MIF2, 876 ENABLE_IP_MIF3, 877 ENABLE_IP_MIF_SECURE_DREX0_TZ, 878 ENABLE_IP_MIF_SECURE_DREX1_TZ, 879 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT, 880 ENABLE_IP_MIF_SECURE_RTC, 881 CLKOUT_CMU_MIF, 882 CLKOUT_CMU_MIF_DIV_STAT, 883 DREX_FREQ_CTRL0, 884 DREX_FREQ_CTRL1, 885 PAUSE, 886 DDRPHY_LOCK_CTRL, 887 }; 888 889 static struct samsung_pll_clock mif_pll_clks[] __initdata = { 890 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", 891 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates), 892 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", 893 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates), 894 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", 895 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates), 896 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", 897 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), 898 }; 899 900 /* list of all parent clock list */ 901 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", }; 902 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", }; 903 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", }; 904 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", }; 905 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", }; 906 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", }; 907 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", }; 908 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", }; 909 910 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", }; 911 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", }; 912 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", }; 913 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", }; 914 915 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", }; 916 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",}; 917 918 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a", 919 "mout_bus_pll_div2", }; 920 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", }; 921 922 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b", 923 "sclk_mphy_pll", }; 924 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a", 925 "mout_mfc_pll_div2", }; 926 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", }; 927 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b", 928 "sclk_mphy_pll", }; 929 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a", 930 "mout_mfc_pll_div2", }; 931 932 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b", 933 "sclk_mphy_pll", }; 934 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a", 935 "mout_mfc_pll_div2", }; 936 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", }; 937 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", }; 938 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", }; 939 940 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", }; 941 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" }; 942 943 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b", 944 "sclk_mphy_pll", }; 945 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", 946 "mout_mfc_pll_div2", }; 947 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; 948 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; 949 950 static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = { 951 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ 952 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), 953 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), 954 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0), 955 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), 956 }; 957 958 static struct samsung_mux_clock mif_mux_clks[] __initdata = { 959 /* MUX_SEL_MIF0 */ 960 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, 961 MUX_SEL_MIF0, 28, 1), 962 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p, 963 MUX_SEL_MIF0, 24, 1), 964 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p, 965 MUX_SEL_MIF0, 20, 1), 966 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p, 967 MUX_SEL_MIF0, 16, 1), 968 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0, 969 12, 1), 970 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0, 971 8, 1), 972 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0, 973 4, 1), 974 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0, 975 0, 1), 976 977 /* MUX_SEL_MIF1 */ 978 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p, 979 MUX_SEL_MIF1, 24, 1), 980 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p, 981 MUX_SEL_MIF1, 20, 1), 982 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p, 983 MUX_SEL_MIF1, 16, 1), 984 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p, 985 MUX_SEL_MIF1, 12, 1), 986 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p, 987 MUX_SEL_MIF1, 8, 1), 988 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p, 989 MUX_SEL_MIF1, 4, 1), 990 991 /* MUX_SEL_MIF2 */ 992 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200", 993 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1), 994 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400", 995 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1), 996 997 /* MUX_SEL_MIF3 */ 998 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b", 999 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1), 1000 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a", 1001 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1), 1002 1003 /* MUX_SEL_MIF4 */ 1004 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c", 1005 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1), 1006 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b", 1007 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1), 1008 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a", 1009 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1), 1010 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c", 1011 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1), 1012 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b", 1013 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1), 1014 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a", 1015 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1), 1016 1017 /* MUX_SEL_MIF5 */ 1018 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c", 1019 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1), 1020 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b", 1021 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1), 1022 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a", 1023 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1), 1024 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p, 1025 MUX_SEL_MIF5, 8, 1), 1026 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p, 1027 MUX_SEL_MIF5, 4, 1), 1028 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p, 1029 MUX_SEL_MIF5, 0, 1), 1030 1031 /* MUX_SEL_MIF6 */ 1032 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p, 1033 MUX_SEL_MIF6, 8, 1), 1034 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p, 1035 MUX_SEL_MIF6, 4, 1), 1036 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p, 1037 MUX_SEL_MIF6, 0, 1), 1038 1039 /* MUX_SEL_MIF7 */ 1040 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c", 1041 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1), 1042 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b", 1043 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1), 1044 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a", 1045 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1), 1046 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p, 1047 MUX_SEL_MIF7, 8, 1), 1048 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p, 1049 MUX_SEL_MIF7, 4, 1), 1050 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p, 1051 MUX_SEL_MIF7, 0, 1), 1052 }; 1053 1054 static struct samsung_div_clock mif_div_clks[] __initdata = { 1055 /* DIV_MIF1 */ 1056 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", 1057 DIV_MIF1, 16, 2), 1058 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1, 1059 12, 2), 1060 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1, 1061 8, 2), 1062 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1, 1063 4, 4), 1064 1065 /* DIV_MIF2 */ 1066 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2", 1067 DIV_MIF2, 20, 3), 1068 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre", 1069 DIV_MIF2, 16, 4), 1070 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre", 1071 DIV_MIF2, 12, 4), 1072 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200", 1073 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3), 1074 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400", 1075 DIV_MIF2, 4, 2), 1076 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400", 1077 DIV_MIF2, 0, 3), 1078 1079 /* DIV_MIF3 */ 1080 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre", 1081 DIV_MIF3, 16, 4), 1082 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b", 1083 DIV_MIF3, 4, 3), 1084 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200", 1085 DIV_MIF3, 0, 3), 1086 1087 /* DIV_MIF4 */ 1088 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c", 1089 DIV_MIF4, 24, 4), 1090 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk", 1091 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4), 1092 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c", 1093 DIV_MIF4, 16, 4), 1094 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c", 1095 DIV_MIF4, 12, 4), 1096 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk", 1097 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4), 1098 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk", 1099 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4), 1100 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk", 1101 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4), 1102 1103 /* DIV_MIF5 */ 1104 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5, 1105 0, 3), 1106 }; 1107 1108 static struct samsung_gate_clock mif_gate_clks[] __initdata = { 1109 /* ENABLE_ACLK_MIF0 */ 1110 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1111 19, CLK_IGNORE_UNUSED, 0), 1112 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1113 18, CLK_IGNORE_UNUSED, 0), 1114 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1115 17, CLK_IGNORE_UNUSED, 0), 1116 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1117 16, CLK_IGNORE_UNUSED, 0), 1118 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0, 1119 15, CLK_IGNORE_UNUSED, 0), 1120 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0, 1121 14, CLK_IGNORE_UNUSED, 0), 1122 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1", 1123 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0), 1124 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0", 1125 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0), 1126 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1", 1127 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0), 1128 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0", 1129 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0), 1130 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1", 1131 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0), 1132 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0", 1133 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0), 1134 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1", 1135 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0), 1136 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0", 1137 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0), 1138 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1", 1139 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0), 1140 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0", 1141 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0), 1142 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1", 1143 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0), 1144 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0", 1145 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1146 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1", 1147 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1148 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0", 1149 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0), 1150 1151 /* ENABLE_ACLK_MIF1 */ 1152 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem", 1153 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28, 1154 CLK_IGNORE_UNUSED, 0), 1155 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci", 1156 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 1157 27, CLK_IGNORE_UNUSED, 0), 1158 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci", 1159 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1160 26, CLK_IGNORE_UNUSED, 0), 1161 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1", 1162 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1163 25, CLK_IGNORE_UNUSED, 0), 1164 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1", 1165 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1166 24, CLK_IGNORE_UNUSED, 0), 1167 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0", 1168 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1169 23, CLK_IGNORE_UNUSED, 0), 1170 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0", 1171 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1172 22, CLK_IGNORE_UNUSED, 0), 1173 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3", 1174 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1175 21, CLK_IGNORE_UNUSED, 0), 1176 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3", 1177 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1178 20, CLK_IGNORE_UNUSED, 0), 1179 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1", 1180 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1181 19, CLK_IGNORE_UNUSED, 0), 1182 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1", 1183 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1184 18, CLK_IGNORE_UNUSED, 0), 1185 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0", 1186 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1187 17, CLK_IGNORE_UNUSED, 0), 1188 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0", 1189 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1190 16, CLK_IGNORE_UNUSED, 0), 1191 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3", 1192 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1193 15, CLK_IGNORE_UNUSED, 0), 1194 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3", 1195 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1196 14, CLK_IGNORE_UNUSED, 0), 1197 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1", 1198 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1199 13, CLK_IGNORE_UNUSED, 0), 1200 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1", 1201 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1202 12, CLK_IGNORE_UNUSED, 0), 1203 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0", 1204 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1205 11, CLK_IGNORE_UNUSED, 0), 1206 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0", 1207 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1208 10, CLK_IGNORE_UNUSED, 0), 1209 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133", 1210 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0), 1211 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133", 1212 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0), 1213 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133", 1214 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0), 1215 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400", 1216 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0), 1217 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200", 1218 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0), 1219 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133", 1220 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0), 1221 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200", 1222 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0), 1223 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133", 1224 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0), 1225 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400", 1226 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0), 1227 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1, 1228 0, CLK_IGNORE_UNUSED, 0), 1229 1230 /* ENABLE_ACLK_MIF2 */ 1231 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266", 1232 ENABLE_ACLK_MIF2, 20, 0, 0), 1233 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1", 1234 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0), 1235 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1", 1236 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0), 1237 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1", 1238 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0), 1239 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0", 1240 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0), 1241 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0", 1242 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0), 1243 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0", 1244 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0), 1245 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx", 1246 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7, 1247 CLK_IGNORE_UNUSED, 0), 1248 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci", 1249 "div_aclk_mif_400", ENABLE_ACLK_MIF2, 1250 5, CLK_IGNORE_UNUSED, 0), 1251 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400", 1252 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0), 1253 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d", 1254 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 1255 3, CLK_IGNORE_UNUSED, 0), 1256 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys", 1257 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0), 1258 1259 /* ENABLE_ACLK_MIF3 */ 1260 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400", 1261 ENABLE_ACLK_MIF3, 4, 1262 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1263 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", 1264 ENABLE_ACLK_MIF3, 1, 1265 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1266 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200", 1267 ENABLE_ACLK_MIF3, 0, 1268 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1269 1270 /* ENABLE_PCLK_MIF */ 1271 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1", 1272 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0), 1273 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1", 1274 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0), 1275 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1", 1276 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0), 1277 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0", 1278 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0), 1279 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0", 1280 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0), 1281 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0", 1282 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0), 1283 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci", 1284 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21, 1285 CLK_IGNORE_UNUSED, 0), 1286 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133", 1287 ENABLE_PCLK_MIF, 19, 0, 0), 1288 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133", 1289 ENABLE_PCLK_MIF, 18, 0, 0), 1290 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3", 1291 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0), 1292 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1", 1293 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0), 1294 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0", 1295 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0), 1296 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3", 1297 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0), 1298 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1", 1299 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0), 1300 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0", 1301 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0), 1302 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133", 1303 ENABLE_PCLK_MIF, 11, 0, 0), 1304 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133", 1305 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), 1306 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133", 1307 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1308 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133", 1309 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1310 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133", 1311 ENABLE_PCLK_MIF, 7, 0, 0), 1312 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133", 1313 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0), 1314 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133", 1315 ENABLE_PCLK_MIF, 5, 0, 0), 1316 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133", 1317 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1318 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133", 1319 ENABLE_PCLK_MIF, 2, 0, 0), 1320 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133", 1321 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1322 1323 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ 1324 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", 1325 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0), 1326 1327 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ 1328 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", 1329 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0), 1330 1331 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ 1332 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", 1333 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), 1334 1335 /* ENABLE_PCLK_MIF_SECURE_RTC */ 1336 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", 1337 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), 1338 1339 /* ENABLE_SCLK_MIF */ 1340 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1", 1341 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0), 1342 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp", 1343 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, 1344 14, CLK_IGNORE_UNUSED, 0), 1345 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0", 1346 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1347 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd", 1348 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1349 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp", 1350 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, 1351 7, CLK_IGNORE_UNUSED, 0), 1352 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp", 1353 "div_sclk_decon_vclk", ENABLE_SCLK_MIF, 1354 6, CLK_IGNORE_UNUSED, 0), 1355 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp", 1356 "div_sclk_decon_eclk", ENABLE_SCLK_MIF, 1357 5, CLK_IGNORE_UNUSED, 0), 1358 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif", 1359 ENABLE_SCLK_MIF, 4, 1360 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1361 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2", 1362 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1363 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2", 1364 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0), 1365 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll", 1366 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0), 1367 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll", 1368 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1369 1370 /* ENABLE_SCLK_TOP_DISP */ 1371 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", 1372 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, 1373 CLK_IGNORE_UNUSED, 0), 1374 }; 1375 1376 static struct samsung_cmu_info mif_cmu_info __initdata = { 1377 .pll_clks = mif_pll_clks, 1378 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1379 .mux_clks = mif_mux_clks, 1380 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), 1381 .div_clks = mif_div_clks, 1382 .nr_div_clks = ARRAY_SIZE(mif_div_clks), 1383 .gate_clks = mif_gate_clks, 1384 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), 1385 .fixed_factor_clks = mif_fixed_factor_clks, 1386 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), 1387 .nr_clk_ids = MIF_NR_CLK, 1388 .clk_regs = mif_clk_regs, 1389 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), 1390 }; 1391 1392 static void __init exynos5433_cmu_mif_init(struct device_node *np) 1393 { 1394 samsung_cmu_register_one(np, &mif_cmu_info); 1395 } 1396 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", 1397 exynos5433_cmu_mif_init); 1398 1399 /* 1400 * Register offset definitions for CMU_PERIC 1401 */ 1402 #define DIV_PERIC 0x0600 1403 #define DIV_STAT_PERIC 0x0700 1404 #define ENABLE_ACLK_PERIC 0x0800 1405 #define ENABLE_PCLK_PERIC0 0x0900 1406 #define ENABLE_PCLK_PERIC1 0x0904 1407 #define ENABLE_SCLK_PERIC 0x0A00 1408 #define ENABLE_IP_PERIC0 0x0B00 1409 #define ENABLE_IP_PERIC1 0x0B04 1410 #define ENABLE_IP_PERIC2 0x0B08 1411 1412 static unsigned long peric_clk_regs[] __initdata = { 1413 DIV_PERIC, 1414 DIV_STAT_PERIC, 1415 ENABLE_ACLK_PERIC, 1416 ENABLE_PCLK_PERIC0, 1417 ENABLE_PCLK_PERIC1, 1418 ENABLE_SCLK_PERIC, 1419 ENABLE_IP_PERIC0, 1420 ENABLE_IP_PERIC1, 1421 ENABLE_IP_PERIC2, 1422 }; 1423 1424 static struct samsung_div_clock peric_div_clks[] __initdata = { 1425 /* DIV_PERIC */ 1426 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), 1427 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), 1428 }; 1429 1430 static struct samsung_gate_clock peric_gate_clks[] __initdata = { 1431 /* ENABLE_ACLK_PERIC */ 1432 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", 1433 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), 1434 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66", 1435 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0), 1436 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66", 1437 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0), 1438 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66", 1439 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0), 1440 1441 /* ENABLE_PCLK_PERIC0 */ 1442 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1443 31, CLK_SET_RATE_PARENT, 0), 1444 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66", 1445 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0), 1446 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66", 1447 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0), 1448 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1449 28, CLK_SET_RATE_PARENT, 0), 1450 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1451 26, CLK_SET_RATE_PARENT, 0), 1452 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1453 25, CLK_SET_RATE_PARENT, 0), 1454 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1455 24, CLK_SET_RATE_PARENT, 0), 1456 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1457 23, CLK_SET_RATE_PARENT, 0), 1458 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1459 22, CLK_SET_RATE_PARENT, 0), 1460 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1461 21, CLK_SET_RATE_PARENT, 0), 1462 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1463 20, CLK_SET_RATE_PARENT, 0), 1464 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66", 1465 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0), 1466 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66", 1467 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0), 1468 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66", 1469 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0), 1470 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66", 1471 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0), 1472 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66", 1473 ENABLE_PCLK_PERIC0, 15, 1474 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1475 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1476 14, CLK_SET_RATE_PARENT, 0), 1477 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1478 13, CLK_SET_RATE_PARENT, 0), 1479 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1480 12, CLK_SET_RATE_PARENT, 0), 1481 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66", 1482 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0), 1483 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66", 1484 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0), 1485 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66", 1486 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0), 1487 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66", 1488 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 1489 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1490 7, CLK_SET_RATE_PARENT, 0), 1491 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1492 6, CLK_SET_RATE_PARENT, 0), 1493 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1494 5, CLK_SET_RATE_PARENT, 0), 1495 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1496 4, CLK_SET_RATE_PARENT, 0), 1497 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1498 3, CLK_SET_RATE_PARENT, 0), 1499 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1500 2, CLK_SET_RATE_PARENT, 0), 1501 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1502 1, CLK_SET_RATE_PARENT, 0), 1503 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1504 0, CLK_SET_RATE_PARENT, 0), 1505 1506 /* ENABLE_PCLK_PERIC1 */ 1507 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1508 9, CLK_SET_RATE_PARENT, 0), 1509 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1510 8, CLK_SET_RATE_PARENT, 0), 1511 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66", 1512 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0), 1513 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66", 1514 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0), 1515 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66", 1516 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0), 1517 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66", 1518 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 1519 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66", 1520 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0), 1521 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66", 1522 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0), 1523 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66", 1524 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0), 1525 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66", 1526 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 1527 1528 /* ENABLE_SCLK_PERIC */ 1529 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", 1530 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), 1531 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", 1532 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), 1533 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, 1534 19, CLK_SET_RATE_PARENT, 0), 1535 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, 1536 18, CLK_SET_RATE_PARENT, 0), 1537 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, 1538 17, 0, 0), 1539 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC, 1540 16, 0, 0), 1541 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0), 1542 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", 1543 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), 1544 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", 1545 ENABLE_SCLK_PERIC, 12, 1546 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1547 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", 1548 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1549 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", 1550 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, 1551 CLK_SET_RATE_PARENT, 0), 1552 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", 1553 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 1554 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", 1555 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 1556 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric", 1557 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 1558 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, 1559 5, CLK_SET_RATE_PARENT, 0), 1560 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, 1561 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1562 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 1563 3, CLK_SET_RATE_PARENT, 0), 1564 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", 1565 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 1566 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", 1567 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 1568 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", 1569 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 1570 }; 1571 1572 static struct samsung_cmu_info peric_cmu_info __initdata = { 1573 .div_clks = peric_div_clks, 1574 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 1575 .gate_clks = peric_gate_clks, 1576 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), 1577 .nr_clk_ids = PERIC_NR_CLK, 1578 .clk_regs = peric_clk_regs, 1579 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 1580 }; 1581 1582 static void __init exynos5433_cmu_peric_init(struct device_node *np) 1583 { 1584 samsung_cmu_register_one(np, &peric_cmu_info); 1585 } 1586 1587 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", 1588 exynos5433_cmu_peric_init); 1589 1590 /* 1591 * Register offset definitions for CMU_PERIS 1592 */ 1593 #define ENABLE_ACLK_PERIS 0x0800 1594 #define ENABLE_PCLK_PERIS 0x0900 1595 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904 1596 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908 1597 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c 1598 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910 1599 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914 1600 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918 1601 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c 1602 #define ENABLE_SCLK_PERIS 0x0a00 1603 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04 1604 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08 1605 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c 1606 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10 1607 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14 1608 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18 1609 #define ENABLE_IP_PERIS0 0x0b00 1610 #define ENABLE_IP_PERIS1 0x0b04 1611 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08 1612 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c 1613 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10 1614 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14 1615 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18 1616 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c 1617 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 1618 1619 static unsigned long peris_clk_regs[] __initdata = { 1620 ENABLE_ACLK_PERIS, 1621 ENABLE_PCLK_PERIS, 1622 ENABLE_PCLK_PERIS_SECURE_TZPC, 1623 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 1624 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 1625 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 1626 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 1627 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 1628 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 1629 ENABLE_SCLK_PERIS, 1630 ENABLE_SCLK_PERIS_SECURE_SECKEY, 1631 ENABLE_SCLK_PERIS_SECURE_CHIPID, 1632 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 1633 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 1634 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 1635 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 1636 ENABLE_IP_PERIS0, 1637 ENABLE_IP_PERIS1, 1638 ENABLE_IP_PERIS_SECURE_TZPC, 1639 ENABLE_IP_PERIS_SECURE_SECKEY, 1640 ENABLE_IP_PERIS_SECURE_CHIPID, 1641 ENABLE_IP_PERIS_SECURE_TOPRTC, 1642 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE, 1643 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT, 1644 ENABLE_IP_PERIS_SECURE_OTP_CON, 1645 }; 1646 1647 static struct samsung_gate_clock peris_gate_clks[] __initdata = { 1648 /* ENABLE_ACLK_PERIS */ 1649 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", 1650 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), 1651 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66", 1652 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1653 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66", 1654 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1655 1656 /* ENABLE_PCLK_PERIS */ 1657 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66", 1658 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0), 1659 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66", 1660 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0), 1661 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66", 1662 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0), 1663 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66", 1664 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0), 1665 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66", 1666 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0), 1667 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66", 1668 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0), 1669 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66", 1670 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0), 1671 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66", 1672 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0), 1673 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66", 1674 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0), 1675 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66", 1676 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0), 1677 1678 /* ENABLE_PCLK_PERIS_SECURE_TZPC */ 1679 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66", 1680 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0), 1681 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66", 1682 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0), 1683 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66", 1684 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0), 1685 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66", 1686 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0), 1687 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66", 1688 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0), 1689 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66", 1690 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0), 1691 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66", 1692 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0), 1693 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66", 1694 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0), 1695 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66", 1696 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0), 1697 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66", 1698 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0), 1699 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66", 1700 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0), 1701 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66", 1702 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0), 1703 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66", 1704 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0), 1705 1706 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ 1707 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66", 1708 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0), 1709 1710 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ 1711 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66", 1712 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0), 1713 1714 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ 1715 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66", 1716 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1717 1718 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ 1719 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif", 1720 "aclk_peris_66", 1721 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0), 1722 1723 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ 1724 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif", 1725 "aclk_peris_66", 1726 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0), 1727 1728 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ 1729 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif", 1730 "aclk_peris_66", 1731 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0), 1732 1733 /* ENABLE_SCLK_PERIS */ 1734 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common", 1735 ENABLE_SCLK_PERIS, 10, 0, 0), 1736 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common", 1737 ENABLE_SCLK_PERIS, 4, 0, 0), 1738 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common", 1739 ENABLE_SCLK_PERIS, 3, 0, 0), 1740 1741 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */ 1742 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common", 1743 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0), 1744 1745 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */ 1746 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common", 1747 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 1748 1749 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ 1750 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common", 1751 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1752 1753 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ 1754 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common", 1755 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0), 1756 1757 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ 1758 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common", 1759 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0), 1760 1761 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ 1762 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common", 1763 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), 1764 }; 1765 1766 static struct samsung_cmu_info peris_cmu_info __initdata = { 1767 .gate_clks = peris_gate_clks, 1768 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 1769 .nr_clk_ids = PERIS_NR_CLK, 1770 .clk_regs = peris_clk_regs, 1771 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 1772 }; 1773 1774 static void __init exynos5433_cmu_peris_init(struct device_node *np) 1775 { 1776 samsung_cmu_register_one(np, &peris_cmu_info); 1777 } 1778 1779 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", 1780 exynos5433_cmu_peris_init); 1781 1782 /* 1783 * Register offset definitions for CMU_FSYS 1784 */ 1785 #define MUX_SEL_FSYS0 0x0200 1786 #define MUX_SEL_FSYS1 0x0204 1787 #define MUX_SEL_FSYS2 0x0208 1788 #define MUX_SEL_FSYS3 0x020c 1789 #define MUX_SEL_FSYS4 0x0210 1790 #define MUX_ENABLE_FSYS0 0x0300 1791 #define MUX_ENABLE_FSYS1 0x0304 1792 #define MUX_ENABLE_FSYS2 0x0308 1793 #define MUX_ENABLE_FSYS3 0x030c 1794 #define MUX_ENABLE_FSYS4 0x0310 1795 #define MUX_STAT_FSYS0 0x0400 1796 #define MUX_STAT_FSYS1 0x0404 1797 #define MUX_STAT_FSYS2 0x0408 1798 #define MUX_STAT_FSYS3 0x040c 1799 #define MUX_STAT_FSYS4 0x0410 1800 #define MUX_IGNORE_FSYS2 0x0508 1801 #define MUX_IGNORE_FSYS3 0x050c 1802 #define ENABLE_ACLK_FSYS0 0x0800 1803 #define ENABLE_ACLK_FSYS1 0x0804 1804 #define ENABLE_PCLK_FSYS 0x0900 1805 #define ENABLE_SCLK_FSYS 0x0a00 1806 #define ENABLE_IP_FSYS0 0x0b00 1807 #define ENABLE_IP_FSYS1 0x0b04 1808 1809 /* list of all parent clock list */ 1810 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", }; 1811 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; 1812 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", }; 1813 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", }; 1814 1815 static unsigned long fsys_clk_regs[] __initdata = { 1816 MUX_SEL_FSYS0, 1817 MUX_SEL_FSYS1, 1818 MUX_SEL_FSYS2, 1819 MUX_SEL_FSYS3, 1820 MUX_SEL_FSYS4, 1821 MUX_ENABLE_FSYS0, 1822 MUX_ENABLE_FSYS1, 1823 MUX_ENABLE_FSYS2, 1824 MUX_ENABLE_FSYS3, 1825 MUX_ENABLE_FSYS4, 1826 MUX_STAT_FSYS0, 1827 MUX_STAT_FSYS1, 1828 MUX_STAT_FSYS2, 1829 MUX_STAT_FSYS3, 1830 MUX_STAT_FSYS4, 1831 MUX_IGNORE_FSYS2, 1832 MUX_IGNORE_FSYS3, 1833 ENABLE_ACLK_FSYS0, 1834 ENABLE_ACLK_FSYS1, 1835 ENABLE_PCLK_FSYS, 1836 ENABLE_SCLK_FSYS, 1837 ENABLE_IP_FSYS0, 1838 ENABLE_IP_FSYS1, 1839 }; 1840 1841 static struct samsung_mux_clock fsys_mux_clks[] __initdata = { 1842 /* MUX_SEL_FSYS0 */ 1843 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user", 1844 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1), 1845 1846 /* MUX_SEL_FSYS1 */ 1847 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user", 1848 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1), 1849 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user", 1850 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1), 1851 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user", 1852 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1), 1853 }; 1854 1855 static struct samsung_gate_clock fsys_gate_clks[] __initdata = { 1856 /* ENABLE_ACLK_FSYS0 */ 1857 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", 1858 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), 1859 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user", 1860 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0), 1861 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user", 1862 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 1863 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user", 1864 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0), 1865 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user", 1866 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0), 1867 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user", 1868 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0), 1869 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user", 1870 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0), 1871 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user", 1872 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0), 1873 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user", 1874 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0), 1875 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user", 1876 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0), 1877 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user", 1878 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0), 1879 1880 /* ENABLE_SCLK_FSYS */ 1881 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user", 1882 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 1883 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user", 1884 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0), 1885 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user", 1886 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1887 1888 /* ENABLE_IP_FSYS0 */ 1889 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), 1890 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), 1891 }; 1892 1893 static struct samsung_cmu_info fsys_cmu_info __initdata = { 1894 .mux_clks = fsys_mux_clks, 1895 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 1896 .gate_clks = fsys_gate_clks, 1897 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 1898 .nr_clk_ids = FSYS_NR_CLK, 1899 .clk_regs = fsys_clk_regs, 1900 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 1901 }; 1902 1903 static void __init exynos5433_cmu_fsys_init(struct device_node *np) 1904 { 1905 samsung_cmu_register_one(np, &fsys_cmu_info); 1906 } 1907 1908 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys", 1909 exynos5433_cmu_fsys_init); 1910 1911 /* 1912 * Register offset definitions for CMU_G2D 1913 */ 1914 #define MUX_SEL_G2D0 0x0200 1915 #define MUX_SEL_ENABLE_G2D0 0x0300 1916 #define MUX_SEL_STAT_G2D0 0x0400 1917 #define DIV_G2D 0x0600 1918 #define DIV_STAT_G2D 0x0700 1919 #define DIV_ENABLE_ACLK_G2D 0x0800 1920 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804 1921 #define DIV_ENABLE_PCLK_G2D 0x0900 1922 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904 1923 #define DIV_ENABLE_IP_G2D0 0x0b00 1924 #define DIV_ENABLE_IP_G2D1 0x0b04 1925 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 1926 1927 static unsigned long g2d_clk_regs[] __initdata = { 1928 MUX_SEL_G2D0, 1929 MUX_SEL_ENABLE_G2D0, 1930 MUX_SEL_STAT_G2D0, 1931 DIV_G2D, 1932 DIV_STAT_G2D, 1933 DIV_ENABLE_ACLK_G2D, 1934 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 1935 DIV_ENABLE_PCLK_G2D, 1936 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 1937 DIV_ENABLE_IP_G2D0, 1938 DIV_ENABLE_IP_G2D1, 1939 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D, 1940 }; 1941 1942 /* list of all parent clock list */ 1943 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; 1944 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; 1945 1946 static struct samsung_mux_clock g2d_mux_clks[] __initdata = { 1947 /* MUX_SEL_G2D0 */ 1948 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", 1949 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), 1950 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user", 1951 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), 1952 }; 1953 1954 static struct samsung_div_clock g2d_div_clks[] __initdata = { 1955 /* DIV_G2D */ 1956 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", 1957 DIV_G2D, 0, 2), 1958 }; 1959 1960 static struct samsung_gate_clock g2d_gate_clks[] __initdata = { 1961 /* DIV_ENABLE_ACLK_G2D */ 1962 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", 1963 DIV_ENABLE_ACLK_G2D, 12, 0, 0), 1964 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user", 1965 DIV_ENABLE_ACLK_G2D, 11, 0, 0), 1966 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user", 1967 DIV_ENABLE_ACLK_G2D, 10, 0, 0), 1968 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user", 1969 DIV_ENABLE_ACLK_G2D, 9, 0, 0), 1970 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user", 1971 DIV_ENABLE_ACLK_G2D, 8, 0, 0), 1972 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx", 1973 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D, 1974 7, 0, 0), 1975 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d", 1976 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), 1977 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d", 1978 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), 1979 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user", 1980 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), 1981 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d", 1982 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), 1983 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user", 1984 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 1985 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user", 1986 DIV_ENABLE_ACLK_G2D, 1, 0, 0), 1987 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user", 1988 DIV_ENABLE_ACLK_G2D, 0, 0, 0), 1989 1990 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ 1991 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user", 1992 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 1993 1994 /* DIV_ENABLE_PCLK_G2D */ 1995 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d", 1996 DIV_ENABLE_PCLK_G2D, 7, 0, 0), 1997 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d", 1998 DIV_ENABLE_PCLK_G2D, 6, 0, 0), 1999 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d", 2000 DIV_ENABLE_PCLK_G2D, 5, 0, 0), 2001 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d", 2002 DIV_ENABLE_PCLK_G2D, 4, 0, 0), 2003 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d", 2004 DIV_ENABLE_PCLK_G2D, 3, 0, 0), 2005 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d", 2006 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2007 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d", 2008 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0), 2009 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D, 2010 0, 0, 0), 2011 2012 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ 2013 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d", 2014 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2015 }; 2016 2017 static struct samsung_cmu_info g2d_cmu_info __initdata = { 2018 .mux_clks = g2d_mux_clks, 2019 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), 2020 .div_clks = g2d_div_clks, 2021 .nr_div_clks = ARRAY_SIZE(g2d_div_clks), 2022 .gate_clks = g2d_gate_clks, 2023 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), 2024 .nr_clk_ids = G2D_NR_CLK, 2025 .clk_regs = g2d_clk_regs, 2026 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), 2027 }; 2028 2029 static void __init exynos5433_cmu_g2d_init(struct device_node *np) 2030 { 2031 samsung_cmu_register_one(np, &g2d_cmu_info); 2032 } 2033 2034 CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d", 2035 exynos5433_cmu_g2d_init); 2036 2037 /* 2038 * Register offset definitions for CMU_DISP 2039 */ 2040 #define DISP_PLL_LOCK 0x0000 2041 #define DISP_PLL_CON0 0x0100 2042 #define DISP_PLL_CON1 0x0104 2043 #define DISP_PLL_FREQ_DET 0x0108 2044 #define MUX_SEL_DISP0 0x0200 2045 #define MUX_SEL_DISP1 0x0204 2046 #define MUX_SEL_DISP2 0x0208 2047 #define MUX_SEL_DISP3 0x020c 2048 #define MUX_SEL_DISP4 0x0210 2049 #define MUX_ENABLE_DISP0 0x0300 2050 #define MUX_ENABLE_DISP1 0x0304 2051 #define MUX_ENABLE_DISP2 0x0308 2052 #define MUX_ENABLE_DISP3 0x030c 2053 #define MUX_ENABLE_DISP4 0x0310 2054 #define MUX_STAT_DISP0 0x0400 2055 #define MUX_STAT_DISP1 0x0404 2056 #define MUX_STAT_DISP2 0x0408 2057 #define MUX_STAT_DISP3 0x040c 2058 #define MUX_STAT_DISP4 0x0410 2059 #define MUX_IGNORE_DISP2 0x0508 2060 #define DIV_DISP 0x0600 2061 #define DIV_DISP_PLL_FREQ_DET 0x0604 2062 #define DIV_STAT_DISP 0x0700 2063 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704 2064 #define ENABLE_ACLK_DISP0 0x0800 2065 #define ENABLE_ACLK_DISP1 0x0804 2066 #define ENABLE_PCLK_DISP 0x0900 2067 #define ENABLE_SCLK_DISP 0x0a00 2068 #define ENABLE_IP_DISP0 0x0b00 2069 #define ENABLE_IP_DISP1 0x0b04 2070 #define CLKOUT_CMU_DISP 0x0c00 2071 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 2072 2073 static unsigned long disp_clk_regs[] __initdata = { 2074 DISP_PLL_LOCK, 2075 DISP_PLL_CON0, 2076 DISP_PLL_CON1, 2077 DISP_PLL_FREQ_DET, 2078 MUX_SEL_DISP0, 2079 MUX_SEL_DISP1, 2080 MUX_SEL_DISP2, 2081 MUX_SEL_DISP3, 2082 MUX_SEL_DISP4, 2083 MUX_ENABLE_DISP0, 2084 MUX_ENABLE_DISP1, 2085 MUX_ENABLE_DISP2, 2086 MUX_ENABLE_DISP3, 2087 MUX_ENABLE_DISP4, 2088 MUX_STAT_DISP0, 2089 MUX_STAT_DISP1, 2090 MUX_STAT_DISP2, 2091 MUX_STAT_DISP3, 2092 MUX_STAT_DISP4, 2093 MUX_IGNORE_DISP2, 2094 DIV_DISP, 2095 DIV_DISP_PLL_FREQ_DET, 2096 DIV_STAT_DISP, 2097 DIV_STAT_DISP_PLL_FREQ_DET, 2098 ENABLE_ACLK_DISP0, 2099 ENABLE_ACLK_DISP1, 2100 ENABLE_PCLK_DISP, 2101 ENABLE_SCLK_DISP, 2102 ENABLE_IP_DISP0, 2103 ENABLE_IP_DISP1, 2104 CLKOUT_CMU_DISP, 2105 CLKOUT_CMU_DISP_DIV_STAT, 2106 }; 2107 2108 /* list of all parent clock list */ 2109 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", }; 2110 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", }; 2111 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", }; 2112 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", }; 2113 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk", 2114 "sclk_decon_tv_eclk_disp", }; 2115 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk", 2116 "sclk_decon_vclk_disp", }; 2117 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk", 2118 "sclk_decon_eclk_disp", }; 2119 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk", 2120 "sclk_decon_tv_vclk_disp", }; 2121 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", }; 2122 2123 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk", 2124 "phyclk_mipidphy1_bitclkdiv8_phy", }; 2125 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk", 2126 "phyclk_mipidphy1_rxclkesc0_phy", }; 2127 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk", 2128 "phyclk_mipidphy0_bitclkdiv8_phy", }; 2129 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk", 2130 "phyclk_mipidphy0_rxclkesc0_phy", }; 2131 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk", 2132 "phyclk_hdmiphy_tmds_clko_phy", }; 2133 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk", 2134 "phyclk_hdmiphy_pixel_clko_phy", }; 2135 2136 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll", 2137 "mout_sclk_dsim0_user", }; 2138 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll", 2139 "mout_sclk_decon_tv_eclk_user", }; 2140 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll", 2141 "mout_sclk_decon_vclk_user", }; 2142 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll", 2143 "mout_sclk_decon_eclk_user", }; 2144 2145 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp", 2146 "mout_sclk_dsim1_user", }; 2147 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { 2148 "mout_phyclk_hdmiphy_pixel_clko_user", 2149 "mout_sclk_decon_tv_vclk_b_disp", }; 2150 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", 2151 "mout_sclk_decon_tv_vclk_user", }; 2152 2153 static struct samsung_pll_clock disp_pll_clks[] __initdata = { 2154 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", 2155 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates), 2156 }; 2157 2158 static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = { 2159 /* 2160 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. 2161 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} 2162 * and sclk_decon_{vclk|tv_vclk}. 2163 */ 2164 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk", 2165 1, 2, 0), 2166 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk", 2167 1, 2, 0), 2168 }; 2169 2170 static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { 2171 /* PHY clocks from MIPI_DPHY1 */ 2172 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT, 2173 188000000), 2174 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT, 2175 100000000), 2176 /* PHY clocks from MIPI_DPHY0 */ 2177 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT, 2178 188000000), 2179 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT, 2180 100000000), 2181 /* PHY clocks from HDMI_PHY */ 2182 FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000), 2183 FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000), 2184 }; 2185 2186 static struct samsung_mux_clock disp_mux_clks[] __initdata = { 2187 /* MUX_SEL_DISP0 */ 2188 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, 2189 0, 1), 2190 2191 /* MUX_SEL_DISP1 */ 2192 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user", 2193 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1), 2194 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user", 2195 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1), 2196 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p, 2197 MUX_SEL_DISP1, 20, 1), 2198 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user", 2199 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1), 2200 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user", 2201 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1), 2202 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user", 2203 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1), 2204 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user", 2205 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1), 2206 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", 2207 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1), 2208 2209 /* MUX_SEL_DISP2 */ 2210 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 2211 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2212 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2, 2213 20, 1), 2214 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 2215 "mout_phyclk_mipidphy1_rxclkesc0_user", 2216 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2, 2217 16, 1), 2218 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 2219 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2220 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2, 2221 12, 1), 2222 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 2223 "mout_phyclk_mipidphy0_rxclkesc0_user", 2224 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2, 2225 8, 1), 2226 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 2227 "mout_phyclk_hdmiphy_tmds_clko_user", 2228 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2, 2229 4, 1), 2230 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 2231 "mout_phyclk_hdmiphy_pixel_clko_user", 2232 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2, 2233 0, 1), 2234 2235 /* MUX_SEL_DISP3 */ 2236 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p, 2237 MUX_SEL_DISP3, 12, 1), 2238 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk", 2239 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1), 2240 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk", 2241 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1), 2242 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk", 2243 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1), 2244 2245 /* MUX_SEL_DISP4 */ 2246 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp", 2247 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1), 2248 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp", 2249 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1), 2250 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP, 2251 "mout_sclk_decon_tv_vclk_c_disp", 2252 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1), 2253 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP, 2254 "mout_sclk_decon_tv_vclk_b_disp", 2255 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1), 2256 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP, 2257 "mout_sclk_decon_tv_vclk_a_disp", 2258 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), 2259 }; 2260 2261 static struct samsung_div_clock disp_div_clks[] __initdata = { 2262 /* DIV_DISP */ 2263 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", 2264 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), 2265 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp", 2266 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3), 2267 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0", 2268 DIV_DISP, 16, 3), 2269 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp", 2270 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3), 2271 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp", 2272 "mout_sclk_decon_vclk", DIV_DISP, 8, 3), 2273 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp", 2274 "mout_sclk_decon_eclk", DIV_DISP, 4, 3), 2275 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user", 2276 DIV_DISP, 0, 2), 2277 }; 2278 2279 static struct samsung_gate_clock disp_gate_clks[] __initdata = { 2280 /* ENABLE_ACLK_DISP0 */ 2281 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", 2282 ENABLE_ACLK_DISP0, 2, 0, 0), 2283 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user", 2284 ENABLE_ACLK_DISP0, 0, 0, 0), 2285 2286 /* ENABLE_ACLK_DISP1 */ 2287 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user", 2288 ENABLE_ACLK_DISP1, 25, 0, 0), 2289 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user", 2290 ENABLE_ACLK_DISP1, 24, 0, 0), 2291 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x", 2292 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0), 2293 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x", 2294 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0), 2295 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3", 2296 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0), 2297 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2", 2298 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0), 2299 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1", 2300 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0), 2301 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0", 2302 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0), 2303 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4", 2304 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0), 2305 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3", 2306 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0), 2307 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2", 2308 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0), 2309 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1", 2310 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0), 2311 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0", 2312 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0), 2313 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p", 2314 "div_pclk_disp", ENABLE_ACLK_DISP1, 2315 12, CLK_IGNORE_UNUSED, 0), 2316 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p", 2317 "div_pclk_disp", ENABLE_ACLK_DISP1, 2318 11, CLK_IGNORE_UNUSED, 0), 2319 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p", 2320 "div_pclk_disp", ENABLE_ACLK_DISP1, 2321 10, CLK_IGNORE_UNUSED, 0), 2322 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp", 2323 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0), 2324 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user", 2325 ENABLE_ACLK_DISP1, 7, 0, 0), 2326 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user", 2327 ENABLE_ACLK_DISP1, 6, 0, 0), 2328 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x", 2329 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0), 2330 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x", 2331 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0), 2332 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user", 2333 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0), 2334 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp", 2335 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0), 2336 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333", 2337 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1, 2338 CLK_IGNORE_UNUSED, 0), 2339 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333", 2340 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 2341 0, CLK_IGNORE_UNUSED, 0), 2342 2343 /* ENABLE_PCLK_DISP */ 2344 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp", 2345 ENABLE_PCLK_DISP, 23, 0, 0), 2346 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp", 2347 ENABLE_PCLK_DISP, 22, 0, 0), 2348 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp", 2349 ENABLE_PCLK_DISP, 21, 0, 0), 2350 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp", 2351 ENABLE_PCLK_DISP, 20, 0, 0), 2352 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp", 2353 ENABLE_PCLK_DISP, 19, 0, 0), 2354 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp", 2355 ENABLE_PCLK_DISP, 18, 0, 0), 2356 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp", 2357 ENABLE_PCLK_DISP, 17, 0, 0), 2358 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp", 2359 ENABLE_PCLK_DISP, 16, 0, 0), 2360 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp", 2361 ENABLE_PCLK_DISP, 15, 0, 0), 2362 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp", 2363 ENABLE_PCLK_DISP, 14, 0, 0), 2364 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp", 2365 ENABLE_PCLK_DISP, 13, 0, 0), 2366 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp", 2367 ENABLE_PCLK_DISP, 12, 0, 0), 2368 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp", 2369 ENABLE_PCLK_DISP, 11, 0, 0), 2370 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp", 2371 ENABLE_PCLK_DISP, 10, 0, 0), 2372 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp", 2373 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), 2374 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp", 2375 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), 2376 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp", 2377 ENABLE_PCLK_DISP, 7, 0, 0), 2378 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp", 2379 ENABLE_PCLK_DISP, 6, 0, 0), 2380 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp", 2381 ENABLE_PCLK_DISP, 5, 0, 0), 2382 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp", 2383 ENABLE_PCLK_DISP, 3, 0, 0), 2384 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp", 2385 ENABLE_PCLK_DISP, 2, 0, 0), 2386 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp", 2387 ENABLE_PCLK_DISP, 1, 0, 0), 2388 2389 /* ENABLE_SCLK_DISP */ 2390 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8", 2391 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2392 ENABLE_SCLK_DISP, 26, 0, 0), 2393 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0", 2394 "mout_phyclk_mipidphy1_rxclkesc0_user", 2395 ENABLE_SCLK_DISP, 25, 0, 0), 2396 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1", 2397 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0), 2398 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1", 2399 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0), 2400 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp", 2401 ENABLE_SCLK_DISP, 22, 0, 0), 2402 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk", 2403 "div_sclk_decon_tv_vclk_disp", 2404 ENABLE_SCLK_DISP, 21, 0, 0), 2405 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8", 2406 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2407 ENABLE_SCLK_DISP, 15, 0, 0), 2408 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0", 2409 "mout_phyclk_mipidphy0_rxclkesc0_user", 2410 ENABLE_SCLK_DISP, 14, 0, 0), 2411 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko", 2412 "mout_phyclk_hdmiphy_tmds_clko_user", 2413 ENABLE_SCLK_DISP, 13, 0, 0), 2414 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel", 2415 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0), 2416 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies", 2417 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0), 2418 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0", 2419 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0), 2420 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0", 2421 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0), 2422 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user", 2423 ENABLE_SCLK_DISP, 7, 0, 0), 2424 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp", 2425 ENABLE_SCLK_DISP, 6, 0, 0), 2426 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp", 2427 ENABLE_SCLK_DISP, 5, 0, 0), 2428 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk", 2429 "div_sclk_decon_tv_eclk_disp", 2430 ENABLE_SCLK_DISP, 4, 0, 0), 2431 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk", 2432 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0), 2433 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk", 2434 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), 2435 }; 2436 2437 static struct samsung_cmu_info disp_cmu_info __initdata = { 2438 .pll_clks = disp_pll_clks, 2439 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), 2440 .mux_clks = disp_mux_clks, 2441 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), 2442 .div_clks = disp_div_clks, 2443 .nr_div_clks = ARRAY_SIZE(disp_div_clks), 2444 .gate_clks = disp_gate_clks, 2445 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), 2446 .fixed_clks = disp_fixed_clks, 2447 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), 2448 .fixed_factor_clks = disp_fixed_factor_clks, 2449 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), 2450 .nr_clk_ids = DISP_NR_CLK, 2451 .clk_regs = disp_clk_regs, 2452 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), 2453 }; 2454 2455 static void __init exynos5433_cmu_disp_init(struct device_node *np) 2456 { 2457 samsung_cmu_register_one(np, &disp_cmu_info); 2458 } 2459 2460 CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp", 2461 exynos5433_cmu_disp_init); 2462