| axg-audio.c (a96cbb146a9736f501fe66ebda6a9018735e5e8a) | axg-audio.c (05d3b7c68e6205b2036a7c854e94a62556eeee0f) |
|---|---|
| 1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/clk-provider.h> 9#include <linux/init.h> | 1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/clk-provider.h> 9#include <linux/init.h> |
| 10#include <linux/of_device.h> |
|
| 10#include <linux/module.h> | 11#include <linux/module.h> |
| 11#include <linux/of.h> | |
| 12#include <linux/platform_device.h> 13#include <linux/regmap.h> 14#include <linux/reset.h> 15#include <linux/reset-controller.h> 16#include <linux/slab.h> 17 | 12#include <linux/platform_device.h> 13#include <linux/regmap.h> 14#include <linux/reset.h> 15#include <linux/reset-controller.h> 16#include <linux/slab.h> 17 |
| 18#include "meson-clkc-utils.h" |
|
| 18#include "axg-audio.h" 19#include "clk-regmap.h" 20#include "clk-phase.h" 21#include "sclk-div.h" 22 23#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ 24 .data = &(struct clk_regmap_gate_data){ \ 25 .offset = (_reg), \ --- 780 unchanged lines hidden (view full) --- 806 tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data); 807static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL( 808 tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data); 809 810/* 811 * Array of all clocks provided by this provider 812 * The input clocks of the controller will be populated at runtime 813 */ | 19#include "axg-audio.h" 20#include "clk-regmap.h" 21#include "clk-phase.h" 22#include "sclk-div.h" 23 24#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ 25 .data = &(struct clk_regmap_gate_data){ \ 26 .offset = (_reg), \ --- 780 unchanged lines hidden (view full) --- 807 tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data); 808static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL( 809 tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data); 810 811/* 812 * Array of all clocks provided by this provider 813 * The input clocks of the controller will be populated at runtime 814 */ |
| 814static struct clk_hw_onecell_data axg_audio_hw_onecell_data = { 815 .hws = { 816 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 817 [AUD_CLKID_PDM] = &pdm.hw, 818 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 819 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 820 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 821 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 822 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 823 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 824 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 825 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 826 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 827 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 828 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 829 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 830 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 831 [AUD_CLKID_LOOPBACK] = &loopback.hw, 832 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 833 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 834 [AUD_CLKID_RESAMPLE] = &resample.hw, 835 [AUD_CLKID_POWER_DETECT] = &power_detect.hw, 836 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw, 837 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw, 838 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw, 839 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw, 840 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw, 841 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw, 842 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw, 843 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw, 844 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw, 845 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw, 846 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw, 847 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw, 848 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw, 849 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw, 850 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw, 851 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw, 852 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw, 853 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw, 854 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 855 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 856 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 857 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 858 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 859 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 860 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 861 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 862 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 863 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 864 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 865 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 866 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 867 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 868 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 869 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 870 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 871 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 872 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 873 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 874 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 875 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 876 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 877 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 878 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 879 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 880 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 881 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 882 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 883 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 884 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 885 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 886 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 887 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 888 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 889 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 890 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 891 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 892 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 893 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 894 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 895 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 896 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 897 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 898 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 899 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 900 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 901 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 902 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 903 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 904 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 905 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 906 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 907 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 908 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 909 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 910 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 911 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 912 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 913 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 914 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 915 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 916 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 917 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 918 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 919 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 920 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 921 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 922 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 923 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 924 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 925 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 926 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 927 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw, 928 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw, 929 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw, 930 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 931 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 932 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 933 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 934 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 935 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 936 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 937 [AUD_CLKID_TOP] = &axg_aud_top, 938 [NR_CLKS] = NULL, 939 }, 940 .num = NR_CLKS, | 815static struct clk_hw *axg_audio_hw_clks[] = { 816 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 817 [AUD_CLKID_PDM] = &pdm.hw, 818 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 819 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 820 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 821 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 822 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 823 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 824 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 825 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 826 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 827 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 828 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 829 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 830 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 831 [AUD_CLKID_LOOPBACK] = &loopback.hw, 832 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 833 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 834 [AUD_CLKID_RESAMPLE] = &resample.hw, 835 [AUD_CLKID_POWER_DETECT] = &power_detect.hw, 836 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw, 837 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw, 838 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw, 839 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw, 840 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw, 841 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw, 842 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw, 843 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw, 844 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw, 845 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw, 846 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw, 847 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw, 848 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw, 849 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw, 850 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw, 851 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw, 852 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw, 853 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw, 854 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 855 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 856 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 857 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 858 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 859 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 860 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 861 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 862 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 863 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 864 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 865 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 866 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 867 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 868 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 869 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 870 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 871 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 872 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 873 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 874 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 875 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 876 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 877 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 878 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 879 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 880 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 881 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 882 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 883 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 884 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 885 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 886 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 887 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 888 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 889 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 890 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 891 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 892 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 893 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 894 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 895 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 896 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 897 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 898 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 899 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 900 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 901 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 902 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 903 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 904 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 905 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 906 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 907 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 908 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 909 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 910 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 911 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 912 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 913 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 914 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 915 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 916 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 917 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 918 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 919 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 920 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 921 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 922 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 923 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 924 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 925 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 926 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 927 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw, 928 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw, 929 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw, 930 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 931 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 932 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 933 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 934 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 935 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 936 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 937 [AUD_CLKID_TOP] = &axg_aud_top, |
| 941}; 942 943/* 944 * Array of all G12A clocks provided by this provider 945 * The input clocks of the controller will be populated at runtime 946 */ | 938}; 939 940/* 941 * Array of all G12A clocks provided by this provider 942 * The input clocks of the controller will be populated at runtime 943 */ |
| 947static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = { 948 .hws = { 949 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 950 [AUD_CLKID_PDM] = &pdm.hw, 951 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 952 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 953 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 954 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 955 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 956 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 957 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 958 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 959 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 960 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 961 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 962 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 963 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 964 [AUD_CLKID_LOOPBACK] = &loopback.hw, 965 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 966 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 967 [AUD_CLKID_RESAMPLE] = &resample.hw, 968 [AUD_CLKID_POWER_DETECT] = &power_detect.hw, 969 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw, 970 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw, 971 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw, 972 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw, 973 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw, 974 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw, 975 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw, 976 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw, 977 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw, 978 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw, 979 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw, 980 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw, 981 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw, 982 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw, 983 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw, 984 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw, 985 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw, 986 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw, 987 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw, 988 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 989 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 990 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 991 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw, 992 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw, 993 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw, 994 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 995 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 996 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 997 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 998 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 999 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 1000 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 1001 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 1002 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 1003 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 1004 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 1005 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 1006 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 1007 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 1008 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 1009 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 1010 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 1011 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 1012 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 1013 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 1014 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 1015 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 1016 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 1017 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 1018 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 1019 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 1020 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 1021 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 1022 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 1023 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 1024 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 1025 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 1026 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 1027 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 1028 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 1029 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 1030 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 1031 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 1032 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 1033 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 1034 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 1035 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 1036 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 1037 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 1038 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 1039 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 1040 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 1041 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 1042 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 1043 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 1044 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 1045 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 1046 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 1047 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 1048 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 1049 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 1050 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 1051 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 1052 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 1053 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 1054 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 1055 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 1056 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 1057 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 1058 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 1059 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 1060 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 1061 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 1062 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 1063 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 1064 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw, 1065 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw, 1066 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw, 1067 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 1068 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 1069 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 1070 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 1071 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 1072 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 1073 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 1074 [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw, 1075 [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw, 1076 [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw, 1077 [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw, 1078 [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw, 1079 [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw, 1080 [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw, 1081 [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw, 1082 [AUD_CLKID_TOP] = &axg_aud_top, 1083 [NR_CLKS] = NULL, 1084 }, 1085 .num = NR_CLKS, | 944static struct clk_hw *g12a_audio_hw_clks[] = { 945 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 946 [AUD_CLKID_PDM] = &pdm.hw, 947 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 948 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 949 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 950 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 951 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 952 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 953 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 954 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 955 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 956 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 957 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 958 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 959 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 960 [AUD_CLKID_LOOPBACK] = &loopback.hw, 961 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 962 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 963 [AUD_CLKID_RESAMPLE] = &resample.hw, 964 [AUD_CLKID_POWER_DETECT] = &power_detect.hw, 965 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw, 966 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw, 967 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw, 968 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw, 969 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw, 970 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw, 971 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw, 972 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw, 973 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw, 974 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw, 975 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw, 976 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw, 977 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw, 978 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw, 979 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw, 980 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw, 981 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw, 982 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw, 983 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw, 984 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 985 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 986 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 987 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw, 988 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw, 989 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw, 990 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 991 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 992 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 993 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 994 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 995 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 996 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 997 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 998 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 999 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 1000 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 1001 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 1002 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 1003 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 1004 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 1005 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 1006 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 1007 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 1008 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 1009 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 1010 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 1011 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 1012 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 1013 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 1014 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 1015 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 1016 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 1017 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 1018 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 1019 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 1020 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 1021 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 1022 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 1023 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 1024 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 1025 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 1026 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 1027 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 1028 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 1029 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 1030 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 1031 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 1032 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 1033 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 1034 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 1035 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 1036 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 1037 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 1038 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 1039 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 1040 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 1041 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 1042 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 1043 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 1044 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 1045 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 1046 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 1047 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 1048 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 1049 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 1050 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 1051 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 1052 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 1053 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 1054 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 1055 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 1056 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 1057 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 1058 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 1059 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 1060 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw, 1061 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw, 1062 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw, 1063 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 1064 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 1065 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 1066 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 1067 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 1068 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 1069 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 1070 [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw, 1071 [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw, 1072 [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw, 1073 [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw, 1074 [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw, 1075 [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw, 1076 [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw, 1077 [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw, 1078 [AUD_CLKID_TOP] = &axg_aud_top, |
| 1086}; 1087 1088/* 1089 * Array of all SM1 clocks provided by this provider 1090 * The input clocks of the controller will be populated at runtime 1091 */ | 1079}; 1080 1081/* 1082 * Array of all SM1 clocks provided by this provider 1083 * The input clocks of the controller will be populated at runtime 1084 */ |
| 1092static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = { 1093 .hws = { 1094 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 1095 [AUD_CLKID_PDM] = &pdm.hw, 1096 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 1097 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 1098 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 1099 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 1100 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 1101 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 1102 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 1103 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 1104 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 1105 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 1106 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 1107 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 1108 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 1109 [AUD_CLKID_LOOPBACK] = &loopback.hw, 1110 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 1111 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 1112 [AUD_CLKID_RESAMPLE] = &resample.hw, 1113 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw, 1114 [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw, 1115 [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw, 1116 [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw, 1117 [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw, 1118 [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw, 1119 [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw, 1120 [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw, 1121 [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw, 1122 [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw, 1123 [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw, 1124 [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw, 1125 [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw, 1126 [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw, 1127 [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw, 1128 [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw, 1129 [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw, 1130 [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw, 1131 [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw, 1132 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 1133 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 1134 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 1135 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw, 1136 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw, 1137 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw, 1138 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 1139 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 1140 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 1141 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 1142 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 1143 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 1144 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 1145 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 1146 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 1147 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 1148 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 1149 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 1150 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 1151 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 1152 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 1153 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 1154 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 1155 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 1156 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 1157 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 1158 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 1159 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 1160 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 1161 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 1162 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 1163 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 1164 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 1165 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 1166 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 1167 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 1168 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 1169 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 1170 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 1171 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 1172 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 1173 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 1174 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 1175 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 1176 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 1177 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 1178 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 1179 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 1180 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 1181 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 1182 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 1183 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 1184 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 1185 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 1186 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 1187 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 1188 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 1189 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 1190 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 1191 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 1192 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 1193 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 1194 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 1195 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 1196 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 1197 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 1198 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 1199 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 1200 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 1201 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 1202 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 1203 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 1204 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 1205 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 1206 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 1207 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 1208 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw, 1209 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw, 1210 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw, 1211 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 1212 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 1213 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 1214 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 1215 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 1216 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 1217 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 1218 [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw, 1219 [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw, 1220 [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw, 1221 [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw, 1222 [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw, 1223 [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw, 1224 [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw, 1225 [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw, 1226 [AUD_CLKID_TOP] = &sm1_aud_top.hw, 1227 [AUD_CLKID_TORAM] = &toram.hw, 1228 [AUD_CLKID_EQDRC] = &eqdrc.hw, 1229 [AUD_CLKID_RESAMPLE_B] = &resample_b.hw, 1230 [AUD_CLKID_TOVAD] = &tovad.hw, 1231 [AUD_CLKID_LOCKER] = &locker.hw, 1232 [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw, 1233 [AUD_CLKID_FRDDR_D] = &frddr_d.hw, 1234 [AUD_CLKID_TODDR_D] = &toddr_d.hw, 1235 [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw, 1236 [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw, 1237 [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw, 1238 [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw, 1239 [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw, 1240 [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw, 1241 [NR_CLKS] = NULL, 1242 }, 1243 .num = NR_CLKS, | 1085static struct clk_hw *sm1_audio_hw_clks[] = { 1086 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 1087 [AUD_CLKID_PDM] = &pdm.hw, 1088 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 1089 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 1090 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 1091 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 1092 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 1093 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 1094 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 1095 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 1096 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 1097 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 1098 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 1099 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 1100 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 1101 [AUD_CLKID_LOOPBACK] = &loopback.hw, 1102 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 1103 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 1104 [AUD_CLKID_RESAMPLE] = &resample.hw, 1105 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw, 1106 [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw, 1107 [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw, 1108 [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw, 1109 [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw, 1110 [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw, 1111 [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw, 1112 [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw, 1113 [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw, 1114 [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw, 1115 [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw, 1116 [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw, 1117 [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw, 1118 [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw, 1119 [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw, 1120 [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw, 1121 [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw, 1122 [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw, 1123 [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw, 1124 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 1125 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 1126 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 1127 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw, 1128 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw, 1129 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw, 1130 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 1131 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 1132 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 1133 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 1134 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 1135 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 1136 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 1137 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 1138 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 1139 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 1140 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 1141 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 1142 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 1143 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 1144 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 1145 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 1146 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 1147 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 1148 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 1149 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 1150 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 1151 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 1152 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 1153 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 1154 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 1155 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 1156 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 1157 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 1158 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 1159 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 1160 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 1161 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 1162 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 1163 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 1164 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 1165 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 1166 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 1167 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 1168 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 1169 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 1170 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 1171 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 1172 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 1173 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 1174 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 1175 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 1176 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 1177 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 1178 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 1179 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 1180 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 1181 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 1182 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 1183 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 1184 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 1185 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 1186 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 1187 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 1188 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 1189 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 1190 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 1191 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 1192 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 1193 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 1194 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 1195 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 1196 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 1197 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 1198 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 1199 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 1200 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw, 1201 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw, 1202 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw, 1203 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 1204 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 1205 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 1206 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 1207 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 1208 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 1209 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 1210 [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw, 1211 [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw, 1212 [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw, 1213 [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw, 1214 [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw, 1215 [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw, 1216 [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw, 1217 [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw, 1218 [AUD_CLKID_TOP] = &sm1_aud_top.hw, 1219 [AUD_CLKID_TORAM] = &toram.hw, 1220 [AUD_CLKID_EQDRC] = &eqdrc.hw, 1221 [AUD_CLKID_RESAMPLE_B] = &resample_b.hw, 1222 [AUD_CLKID_TOVAD] = &tovad.hw, 1223 [AUD_CLKID_LOCKER] = &locker.hw, 1224 [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw, 1225 [AUD_CLKID_FRDDR_D] = &frddr_d.hw, 1226 [AUD_CLKID_TODDR_D] = &toddr_d.hw, 1227 [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw, 1228 [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw, 1229 [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw, 1230 [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw, 1231 [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw, 1232 [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw, |
| 1244}; 1245 1246 1247/* Convenience table to populate regmap in .probe(). */ 1248static struct clk_regmap *const axg_clk_regmaps[] = { 1249 &ddr_arb, 1250 &pdm, 1251 &tdmin_a, --- 488 unchanged lines hidden (view full) --- 1740 .val_bits = 32, 1741 .reg_stride = 4, 1742 .max_register = AUDIO_CLK_SPDIFOUT_B_CTRL, 1743}; 1744 1745struct audioclk_data { 1746 struct clk_regmap *const *regmap_clks; 1747 unsigned int regmap_clk_num; | 1233}; 1234 1235 1236/* Convenience table to populate regmap in .probe(). */ 1237static struct clk_regmap *const axg_clk_regmaps[] = { 1238 &ddr_arb, 1239 &pdm, 1240 &tdmin_a, --- 488 unchanged lines hidden (view full) --- 1729 .val_bits = 32, 1730 .reg_stride = 4, 1731 .max_register = AUDIO_CLK_SPDIFOUT_B_CTRL, 1732}; 1733 1734struct audioclk_data { 1735 struct clk_regmap *const *regmap_clks; 1736 unsigned int regmap_clk_num; |
| 1748 struct clk_hw_onecell_data *hw_onecell_data; | 1737 struct meson_clk_hw_data hw_clks; |
| 1749 unsigned int reset_offset; 1750 unsigned int reset_num; 1751}; 1752 1753static int axg_audio_clkc_probe(struct platform_device *pdev) 1754{ 1755 struct device *dev = &pdev->dev; 1756 const struct audioclk_data *data; --- 29 unchanged lines hidden (view full) --- 1786 return ret; 1787 } 1788 1789 /* Populate regmap for the regmap backed clocks */ 1790 for (i = 0; i < data->regmap_clk_num; i++) 1791 data->regmap_clks[i]->map = map; 1792 1793 /* Take care to skip the registered input clocks */ | 1738 unsigned int reset_offset; 1739 unsigned int reset_num; 1740}; 1741 1742static int axg_audio_clkc_probe(struct platform_device *pdev) 1743{ 1744 struct device *dev = &pdev->dev; 1745 const struct audioclk_data *data; --- 29 unchanged lines hidden (view full) --- 1775 return ret; 1776 } 1777 1778 /* Populate regmap for the regmap backed clocks */ 1779 for (i = 0; i < data->regmap_clk_num; i++) 1780 data->regmap_clks[i]->map = map; 1781 1782 /* Take care to skip the registered input clocks */ |
| 1794 for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) { | 1783 for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) { |
| 1795 const char *name; 1796 | 1784 const char *name; 1785 |
| 1797 hw = data->hw_onecell_data->hws[i]; | 1786 hw = data->hw_clks.hws[i]; |
| 1798 /* array might be sparse */ 1799 if (!hw) 1800 continue; 1801 1802 name = hw->init->name; 1803 1804 ret = devm_clk_hw_register(dev, hw); 1805 if (ret) { 1806 dev_err(dev, "failed to register clock %s\n", name); 1807 return ret; 1808 } 1809 } 1810 | 1787 /* array might be sparse */ 1788 if (!hw) 1789 continue; 1790 1791 name = hw->init->name; 1792 1793 ret = devm_clk_hw_register(dev, hw); 1794 if (ret) { 1795 dev_err(dev, "failed to register clock %s\n", name); 1796 return ret; 1797 } 1798 } 1799 |
| 1811 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 1812 data->hw_onecell_data); | 1800 ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks); |
| 1813 if (ret) 1814 return ret; 1815 1816 /* Stop here if there is no reset */ 1817 if (!data->reset_num) 1818 return 0; 1819 1820 rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); --- 8 unchanged lines hidden (view full) --- 1829 rst->rstc.owner = THIS_MODULE; 1830 1831 return devm_reset_controller_register(dev, &rst->rstc); 1832} 1833 1834static const struct audioclk_data axg_audioclk_data = { 1835 .regmap_clks = axg_clk_regmaps, 1836 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), | 1801 if (ret) 1802 return ret; 1803 1804 /* Stop here if there is no reset */ 1805 if (!data->reset_num) 1806 return 0; 1807 1808 rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); --- 8 unchanged lines hidden (view full) --- 1817 rst->rstc.owner = THIS_MODULE; 1818 1819 return devm_reset_controller_register(dev, &rst->rstc); 1820} 1821 1822static const struct audioclk_data axg_audioclk_data = { 1823 .regmap_clks = axg_clk_regmaps, 1824 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), |
| 1837 .hw_onecell_data = &axg_audio_hw_onecell_data, | 1825 .hw_clks = { 1826 .hws = axg_audio_hw_clks, 1827 .num = ARRAY_SIZE(axg_audio_hw_clks), 1828 }, |
| 1838}; 1839 1840static const struct audioclk_data g12a_audioclk_data = { 1841 .regmap_clks = g12a_clk_regmaps, 1842 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), | 1829}; 1830 1831static const struct audioclk_data g12a_audioclk_data = { 1832 .regmap_clks = g12a_clk_regmaps, 1833 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), |
| 1843 .hw_onecell_data = &g12a_audio_hw_onecell_data, | 1834 .hw_clks = { 1835 .hws = g12a_audio_hw_clks, 1836 .num = ARRAY_SIZE(g12a_audio_hw_clks), 1837 }, |
| 1844 .reset_offset = AUDIO_SW_RESET, 1845 .reset_num = 26, 1846}; 1847 1848static const struct audioclk_data sm1_audioclk_data = { 1849 .regmap_clks = sm1_clk_regmaps, 1850 .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps), | 1838 .reset_offset = AUDIO_SW_RESET, 1839 .reset_num = 26, 1840}; 1841 1842static const struct audioclk_data sm1_audioclk_data = { 1843 .regmap_clks = sm1_clk_regmaps, 1844 .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps), |
| 1851 .hw_onecell_data = &sm1_audio_hw_onecell_data, | 1845 .hw_clks = { 1846 .hws = sm1_audio_hw_clks, 1847 .num = ARRAY_SIZE(sm1_audio_hw_clks), 1848 }, |
| 1852 .reset_offset = AUDIO_SM1_SW_RESET0, 1853 .reset_num = 39, 1854}; 1855 1856static const struct of_device_id clkc_match_table[] = { 1857 { 1858 .compatible = "amlogic,axg-audio-clkc", 1859 .data = &axg_audioclk_data --- 22 unchanged lines hidden --- | 1849 .reset_offset = AUDIO_SM1_SW_RESET0, 1850 .reset_num = 39, 1851}; 1852 1853static const struct of_device_id clkc_match_table[] = { 1854 { 1855 .compatible = "amlogic,axg-audio-clkc", 1856 .data = &axg_audioclk_data --- 22 unchanged lines hidden --- |