1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/init.h> 10 #include <linux/of_device.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/reset.h> 15 #include <linux/reset-controller.h> 16 #include <linux/slab.h> 17 18 #include "meson-clkc-utils.h" 19 #include "axg-audio.h" 20 #include "clk-regmap.h" 21 #include "clk-phase.h" 22 #include "sclk-div.h" 23 24 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ 25 .data = &(struct clk_regmap_gate_data){ \ 26 .offset = (_reg), \ 27 .bit_idx = (_bit), \ 28 }, \ 29 .hw.init = &(struct clk_init_data) { \ 30 .name = "aud_"#_name, \ 31 .ops = &clk_regmap_gate_ops, \ 32 .parent_names = (const char *[]){ #_pname }, \ 33 .num_parents = 1, \ 34 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 35 }, \ 36 } 37 38 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) { \ 39 .data = &(struct clk_regmap_mux_data){ \ 40 .offset = (_reg), \ 41 .mask = (_mask), \ 42 .shift = (_shift), \ 43 .flags = (_dflags), \ 44 }, \ 45 .hw.init = &(struct clk_init_data){ \ 46 .name = "aud_"#_name, \ 47 .ops = &clk_regmap_mux_ops, \ 48 .parent_data = _pdata, \ 49 .num_parents = ARRAY_SIZE(_pdata), \ 50 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 51 }, \ 52 } 53 54 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ 55 .data = &(struct clk_regmap_div_data){ \ 56 .offset = (_reg), \ 57 .shift = (_shift), \ 58 .width = (_width), \ 59 .flags = (_dflags), \ 60 }, \ 61 .hw.init = &(struct clk_init_data){ \ 62 .name = "aud_"#_name, \ 63 .ops = &clk_regmap_divider_ops, \ 64 .parent_names = (const char *[]){ #_pname }, \ 65 .num_parents = 1, \ 66 .flags = (_iflags), \ 67 }, \ 68 } 69 70 #define AUD_PCLK_GATE(_name, _reg, _bit) { \ 71 .data = &(struct clk_regmap_gate_data){ \ 72 .offset = (_reg), \ 73 .bit_idx = (_bit), \ 74 }, \ 75 .hw.init = &(struct clk_init_data) { \ 76 .name = "aud_"#_name, \ 77 .ops = &clk_regmap_gate_ops, \ 78 .parent_names = (const char *[]){ "aud_top" }, \ 79 .num_parents = 1, \ 80 }, \ 81 } 82 83 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ 84 _hi_shift, _hi_width, _pname, _iflags) { \ 85 .data = &(struct meson_sclk_div_data) { \ 86 .div = { \ 87 .reg_off = (_reg), \ 88 .shift = (_div_shift), \ 89 .width = (_div_width), \ 90 }, \ 91 .hi = { \ 92 .reg_off = (_reg), \ 93 .shift = (_hi_shift), \ 94 .width = (_hi_width), \ 95 }, \ 96 }, \ 97 .hw.init = &(struct clk_init_data) { \ 98 .name = "aud_"#_name, \ 99 .ops = &meson_sclk_div_ops, \ 100 .parent_names = (const char *[]){ #_pname }, \ 101 .num_parents = 1, \ 102 .flags = (_iflags), \ 103 }, \ 104 } 105 106 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ 107 _pname, _iflags) { \ 108 .data = &(struct meson_clk_triphase_data) { \ 109 .ph0 = { \ 110 .reg_off = (_reg), \ 111 .shift = (_shift0), \ 112 .width = (_width), \ 113 }, \ 114 .ph1 = { \ 115 .reg_off = (_reg), \ 116 .shift = (_shift1), \ 117 .width = (_width), \ 118 }, \ 119 .ph2 = { \ 120 .reg_off = (_reg), \ 121 .shift = (_shift2), \ 122 .width = (_width), \ 123 }, \ 124 }, \ 125 .hw.init = &(struct clk_init_data) { \ 126 .name = "aud_"#_name, \ 127 .ops = &meson_clk_triphase_ops, \ 128 .parent_names = (const char *[]){ #_pname }, \ 129 .num_parents = 1, \ 130 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 131 }, \ 132 } 133 134 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ 135 .data = &(struct meson_clk_phase_data) { \ 136 .ph = { \ 137 .reg_off = (_reg), \ 138 .shift = (_shift), \ 139 .width = (_width), \ 140 }, \ 141 }, \ 142 .hw.init = &(struct clk_init_data) { \ 143 .name = "aud_"#_name, \ 144 .ops = &meson_clk_phase_ops, \ 145 .parent_names = (const char *[]){ #_pname }, \ 146 .num_parents = 1, \ 147 .flags = (_iflags), \ 148 }, \ 149 } 150 151 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ 152 _iflags) { \ 153 .data = &(struct meson_sclk_ws_inv_data) { \ 154 .ph = { \ 155 .reg_off = (_reg), \ 156 .shift = (_shift_ph), \ 157 .width = (_width), \ 158 }, \ 159 .ws = { \ 160 .reg_off = (_reg), \ 161 .shift = (_shift_ws), \ 162 .width = (_width), \ 163 }, \ 164 }, \ 165 .hw.init = &(struct clk_init_data) { \ 166 .name = "aud_"#_name, \ 167 .ops = &meson_clk_phase_ops, \ 168 .parent_names = (const char *[]){ #_pname }, \ 169 .num_parents = 1, \ 170 .flags = (_iflags), \ 171 }, \ 172 } 173 174 /* Audio Master Clocks */ 175 static const struct clk_parent_data mst_mux_parent_data[] = { 176 { .fw_name = "mst_in0", }, 177 { .fw_name = "mst_in1", }, 178 { .fw_name = "mst_in2", }, 179 { .fw_name = "mst_in3", }, 180 { .fw_name = "mst_in4", }, 181 { .fw_name = "mst_in5", }, 182 { .fw_name = "mst_in6", }, 183 { .fw_name = "mst_in7", }, 184 }; 185 186 #define AUD_MST_MUX(_name, _reg, _flag) \ 187 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \ 188 mst_mux_parent_data, 0) 189 #define AUD_MST_DIV(_name, _reg, _flag) \ 190 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \ 191 aud_##_name##_sel, CLK_SET_RATE_PARENT) 192 #define AUD_MST_MCLK_GATE(_name, _reg) \ 193 AUD_GATE(_name, _reg, 31, aud_##_name##_div, \ 194 CLK_SET_RATE_PARENT) 195 196 #define AUD_MST_MCLK_MUX(_name, _reg) \ 197 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST) 198 #define AUD_MST_MCLK_DIV(_name, _reg) \ 199 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST) 200 201 #define AUD_MST_SYS_MUX(_name, _reg) \ 202 AUD_MST_MUX(_name, _reg, 0) 203 #define AUD_MST_SYS_DIV(_name, _reg) \ 204 AUD_MST_DIV(_name, _reg, 0) 205 206 /* Sample Clocks */ 207 #define AUD_MST_SCLK_PRE_EN(_name, _reg) \ 208 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \ 209 aud_mst_##_name##_mclk, 0) 210 #define AUD_MST_SCLK_DIV(_name, _reg) \ 211 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \ 212 aud_mst_##_name##_sclk_pre_en, \ 213 CLK_SET_RATE_PARENT) 214 #define AUD_MST_SCLK_POST_EN(_name, _reg) \ 215 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \ 216 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT) 217 #define AUD_MST_SCLK(_name, _reg) \ 218 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \ 219 aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT) 220 221 #define AUD_MST_LRCLK_DIV(_name, _reg) \ 222 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \ 223 aud_mst_##_name##_sclk_post_en, 0) 224 #define AUD_MST_LRCLK(_name, _reg) \ 225 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \ 226 aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT) 227 228 /* TDM bit clock sources */ 229 static const struct clk_parent_data tdm_sclk_parent_data[] = { 230 { .name = "aud_mst_a_sclk", .index = -1, }, 231 { .name = "aud_mst_b_sclk", .index = -1, }, 232 { .name = "aud_mst_c_sclk", .index = -1, }, 233 { .name = "aud_mst_d_sclk", .index = -1, }, 234 { .name = "aud_mst_e_sclk", .index = -1, }, 235 { .name = "aud_mst_f_sclk", .index = -1, }, 236 { .fw_name = "slv_sclk0", }, 237 { .fw_name = "slv_sclk1", }, 238 { .fw_name = "slv_sclk2", }, 239 { .fw_name = "slv_sclk3", }, 240 { .fw_name = "slv_sclk4", }, 241 { .fw_name = "slv_sclk5", }, 242 { .fw_name = "slv_sclk6", }, 243 { .fw_name = "slv_sclk7", }, 244 { .fw_name = "slv_sclk8", }, 245 { .fw_name = "slv_sclk9", }, 246 }; 247 248 /* TDM sample clock sources */ 249 static const struct clk_parent_data tdm_lrclk_parent_data[] = { 250 { .name = "aud_mst_a_lrclk", .index = -1, }, 251 { .name = "aud_mst_b_lrclk", .index = -1, }, 252 { .name = "aud_mst_c_lrclk", .index = -1, }, 253 { .name = "aud_mst_d_lrclk", .index = -1, }, 254 { .name = "aud_mst_e_lrclk", .index = -1, }, 255 { .name = "aud_mst_f_lrclk", .index = -1, }, 256 { .fw_name = "slv_lrclk0", }, 257 { .fw_name = "slv_lrclk1", }, 258 { .fw_name = "slv_lrclk2", }, 259 { .fw_name = "slv_lrclk3", }, 260 { .fw_name = "slv_lrclk4", }, 261 { .fw_name = "slv_lrclk5", }, 262 { .fw_name = "slv_lrclk6", }, 263 { .fw_name = "slv_lrclk7", }, 264 { .fw_name = "slv_lrclk8", }, 265 { .fw_name = "slv_lrclk9", }, 266 }; 267 268 #define AUD_TDM_SCLK_MUX(_name, _reg) \ 269 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \ 270 CLK_MUX_ROUND_CLOSEST, tdm_sclk_parent_data, 0) 271 #define AUD_TDM_SCLK_PRE_EN(_name, _reg) \ 272 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \ 273 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT) 274 #define AUD_TDM_SCLK_POST_EN(_name, _reg) \ 275 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \ 276 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT) 277 #define AUD_TDM_SCLK(_name, _reg) \ 278 AUD_PHASE(tdm##_name##_sclk, _reg, 1, 29, \ 279 aud_tdm##_name##_sclk_post_en, \ 280 CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT) 281 #define AUD_TDM_SCLK_WS(_name, _reg) \ 282 AUD_SCLK_WS(tdm##_name##_sclk, _reg, 1, 29, 28, \ 283 aud_tdm##_name##_sclk_post_en, \ 284 CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT) 285 286 #define AUD_TDM_LRLCK(_name, _reg) \ 287 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \ 288 CLK_MUX_ROUND_CLOSEST, tdm_lrclk_parent_data, 0) 289 290 /* Pad master clock sources */ 291 static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = { 292 { .name = "aud_mst_a_mclk", .index = -1, }, 293 { .name = "aud_mst_b_mclk", .index = -1, }, 294 { .name = "aud_mst_c_mclk", .index = -1, }, 295 { .name = "aud_mst_d_mclk", .index = -1, }, 296 { .name = "aud_mst_e_mclk", .index = -1, }, 297 { .name = "aud_mst_f_mclk", .index = -1, }, 298 }; 299 300 /* Pad bit clock sources */ 301 static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = { 302 { .name = "aud_mst_a_sclk", .index = -1, }, 303 { .name = "aud_mst_b_sclk", .index = -1, }, 304 { .name = "aud_mst_c_sclk", .index = -1, }, 305 { .name = "aud_mst_d_sclk", .index = -1, }, 306 { .name = "aud_mst_e_sclk", .index = -1, }, 307 { .name = "aud_mst_f_sclk", .index = -1, }, 308 }; 309 310 /* Pad sample clock sources */ 311 static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = { 312 { .name = "aud_mst_a_lrclk", .index = -1, }, 313 { .name = "aud_mst_b_lrclk", .index = -1, }, 314 { .name = "aud_mst_c_lrclk", .index = -1, }, 315 { .name = "aud_mst_d_lrclk", .index = -1, }, 316 { .name = "aud_mst_e_lrclk", .index = -1, }, 317 { .name = "aud_mst_f_lrclk", .index = -1, }, 318 }; 319 320 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \ 321 AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \ 322 CLK_SET_RATE_NO_REPARENT) 323 324 /* Common Clocks */ 325 static struct clk_regmap ddr_arb = 326 AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0); 327 static struct clk_regmap pdm = 328 AUD_PCLK_GATE(pdm, AUDIO_CLK_GATE_EN, 1); 329 static struct clk_regmap tdmin_a = 330 AUD_PCLK_GATE(tdmin_a, AUDIO_CLK_GATE_EN, 2); 331 static struct clk_regmap tdmin_b = 332 AUD_PCLK_GATE(tdmin_b, AUDIO_CLK_GATE_EN, 3); 333 static struct clk_regmap tdmin_c = 334 AUD_PCLK_GATE(tdmin_c, AUDIO_CLK_GATE_EN, 4); 335 static struct clk_regmap tdmin_lb = 336 AUD_PCLK_GATE(tdmin_lb, AUDIO_CLK_GATE_EN, 5); 337 static struct clk_regmap tdmout_a = 338 AUD_PCLK_GATE(tdmout_a, AUDIO_CLK_GATE_EN, 6); 339 static struct clk_regmap tdmout_b = 340 AUD_PCLK_GATE(tdmout_b, AUDIO_CLK_GATE_EN, 7); 341 static struct clk_regmap tdmout_c = 342 AUD_PCLK_GATE(tdmout_c, AUDIO_CLK_GATE_EN, 8); 343 static struct clk_regmap frddr_a = 344 AUD_PCLK_GATE(frddr_a, AUDIO_CLK_GATE_EN, 9); 345 static struct clk_regmap frddr_b = 346 AUD_PCLK_GATE(frddr_b, AUDIO_CLK_GATE_EN, 10); 347 static struct clk_regmap frddr_c = 348 AUD_PCLK_GATE(frddr_c, AUDIO_CLK_GATE_EN, 11); 349 static struct clk_regmap toddr_a = 350 AUD_PCLK_GATE(toddr_a, AUDIO_CLK_GATE_EN, 12); 351 static struct clk_regmap toddr_b = 352 AUD_PCLK_GATE(toddr_b, AUDIO_CLK_GATE_EN, 13); 353 static struct clk_regmap toddr_c = 354 AUD_PCLK_GATE(toddr_c, AUDIO_CLK_GATE_EN, 14); 355 static struct clk_regmap loopback = 356 AUD_PCLK_GATE(loopback, AUDIO_CLK_GATE_EN, 15); 357 static struct clk_regmap spdifin = 358 AUD_PCLK_GATE(spdifin, AUDIO_CLK_GATE_EN, 16); 359 static struct clk_regmap spdifout = 360 AUD_PCLK_GATE(spdifout, AUDIO_CLK_GATE_EN, 17); 361 static struct clk_regmap resample = 362 AUD_PCLK_GATE(resample, AUDIO_CLK_GATE_EN, 18); 363 static struct clk_regmap power_detect = 364 AUD_PCLK_GATE(power_detect, AUDIO_CLK_GATE_EN, 19); 365 366 static struct clk_regmap spdifout_clk_sel = 367 AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 368 static struct clk_regmap pdm_dclk_sel = 369 AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 370 static struct clk_regmap spdifin_clk_sel = 371 AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 372 static struct clk_regmap pdm_sysclk_sel = 373 AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 374 static struct clk_regmap spdifout_b_clk_sel = 375 AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 376 377 static struct clk_regmap spdifout_clk_div = 378 AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 379 static struct clk_regmap pdm_dclk_div = 380 AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 381 static struct clk_regmap spdifin_clk_div = 382 AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 383 static struct clk_regmap pdm_sysclk_div = 384 AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 385 static struct clk_regmap spdifout_b_clk_div = 386 AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 387 388 static struct clk_regmap spdifout_clk = 389 AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 390 static struct clk_regmap spdifin_clk = 391 AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 392 static struct clk_regmap pdm_dclk = 393 AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 394 static struct clk_regmap pdm_sysclk = 395 AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 396 static struct clk_regmap spdifout_b_clk = 397 AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 398 399 static struct clk_regmap mst_a_sclk_pre_en = 400 AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0); 401 static struct clk_regmap mst_b_sclk_pre_en = 402 AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0); 403 static struct clk_regmap mst_c_sclk_pre_en = 404 AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0); 405 static struct clk_regmap mst_d_sclk_pre_en = 406 AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0); 407 static struct clk_regmap mst_e_sclk_pre_en = 408 AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0); 409 static struct clk_regmap mst_f_sclk_pre_en = 410 AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0); 411 412 static struct clk_regmap mst_a_sclk_div = 413 AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 414 static struct clk_regmap mst_b_sclk_div = 415 AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 416 static struct clk_regmap mst_c_sclk_div = 417 AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0); 418 static struct clk_regmap mst_d_sclk_div = 419 AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0); 420 static struct clk_regmap mst_e_sclk_div = 421 AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); 422 static struct clk_regmap mst_f_sclk_div = 423 AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 424 425 static struct clk_regmap mst_a_sclk_post_en = 426 AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0); 427 static struct clk_regmap mst_b_sclk_post_en = 428 AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0); 429 static struct clk_regmap mst_c_sclk_post_en = 430 AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0); 431 static struct clk_regmap mst_d_sclk_post_en = 432 AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0); 433 static struct clk_regmap mst_e_sclk_post_en = 434 AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0); 435 static struct clk_regmap mst_f_sclk_post_en = 436 AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0); 437 438 static struct clk_regmap mst_a_sclk = 439 AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1); 440 static struct clk_regmap mst_b_sclk = 441 AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1); 442 static struct clk_regmap mst_c_sclk = 443 AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1); 444 static struct clk_regmap mst_d_sclk = 445 AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1); 446 static struct clk_regmap mst_e_sclk = 447 AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1); 448 static struct clk_regmap mst_f_sclk = 449 AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1); 450 451 static struct clk_regmap mst_a_lrclk_div = 452 AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 453 static struct clk_regmap mst_b_lrclk_div = 454 AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 455 static struct clk_regmap mst_c_lrclk_div = 456 AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0); 457 static struct clk_regmap mst_d_lrclk_div = 458 AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0); 459 static struct clk_regmap mst_e_lrclk_div = 460 AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); 461 static struct clk_regmap mst_f_lrclk_div = 462 AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 463 464 static struct clk_regmap mst_a_lrclk = 465 AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1); 466 static struct clk_regmap mst_b_lrclk = 467 AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1); 468 static struct clk_regmap mst_c_lrclk = 469 AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1); 470 static struct clk_regmap mst_d_lrclk = 471 AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1); 472 static struct clk_regmap mst_e_lrclk = 473 AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1); 474 static struct clk_regmap mst_f_lrclk = 475 AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1); 476 477 static struct clk_regmap tdmin_a_sclk_sel = 478 AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL); 479 static struct clk_regmap tdmin_b_sclk_sel = 480 AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL); 481 static struct clk_regmap tdmin_c_sclk_sel = 482 AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL); 483 static struct clk_regmap tdmin_lb_sclk_sel = 484 AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 485 static struct clk_regmap tdmout_a_sclk_sel = 486 AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 487 static struct clk_regmap tdmout_b_sclk_sel = 488 AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 489 static struct clk_regmap tdmout_c_sclk_sel = 490 AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 491 492 static struct clk_regmap tdmin_a_sclk_pre_en = 493 AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 494 static struct clk_regmap tdmin_b_sclk_pre_en = 495 AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 496 static struct clk_regmap tdmin_c_sclk_pre_en = 497 AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL); 498 static struct clk_regmap tdmin_lb_sclk_pre_en = 499 AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 500 static struct clk_regmap tdmout_a_sclk_pre_en = 501 AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 502 static struct clk_regmap tdmout_b_sclk_pre_en = 503 AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 504 static struct clk_regmap tdmout_c_sclk_pre_en = 505 AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 506 507 static struct clk_regmap tdmin_a_sclk_post_en = 508 AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 509 static struct clk_regmap tdmin_b_sclk_post_en = 510 AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 511 static struct clk_regmap tdmin_c_sclk_post_en = 512 AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL); 513 static struct clk_regmap tdmin_lb_sclk_post_en = 514 AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 515 static struct clk_regmap tdmout_a_sclk_post_en = 516 AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 517 static struct clk_regmap tdmout_b_sclk_post_en = 518 AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 519 static struct clk_regmap tdmout_c_sclk_post_en = 520 AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 521 522 static struct clk_regmap tdmin_a_sclk = 523 AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 524 static struct clk_regmap tdmin_b_sclk = 525 AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 526 static struct clk_regmap tdmin_c_sclk = 527 AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL); 528 static struct clk_regmap tdmin_lb_sclk = 529 AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 530 531 static struct clk_regmap tdmin_a_lrclk = 532 AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 533 static struct clk_regmap tdmin_b_lrclk = 534 AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 535 static struct clk_regmap tdmin_c_lrclk = 536 AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL); 537 static struct clk_regmap tdmin_lb_lrclk = 538 AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 539 static struct clk_regmap tdmout_a_lrclk = 540 AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 541 static struct clk_regmap tdmout_b_lrclk = 542 AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 543 static struct clk_regmap tdmout_c_lrclk = 544 AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 545 546 /* AXG Clocks */ 547 static struct clk_regmap axg_tdmout_a_sclk = 548 AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 549 static struct clk_regmap axg_tdmout_b_sclk = 550 AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 551 static struct clk_regmap axg_tdmout_c_sclk = 552 AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 553 554 /* AXG/G12A Clocks */ 555 static struct clk_hw axg_aud_top = { 556 .init = &(struct clk_init_data) { 557 /* Provide aud_top signal name on axg and g12a */ 558 .name = "aud_top", 559 .ops = &(const struct clk_ops) {}, 560 .parent_data = &(const struct clk_parent_data) { 561 .fw_name = "pclk", 562 }, 563 .num_parents = 1, 564 }, 565 }; 566 567 static struct clk_regmap mst_a_mclk_sel = 568 AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL); 569 static struct clk_regmap mst_b_mclk_sel = 570 AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL); 571 static struct clk_regmap mst_c_mclk_sel = 572 AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL); 573 static struct clk_regmap mst_d_mclk_sel = 574 AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL); 575 static struct clk_regmap mst_e_mclk_sel = 576 AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL); 577 static struct clk_regmap mst_f_mclk_sel = 578 AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL); 579 580 static struct clk_regmap mst_a_mclk_div = 581 AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL); 582 static struct clk_regmap mst_b_mclk_div = 583 AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL); 584 static struct clk_regmap mst_c_mclk_div = 585 AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL); 586 static struct clk_regmap mst_d_mclk_div = 587 AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL); 588 static struct clk_regmap mst_e_mclk_div = 589 AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL); 590 static struct clk_regmap mst_f_mclk_div = 591 AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL); 592 593 static struct clk_regmap mst_a_mclk = 594 AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL); 595 static struct clk_regmap mst_b_mclk = 596 AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL); 597 static struct clk_regmap mst_c_mclk = 598 AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL); 599 static struct clk_regmap mst_d_mclk = 600 AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL); 601 static struct clk_regmap mst_e_mclk = 602 AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL); 603 static struct clk_regmap mst_f_mclk = 604 AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL); 605 606 /* G12a clocks */ 607 static struct clk_regmap g12a_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL( 608 mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data); 609 static struct clk_regmap g12a_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL( 610 mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data); 611 static struct clk_regmap g12a_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL( 612 lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data); 613 static struct clk_regmap g12a_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL( 614 lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data); 615 static struct clk_regmap g12a_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL( 616 lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data); 617 static struct clk_regmap g12a_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL( 618 sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data); 619 static struct clk_regmap g12a_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL( 620 sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data); 621 static struct clk_regmap g12a_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL( 622 sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data); 623 624 static struct clk_regmap g12a_tdmout_a_sclk = 625 AUD_TDM_SCLK_WS(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 626 static struct clk_regmap g12a_tdmout_b_sclk = 627 AUD_TDM_SCLK_WS(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 628 static struct clk_regmap g12a_tdmout_c_sclk = 629 AUD_TDM_SCLK_WS(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 630 631 static struct clk_regmap toram = 632 AUD_PCLK_GATE(toram, AUDIO_CLK_GATE_EN, 20); 633 static struct clk_regmap spdifout_b = 634 AUD_PCLK_GATE(spdifout_b, AUDIO_CLK_GATE_EN, 21); 635 static struct clk_regmap eqdrc = 636 AUD_PCLK_GATE(eqdrc, AUDIO_CLK_GATE_EN, 22); 637 638 /* SM1 Clocks */ 639 static struct clk_regmap sm1_clk81_en = { 640 .data = &(struct clk_regmap_gate_data){ 641 .offset = AUDIO_CLK81_EN, 642 .bit_idx = 31, 643 }, 644 .hw.init = &(struct clk_init_data) { 645 .name = "aud_clk81_en", 646 .ops = &clk_regmap_gate_ops, 647 .parent_data = &(const struct clk_parent_data) { 648 .fw_name = "pclk", 649 }, 650 .num_parents = 1, 651 }, 652 }; 653 654 static struct clk_regmap sm1_sysclk_a_div = { 655 .data = &(struct clk_regmap_div_data){ 656 .offset = AUDIO_CLK81_CTRL, 657 .shift = 0, 658 .width = 8, 659 }, 660 .hw.init = &(struct clk_init_data) { 661 .name = "aud_sysclk_a_div", 662 .ops = &clk_regmap_divider_ops, 663 .parent_hws = (const struct clk_hw *[]) { 664 &sm1_clk81_en.hw, 665 }, 666 .num_parents = 1, 667 .flags = CLK_SET_RATE_PARENT, 668 }, 669 }; 670 671 static struct clk_regmap sm1_sysclk_a_en = { 672 .data = &(struct clk_regmap_gate_data){ 673 .offset = AUDIO_CLK81_CTRL, 674 .bit_idx = 8, 675 }, 676 .hw.init = &(struct clk_init_data) { 677 .name = "aud_sysclk_a_en", 678 .ops = &clk_regmap_gate_ops, 679 .parent_hws = (const struct clk_hw *[]) { 680 &sm1_sysclk_a_div.hw, 681 }, 682 .num_parents = 1, 683 .flags = CLK_SET_RATE_PARENT, 684 }, 685 }; 686 687 static struct clk_regmap sm1_sysclk_b_div = { 688 .data = &(struct clk_regmap_div_data){ 689 .offset = AUDIO_CLK81_CTRL, 690 .shift = 16, 691 .width = 8, 692 }, 693 .hw.init = &(struct clk_init_data) { 694 .name = "aud_sysclk_b_div", 695 .ops = &clk_regmap_divider_ops, 696 .parent_hws = (const struct clk_hw *[]) { 697 &sm1_clk81_en.hw, 698 }, 699 .num_parents = 1, 700 .flags = CLK_SET_RATE_PARENT, 701 }, 702 }; 703 704 static struct clk_regmap sm1_sysclk_b_en = { 705 .data = &(struct clk_regmap_gate_data){ 706 .offset = AUDIO_CLK81_CTRL, 707 .bit_idx = 24, 708 }, 709 .hw.init = &(struct clk_init_data) { 710 .name = "aud_sysclk_b_en", 711 .ops = &clk_regmap_gate_ops, 712 .parent_hws = (const struct clk_hw *[]) { 713 &sm1_sysclk_b_div.hw, 714 }, 715 .num_parents = 1, 716 .flags = CLK_SET_RATE_PARENT, 717 }, 718 }; 719 720 static const struct clk_hw *sm1_aud_top_parents[] = { 721 &sm1_sysclk_a_en.hw, 722 &sm1_sysclk_b_en.hw, 723 }; 724 725 static struct clk_regmap sm1_aud_top = { 726 .data = &(struct clk_regmap_mux_data){ 727 .offset = AUDIO_CLK81_CTRL, 728 .mask = 0x1, 729 .shift = 31, 730 }, 731 .hw.init = &(struct clk_init_data){ 732 .name = "aud_top", 733 .ops = &clk_regmap_mux_ops, 734 .parent_hws = sm1_aud_top_parents, 735 .num_parents = ARRAY_SIZE(sm1_aud_top_parents), 736 .flags = CLK_SET_RATE_NO_REPARENT, 737 }, 738 }; 739 740 static struct clk_regmap resample_b = 741 AUD_PCLK_GATE(resample_b, AUDIO_CLK_GATE_EN, 26); 742 static struct clk_regmap tovad = 743 AUD_PCLK_GATE(tovad, AUDIO_CLK_GATE_EN, 27); 744 static struct clk_regmap locker = 745 AUD_PCLK_GATE(locker, AUDIO_CLK_GATE_EN, 28); 746 static struct clk_regmap spdifin_lb = 747 AUD_PCLK_GATE(spdifin_lb, AUDIO_CLK_GATE_EN, 29); 748 static struct clk_regmap frddr_d = 749 AUD_PCLK_GATE(frddr_d, AUDIO_CLK_GATE_EN1, 0); 750 static struct clk_regmap toddr_d = 751 AUD_PCLK_GATE(toddr_d, AUDIO_CLK_GATE_EN1, 1); 752 static struct clk_regmap loopback_b = 753 AUD_PCLK_GATE(loopback_b, AUDIO_CLK_GATE_EN1, 2); 754 755 static struct clk_regmap sm1_mst_a_mclk_sel = 756 AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL); 757 static struct clk_regmap sm1_mst_b_mclk_sel = 758 AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL); 759 static struct clk_regmap sm1_mst_c_mclk_sel = 760 AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL); 761 static struct clk_regmap sm1_mst_d_mclk_sel = 762 AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL); 763 static struct clk_regmap sm1_mst_e_mclk_sel = 764 AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL); 765 static struct clk_regmap sm1_mst_f_mclk_sel = 766 AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL); 767 768 static struct clk_regmap sm1_mst_a_mclk_div = 769 AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL); 770 static struct clk_regmap sm1_mst_b_mclk_div = 771 AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL); 772 static struct clk_regmap sm1_mst_c_mclk_div = 773 AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL); 774 static struct clk_regmap sm1_mst_d_mclk_div = 775 AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL); 776 static struct clk_regmap sm1_mst_e_mclk_div = 777 AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL); 778 static struct clk_regmap sm1_mst_f_mclk_div = 779 AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL); 780 781 static struct clk_regmap sm1_mst_a_mclk = 782 AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_SM1_MCLK_A_CTRL); 783 static struct clk_regmap sm1_mst_b_mclk = 784 AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_SM1_MCLK_B_CTRL); 785 static struct clk_regmap sm1_mst_c_mclk = 786 AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_SM1_MCLK_C_CTRL); 787 static struct clk_regmap sm1_mst_d_mclk = 788 AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_SM1_MCLK_D_CTRL); 789 static struct clk_regmap sm1_mst_e_mclk = 790 AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_SM1_MCLK_E_CTRL); 791 static struct clk_regmap sm1_mst_f_mclk = 792 AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_SM1_MCLK_F_CTRL); 793 794 static struct clk_regmap sm1_tdm_mclk_pad_0 = AUD_TDM_PAD_CTRL( 795 tdm_mclk_pad_0, AUDIO_SM1_MST_PAD_CTRL0, 0, mclk_pad_ctrl_parent_data); 796 static struct clk_regmap sm1_tdm_mclk_pad_1 = AUD_TDM_PAD_CTRL( 797 tdm_mclk_pad_1, AUDIO_SM1_MST_PAD_CTRL0, 4, mclk_pad_ctrl_parent_data); 798 static struct clk_regmap sm1_tdm_lrclk_pad_0 = AUD_TDM_PAD_CTRL( 799 tdm_lrclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 16, lrclk_pad_ctrl_parent_data); 800 static struct clk_regmap sm1_tdm_lrclk_pad_1 = AUD_TDM_PAD_CTRL( 801 tdm_lrclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 20, lrclk_pad_ctrl_parent_data); 802 static struct clk_regmap sm1_tdm_lrclk_pad_2 = AUD_TDM_PAD_CTRL( 803 tdm_lrclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 24, lrclk_pad_ctrl_parent_data); 804 static struct clk_regmap sm1_tdm_sclk_pad_0 = AUD_TDM_PAD_CTRL( 805 tdm_sclk_pad_0, AUDIO_SM1_MST_PAD_CTRL1, 0, sclk_pad_ctrl_parent_data); 806 static struct clk_regmap sm1_tdm_sclk_pad_1 = AUD_TDM_PAD_CTRL( 807 tdm_sclk_pad_1, AUDIO_SM1_MST_PAD_CTRL1, 4, sclk_pad_ctrl_parent_data); 808 static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL( 809 tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data); 810 811 /* 812 * Array of all clocks provided by this provider 813 * The input clocks of the controller will be populated at runtime 814 */ 815 static struct clk_hw *axg_audio_hw_clks[] = { 816 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 817 [AUD_CLKID_PDM] = &pdm.hw, 818 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 819 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 820 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 821 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 822 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 823 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 824 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 825 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 826 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 827 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 828 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 829 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 830 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 831 [AUD_CLKID_LOOPBACK] = &loopback.hw, 832 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 833 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 834 [AUD_CLKID_RESAMPLE] = &resample.hw, 835 [AUD_CLKID_POWER_DETECT] = &power_detect.hw, 836 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw, 837 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw, 838 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw, 839 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw, 840 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw, 841 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw, 842 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw, 843 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw, 844 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw, 845 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw, 846 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw, 847 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw, 848 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw, 849 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw, 850 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw, 851 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw, 852 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw, 853 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw, 854 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 855 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 856 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 857 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 858 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 859 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 860 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 861 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 862 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 863 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 864 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 865 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 866 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 867 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 868 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 869 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 870 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 871 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 872 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 873 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 874 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 875 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 876 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 877 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 878 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 879 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 880 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 881 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 882 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 883 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 884 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 885 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 886 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 887 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 888 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 889 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 890 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 891 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 892 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 893 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 894 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 895 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 896 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 897 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 898 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 899 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 900 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 901 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 902 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 903 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 904 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 905 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 906 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 907 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 908 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 909 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 910 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 911 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 912 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 913 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 914 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 915 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 916 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 917 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 918 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 919 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 920 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 921 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 922 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 923 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 924 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 925 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 926 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 927 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw, 928 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw, 929 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw, 930 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 931 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 932 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 933 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 934 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 935 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 936 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 937 [AUD_CLKID_TOP] = &axg_aud_top, 938 }; 939 940 /* 941 * Array of all G12A clocks provided by this provider 942 * The input clocks of the controller will be populated at runtime 943 */ 944 static struct clk_hw *g12a_audio_hw_clks[] = { 945 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 946 [AUD_CLKID_PDM] = &pdm.hw, 947 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 948 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 949 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 950 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 951 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 952 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 953 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 954 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 955 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 956 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 957 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 958 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 959 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 960 [AUD_CLKID_LOOPBACK] = &loopback.hw, 961 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 962 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 963 [AUD_CLKID_RESAMPLE] = &resample.hw, 964 [AUD_CLKID_POWER_DETECT] = &power_detect.hw, 965 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw, 966 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw, 967 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw, 968 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw, 969 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw, 970 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw, 971 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw, 972 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw, 973 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw, 974 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw, 975 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw, 976 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw, 977 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw, 978 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw, 979 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw, 980 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw, 981 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw, 982 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw, 983 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw, 984 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 985 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 986 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 987 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw, 988 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw, 989 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw, 990 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 991 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 992 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 993 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 994 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 995 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 996 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 997 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 998 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 999 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 1000 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 1001 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 1002 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 1003 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 1004 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 1005 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 1006 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 1007 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 1008 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 1009 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 1010 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 1011 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 1012 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 1013 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 1014 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 1015 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 1016 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 1017 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 1018 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 1019 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 1020 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 1021 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 1022 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 1023 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 1024 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 1025 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 1026 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 1027 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 1028 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 1029 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 1030 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 1031 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 1032 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 1033 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 1034 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 1035 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 1036 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 1037 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 1038 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 1039 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 1040 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 1041 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 1042 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 1043 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 1044 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 1045 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 1046 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 1047 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 1048 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 1049 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 1050 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 1051 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 1052 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 1053 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 1054 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 1055 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 1056 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 1057 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 1058 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 1059 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 1060 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw, 1061 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw, 1062 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw, 1063 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 1064 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 1065 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 1066 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 1067 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 1068 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 1069 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 1070 [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw, 1071 [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw, 1072 [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw, 1073 [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw, 1074 [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw, 1075 [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw, 1076 [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw, 1077 [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw, 1078 [AUD_CLKID_TOP] = &axg_aud_top, 1079 }; 1080 1081 /* 1082 * Array of all SM1 clocks provided by this provider 1083 * The input clocks of the controller will be populated at runtime 1084 */ 1085 static struct clk_hw *sm1_audio_hw_clks[] = { 1086 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw, 1087 [AUD_CLKID_PDM] = &pdm.hw, 1088 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw, 1089 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw, 1090 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw, 1091 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw, 1092 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw, 1093 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw, 1094 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw, 1095 [AUD_CLKID_FRDDR_A] = &frddr_a.hw, 1096 [AUD_CLKID_FRDDR_B] = &frddr_b.hw, 1097 [AUD_CLKID_FRDDR_C] = &frddr_c.hw, 1098 [AUD_CLKID_TODDR_A] = &toddr_a.hw, 1099 [AUD_CLKID_TODDR_B] = &toddr_b.hw, 1100 [AUD_CLKID_TODDR_C] = &toddr_c.hw, 1101 [AUD_CLKID_LOOPBACK] = &loopback.hw, 1102 [AUD_CLKID_SPDIFIN] = &spdifin.hw, 1103 [AUD_CLKID_SPDIFOUT] = &spdifout.hw, 1104 [AUD_CLKID_RESAMPLE] = &resample.hw, 1105 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw, 1106 [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw, 1107 [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw, 1108 [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw, 1109 [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw, 1110 [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw, 1111 [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw, 1112 [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw, 1113 [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw, 1114 [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw, 1115 [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw, 1116 [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw, 1117 [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw, 1118 [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw, 1119 [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw, 1120 [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw, 1121 [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw, 1122 [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw, 1123 [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw, 1124 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw, 1125 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw, 1126 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw, 1127 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw, 1128 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw, 1129 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw, 1130 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw, 1131 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw, 1132 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw, 1133 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw, 1134 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw, 1135 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw, 1136 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw, 1137 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw, 1138 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw, 1139 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw, 1140 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw, 1141 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw, 1142 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw, 1143 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw, 1144 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw, 1145 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw, 1146 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw, 1147 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw, 1148 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw, 1149 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw, 1150 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw, 1151 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw, 1152 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw, 1153 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw, 1154 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw, 1155 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw, 1156 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw, 1157 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw, 1158 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw, 1159 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw, 1160 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw, 1161 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw, 1162 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw, 1163 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw, 1164 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw, 1165 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw, 1166 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw, 1167 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw, 1168 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw, 1169 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw, 1170 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw, 1171 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw, 1172 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw, 1173 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw, 1174 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw, 1175 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw, 1176 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw, 1177 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw, 1178 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw, 1179 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw, 1180 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw, 1181 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw, 1182 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw, 1183 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw, 1184 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw, 1185 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw, 1186 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw, 1187 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw, 1188 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw, 1189 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw, 1190 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw, 1191 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw, 1192 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw, 1193 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw, 1194 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw, 1195 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw, 1196 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw, 1197 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw, 1198 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw, 1199 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw, 1200 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw, 1201 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw, 1202 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw, 1203 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw, 1204 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw, 1205 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw, 1206 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw, 1207 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw, 1208 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw, 1209 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw, 1210 [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw, 1211 [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw, 1212 [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw, 1213 [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw, 1214 [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw, 1215 [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw, 1216 [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw, 1217 [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw, 1218 [AUD_CLKID_TOP] = &sm1_aud_top.hw, 1219 [AUD_CLKID_TORAM] = &toram.hw, 1220 [AUD_CLKID_EQDRC] = &eqdrc.hw, 1221 [AUD_CLKID_RESAMPLE_B] = &resample_b.hw, 1222 [AUD_CLKID_TOVAD] = &tovad.hw, 1223 [AUD_CLKID_LOCKER] = &locker.hw, 1224 [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw, 1225 [AUD_CLKID_FRDDR_D] = &frddr_d.hw, 1226 [AUD_CLKID_TODDR_D] = &toddr_d.hw, 1227 [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw, 1228 [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw, 1229 [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw, 1230 [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw, 1231 [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw, 1232 [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw, 1233 }; 1234 1235 1236 /* Convenience table to populate regmap in .probe(). */ 1237 static struct clk_regmap *const axg_clk_regmaps[] = { 1238 &ddr_arb, 1239 &pdm, 1240 &tdmin_a, 1241 &tdmin_b, 1242 &tdmin_c, 1243 &tdmin_lb, 1244 &tdmout_a, 1245 &tdmout_b, 1246 &tdmout_c, 1247 &frddr_a, 1248 &frddr_b, 1249 &frddr_c, 1250 &toddr_a, 1251 &toddr_b, 1252 &toddr_c, 1253 &loopback, 1254 &spdifin, 1255 &spdifout, 1256 &resample, 1257 &power_detect, 1258 &mst_a_mclk_sel, 1259 &mst_b_mclk_sel, 1260 &mst_c_mclk_sel, 1261 &mst_d_mclk_sel, 1262 &mst_e_mclk_sel, 1263 &mst_f_mclk_sel, 1264 &mst_a_mclk_div, 1265 &mst_b_mclk_div, 1266 &mst_c_mclk_div, 1267 &mst_d_mclk_div, 1268 &mst_e_mclk_div, 1269 &mst_f_mclk_div, 1270 &mst_a_mclk, 1271 &mst_b_mclk, 1272 &mst_c_mclk, 1273 &mst_d_mclk, 1274 &mst_e_mclk, 1275 &mst_f_mclk, 1276 &spdifout_clk_sel, 1277 &spdifout_clk_div, 1278 &spdifout_clk, 1279 &spdifin_clk_sel, 1280 &spdifin_clk_div, 1281 &spdifin_clk, 1282 &pdm_dclk_sel, 1283 &pdm_dclk_div, 1284 &pdm_dclk, 1285 &pdm_sysclk_sel, 1286 &pdm_sysclk_div, 1287 &pdm_sysclk, 1288 &mst_a_sclk_pre_en, 1289 &mst_b_sclk_pre_en, 1290 &mst_c_sclk_pre_en, 1291 &mst_d_sclk_pre_en, 1292 &mst_e_sclk_pre_en, 1293 &mst_f_sclk_pre_en, 1294 &mst_a_sclk_div, 1295 &mst_b_sclk_div, 1296 &mst_c_sclk_div, 1297 &mst_d_sclk_div, 1298 &mst_e_sclk_div, 1299 &mst_f_sclk_div, 1300 &mst_a_sclk_post_en, 1301 &mst_b_sclk_post_en, 1302 &mst_c_sclk_post_en, 1303 &mst_d_sclk_post_en, 1304 &mst_e_sclk_post_en, 1305 &mst_f_sclk_post_en, 1306 &mst_a_sclk, 1307 &mst_b_sclk, 1308 &mst_c_sclk, 1309 &mst_d_sclk, 1310 &mst_e_sclk, 1311 &mst_f_sclk, 1312 &mst_a_lrclk_div, 1313 &mst_b_lrclk_div, 1314 &mst_c_lrclk_div, 1315 &mst_d_lrclk_div, 1316 &mst_e_lrclk_div, 1317 &mst_f_lrclk_div, 1318 &mst_a_lrclk, 1319 &mst_b_lrclk, 1320 &mst_c_lrclk, 1321 &mst_d_lrclk, 1322 &mst_e_lrclk, 1323 &mst_f_lrclk, 1324 &tdmin_a_sclk_sel, 1325 &tdmin_b_sclk_sel, 1326 &tdmin_c_sclk_sel, 1327 &tdmin_lb_sclk_sel, 1328 &tdmout_a_sclk_sel, 1329 &tdmout_b_sclk_sel, 1330 &tdmout_c_sclk_sel, 1331 &tdmin_a_sclk_pre_en, 1332 &tdmin_b_sclk_pre_en, 1333 &tdmin_c_sclk_pre_en, 1334 &tdmin_lb_sclk_pre_en, 1335 &tdmout_a_sclk_pre_en, 1336 &tdmout_b_sclk_pre_en, 1337 &tdmout_c_sclk_pre_en, 1338 &tdmin_a_sclk_post_en, 1339 &tdmin_b_sclk_post_en, 1340 &tdmin_c_sclk_post_en, 1341 &tdmin_lb_sclk_post_en, 1342 &tdmout_a_sclk_post_en, 1343 &tdmout_b_sclk_post_en, 1344 &tdmout_c_sclk_post_en, 1345 &tdmin_a_sclk, 1346 &tdmin_b_sclk, 1347 &tdmin_c_sclk, 1348 &tdmin_lb_sclk, 1349 &axg_tdmout_a_sclk, 1350 &axg_tdmout_b_sclk, 1351 &axg_tdmout_c_sclk, 1352 &tdmin_a_lrclk, 1353 &tdmin_b_lrclk, 1354 &tdmin_c_lrclk, 1355 &tdmin_lb_lrclk, 1356 &tdmout_a_lrclk, 1357 &tdmout_b_lrclk, 1358 &tdmout_c_lrclk, 1359 }; 1360 1361 static struct clk_regmap *const g12a_clk_regmaps[] = { 1362 &ddr_arb, 1363 &pdm, 1364 &tdmin_a, 1365 &tdmin_b, 1366 &tdmin_c, 1367 &tdmin_lb, 1368 &tdmout_a, 1369 &tdmout_b, 1370 &tdmout_c, 1371 &frddr_a, 1372 &frddr_b, 1373 &frddr_c, 1374 &toddr_a, 1375 &toddr_b, 1376 &toddr_c, 1377 &loopback, 1378 &spdifin, 1379 &spdifout, 1380 &resample, 1381 &power_detect, 1382 &spdifout_b, 1383 &mst_a_mclk_sel, 1384 &mst_b_mclk_sel, 1385 &mst_c_mclk_sel, 1386 &mst_d_mclk_sel, 1387 &mst_e_mclk_sel, 1388 &mst_f_mclk_sel, 1389 &mst_a_mclk_div, 1390 &mst_b_mclk_div, 1391 &mst_c_mclk_div, 1392 &mst_d_mclk_div, 1393 &mst_e_mclk_div, 1394 &mst_f_mclk_div, 1395 &mst_a_mclk, 1396 &mst_b_mclk, 1397 &mst_c_mclk, 1398 &mst_d_mclk, 1399 &mst_e_mclk, 1400 &mst_f_mclk, 1401 &spdifout_clk_sel, 1402 &spdifout_clk_div, 1403 &spdifout_clk, 1404 &spdifin_clk_sel, 1405 &spdifin_clk_div, 1406 &spdifin_clk, 1407 &pdm_dclk_sel, 1408 &pdm_dclk_div, 1409 &pdm_dclk, 1410 &pdm_sysclk_sel, 1411 &pdm_sysclk_div, 1412 &pdm_sysclk, 1413 &mst_a_sclk_pre_en, 1414 &mst_b_sclk_pre_en, 1415 &mst_c_sclk_pre_en, 1416 &mst_d_sclk_pre_en, 1417 &mst_e_sclk_pre_en, 1418 &mst_f_sclk_pre_en, 1419 &mst_a_sclk_div, 1420 &mst_b_sclk_div, 1421 &mst_c_sclk_div, 1422 &mst_d_sclk_div, 1423 &mst_e_sclk_div, 1424 &mst_f_sclk_div, 1425 &mst_a_sclk_post_en, 1426 &mst_b_sclk_post_en, 1427 &mst_c_sclk_post_en, 1428 &mst_d_sclk_post_en, 1429 &mst_e_sclk_post_en, 1430 &mst_f_sclk_post_en, 1431 &mst_a_sclk, 1432 &mst_b_sclk, 1433 &mst_c_sclk, 1434 &mst_d_sclk, 1435 &mst_e_sclk, 1436 &mst_f_sclk, 1437 &mst_a_lrclk_div, 1438 &mst_b_lrclk_div, 1439 &mst_c_lrclk_div, 1440 &mst_d_lrclk_div, 1441 &mst_e_lrclk_div, 1442 &mst_f_lrclk_div, 1443 &mst_a_lrclk, 1444 &mst_b_lrclk, 1445 &mst_c_lrclk, 1446 &mst_d_lrclk, 1447 &mst_e_lrclk, 1448 &mst_f_lrclk, 1449 &tdmin_a_sclk_sel, 1450 &tdmin_b_sclk_sel, 1451 &tdmin_c_sclk_sel, 1452 &tdmin_lb_sclk_sel, 1453 &tdmout_a_sclk_sel, 1454 &tdmout_b_sclk_sel, 1455 &tdmout_c_sclk_sel, 1456 &tdmin_a_sclk_pre_en, 1457 &tdmin_b_sclk_pre_en, 1458 &tdmin_c_sclk_pre_en, 1459 &tdmin_lb_sclk_pre_en, 1460 &tdmout_a_sclk_pre_en, 1461 &tdmout_b_sclk_pre_en, 1462 &tdmout_c_sclk_pre_en, 1463 &tdmin_a_sclk_post_en, 1464 &tdmin_b_sclk_post_en, 1465 &tdmin_c_sclk_post_en, 1466 &tdmin_lb_sclk_post_en, 1467 &tdmout_a_sclk_post_en, 1468 &tdmout_b_sclk_post_en, 1469 &tdmout_c_sclk_post_en, 1470 &tdmin_a_sclk, 1471 &tdmin_b_sclk, 1472 &tdmin_c_sclk, 1473 &tdmin_lb_sclk, 1474 &g12a_tdmout_a_sclk, 1475 &g12a_tdmout_b_sclk, 1476 &g12a_tdmout_c_sclk, 1477 &tdmin_a_lrclk, 1478 &tdmin_b_lrclk, 1479 &tdmin_c_lrclk, 1480 &tdmin_lb_lrclk, 1481 &tdmout_a_lrclk, 1482 &tdmout_b_lrclk, 1483 &tdmout_c_lrclk, 1484 &spdifout_b_clk_sel, 1485 &spdifout_b_clk_div, 1486 &spdifout_b_clk, 1487 &g12a_tdm_mclk_pad_0, 1488 &g12a_tdm_mclk_pad_1, 1489 &g12a_tdm_lrclk_pad_0, 1490 &g12a_tdm_lrclk_pad_1, 1491 &g12a_tdm_lrclk_pad_2, 1492 &g12a_tdm_sclk_pad_0, 1493 &g12a_tdm_sclk_pad_1, 1494 &g12a_tdm_sclk_pad_2, 1495 &toram, 1496 &eqdrc, 1497 }; 1498 1499 static struct clk_regmap *const sm1_clk_regmaps[] = { 1500 &ddr_arb, 1501 &pdm, 1502 &tdmin_a, 1503 &tdmin_b, 1504 &tdmin_c, 1505 &tdmin_lb, 1506 &tdmout_a, 1507 &tdmout_b, 1508 &tdmout_c, 1509 &frddr_a, 1510 &frddr_b, 1511 &frddr_c, 1512 &toddr_a, 1513 &toddr_b, 1514 &toddr_c, 1515 &loopback, 1516 &spdifin, 1517 &spdifout, 1518 &resample, 1519 &spdifout_b, 1520 &sm1_mst_a_mclk_sel, 1521 &sm1_mst_b_mclk_sel, 1522 &sm1_mst_c_mclk_sel, 1523 &sm1_mst_d_mclk_sel, 1524 &sm1_mst_e_mclk_sel, 1525 &sm1_mst_f_mclk_sel, 1526 &sm1_mst_a_mclk_div, 1527 &sm1_mst_b_mclk_div, 1528 &sm1_mst_c_mclk_div, 1529 &sm1_mst_d_mclk_div, 1530 &sm1_mst_e_mclk_div, 1531 &sm1_mst_f_mclk_div, 1532 &sm1_mst_a_mclk, 1533 &sm1_mst_b_mclk, 1534 &sm1_mst_c_mclk, 1535 &sm1_mst_d_mclk, 1536 &sm1_mst_e_mclk, 1537 &sm1_mst_f_mclk, 1538 &spdifout_clk_sel, 1539 &spdifout_clk_div, 1540 &spdifout_clk, 1541 &spdifin_clk_sel, 1542 &spdifin_clk_div, 1543 &spdifin_clk, 1544 &pdm_dclk_sel, 1545 &pdm_dclk_div, 1546 &pdm_dclk, 1547 &pdm_sysclk_sel, 1548 &pdm_sysclk_div, 1549 &pdm_sysclk, 1550 &mst_a_sclk_pre_en, 1551 &mst_b_sclk_pre_en, 1552 &mst_c_sclk_pre_en, 1553 &mst_d_sclk_pre_en, 1554 &mst_e_sclk_pre_en, 1555 &mst_f_sclk_pre_en, 1556 &mst_a_sclk_div, 1557 &mst_b_sclk_div, 1558 &mst_c_sclk_div, 1559 &mst_d_sclk_div, 1560 &mst_e_sclk_div, 1561 &mst_f_sclk_div, 1562 &mst_a_sclk_post_en, 1563 &mst_b_sclk_post_en, 1564 &mst_c_sclk_post_en, 1565 &mst_d_sclk_post_en, 1566 &mst_e_sclk_post_en, 1567 &mst_f_sclk_post_en, 1568 &mst_a_sclk, 1569 &mst_b_sclk, 1570 &mst_c_sclk, 1571 &mst_d_sclk, 1572 &mst_e_sclk, 1573 &mst_f_sclk, 1574 &mst_a_lrclk_div, 1575 &mst_b_lrclk_div, 1576 &mst_c_lrclk_div, 1577 &mst_d_lrclk_div, 1578 &mst_e_lrclk_div, 1579 &mst_f_lrclk_div, 1580 &mst_a_lrclk, 1581 &mst_b_lrclk, 1582 &mst_c_lrclk, 1583 &mst_d_lrclk, 1584 &mst_e_lrclk, 1585 &mst_f_lrclk, 1586 &tdmin_a_sclk_sel, 1587 &tdmin_b_sclk_sel, 1588 &tdmin_c_sclk_sel, 1589 &tdmin_lb_sclk_sel, 1590 &tdmout_a_sclk_sel, 1591 &tdmout_b_sclk_sel, 1592 &tdmout_c_sclk_sel, 1593 &tdmin_a_sclk_pre_en, 1594 &tdmin_b_sclk_pre_en, 1595 &tdmin_c_sclk_pre_en, 1596 &tdmin_lb_sclk_pre_en, 1597 &tdmout_a_sclk_pre_en, 1598 &tdmout_b_sclk_pre_en, 1599 &tdmout_c_sclk_pre_en, 1600 &tdmin_a_sclk_post_en, 1601 &tdmin_b_sclk_post_en, 1602 &tdmin_c_sclk_post_en, 1603 &tdmin_lb_sclk_post_en, 1604 &tdmout_a_sclk_post_en, 1605 &tdmout_b_sclk_post_en, 1606 &tdmout_c_sclk_post_en, 1607 &tdmin_a_sclk, 1608 &tdmin_b_sclk, 1609 &tdmin_c_sclk, 1610 &tdmin_lb_sclk, 1611 &g12a_tdmout_a_sclk, 1612 &g12a_tdmout_b_sclk, 1613 &g12a_tdmout_c_sclk, 1614 &tdmin_a_lrclk, 1615 &tdmin_b_lrclk, 1616 &tdmin_c_lrclk, 1617 &tdmin_lb_lrclk, 1618 &tdmout_a_lrclk, 1619 &tdmout_b_lrclk, 1620 &tdmout_c_lrclk, 1621 &spdifout_b_clk_sel, 1622 &spdifout_b_clk_div, 1623 &spdifout_b_clk, 1624 &sm1_tdm_mclk_pad_0, 1625 &sm1_tdm_mclk_pad_1, 1626 &sm1_tdm_lrclk_pad_0, 1627 &sm1_tdm_lrclk_pad_1, 1628 &sm1_tdm_lrclk_pad_2, 1629 &sm1_tdm_sclk_pad_0, 1630 &sm1_tdm_sclk_pad_1, 1631 &sm1_tdm_sclk_pad_2, 1632 &sm1_aud_top, 1633 &toram, 1634 &eqdrc, 1635 &resample_b, 1636 &tovad, 1637 &locker, 1638 &spdifin_lb, 1639 &frddr_d, 1640 &toddr_d, 1641 &loopback_b, 1642 &sm1_clk81_en, 1643 &sm1_sysclk_a_div, 1644 &sm1_sysclk_a_en, 1645 &sm1_sysclk_b_div, 1646 &sm1_sysclk_b_en, 1647 }; 1648 1649 struct axg_audio_reset_data { 1650 struct reset_controller_dev rstc; 1651 struct regmap *map; 1652 unsigned int offset; 1653 }; 1654 1655 static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst, 1656 unsigned long id, 1657 unsigned int *reg, 1658 unsigned int *bit) 1659 { 1660 unsigned int stride = regmap_get_reg_stride(rst->map); 1661 1662 *reg = (id / (stride * BITS_PER_BYTE)) * stride; 1663 *reg += rst->offset; 1664 *bit = id % (stride * BITS_PER_BYTE); 1665 } 1666 1667 static int axg_audio_reset_update(struct reset_controller_dev *rcdev, 1668 unsigned long id, bool assert) 1669 { 1670 struct axg_audio_reset_data *rst = 1671 container_of(rcdev, struct axg_audio_reset_data, rstc); 1672 unsigned int offset, bit; 1673 1674 axg_audio_reset_reg_and_bit(rst, id, &offset, &bit); 1675 1676 regmap_update_bits(rst->map, offset, BIT(bit), 1677 assert ? BIT(bit) : 0); 1678 1679 return 0; 1680 } 1681 1682 static int axg_audio_reset_status(struct reset_controller_dev *rcdev, 1683 unsigned long id) 1684 { 1685 struct axg_audio_reset_data *rst = 1686 container_of(rcdev, struct axg_audio_reset_data, rstc); 1687 unsigned int val, offset, bit; 1688 1689 axg_audio_reset_reg_and_bit(rst, id, &offset, &bit); 1690 1691 regmap_read(rst->map, offset, &val); 1692 1693 return !!(val & BIT(bit)); 1694 } 1695 1696 static int axg_audio_reset_assert(struct reset_controller_dev *rcdev, 1697 unsigned long id) 1698 { 1699 return axg_audio_reset_update(rcdev, id, true); 1700 } 1701 1702 static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev, 1703 unsigned long id) 1704 { 1705 return axg_audio_reset_update(rcdev, id, false); 1706 } 1707 1708 static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev, 1709 unsigned long id) 1710 { 1711 int ret; 1712 1713 ret = axg_audio_reset_assert(rcdev, id); 1714 if (ret) 1715 return ret; 1716 1717 return axg_audio_reset_deassert(rcdev, id); 1718 } 1719 1720 static const struct reset_control_ops axg_audio_rstc_ops = { 1721 .assert = axg_audio_reset_assert, 1722 .deassert = axg_audio_reset_deassert, 1723 .reset = axg_audio_reset_toggle, 1724 .status = axg_audio_reset_status, 1725 }; 1726 1727 static const struct regmap_config axg_audio_regmap_cfg = { 1728 .reg_bits = 32, 1729 .val_bits = 32, 1730 .reg_stride = 4, 1731 .max_register = AUDIO_CLK_SPDIFOUT_B_CTRL, 1732 }; 1733 1734 struct audioclk_data { 1735 struct clk_regmap *const *regmap_clks; 1736 unsigned int regmap_clk_num; 1737 struct meson_clk_hw_data hw_clks; 1738 unsigned int reset_offset; 1739 unsigned int reset_num; 1740 }; 1741 1742 static int axg_audio_clkc_probe(struct platform_device *pdev) 1743 { 1744 struct device *dev = &pdev->dev; 1745 const struct audioclk_data *data; 1746 struct axg_audio_reset_data *rst; 1747 struct regmap *map; 1748 void __iomem *regs; 1749 struct clk_hw *hw; 1750 struct clk *clk; 1751 int ret, i; 1752 1753 data = of_device_get_match_data(dev); 1754 if (!data) 1755 return -EINVAL; 1756 1757 regs = devm_platform_ioremap_resource(pdev, 0); 1758 if (IS_ERR(regs)) 1759 return PTR_ERR(regs); 1760 1761 map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg); 1762 if (IS_ERR(map)) { 1763 dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map)); 1764 return PTR_ERR(map); 1765 } 1766 1767 /* Get the mandatory peripheral clock */ 1768 clk = devm_clk_get_enabled(dev, "pclk"); 1769 if (IS_ERR(clk)) 1770 return PTR_ERR(clk); 1771 1772 ret = device_reset(dev); 1773 if (ret) { 1774 dev_err_probe(dev, ret, "failed to reset device\n"); 1775 return ret; 1776 } 1777 1778 /* Populate regmap for the regmap backed clocks */ 1779 for (i = 0; i < data->regmap_clk_num; i++) 1780 data->regmap_clks[i]->map = map; 1781 1782 /* Take care to skip the registered input clocks */ 1783 for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) { 1784 const char *name; 1785 1786 hw = data->hw_clks.hws[i]; 1787 /* array might be sparse */ 1788 if (!hw) 1789 continue; 1790 1791 name = hw->init->name; 1792 1793 ret = devm_clk_hw_register(dev, hw); 1794 if (ret) { 1795 dev_err(dev, "failed to register clock %s\n", name); 1796 return ret; 1797 } 1798 } 1799 1800 ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks); 1801 if (ret) 1802 return ret; 1803 1804 /* Stop here if there is no reset */ 1805 if (!data->reset_num) 1806 return 0; 1807 1808 rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL); 1809 if (!rst) 1810 return -ENOMEM; 1811 1812 rst->map = map; 1813 rst->offset = data->reset_offset; 1814 rst->rstc.nr_resets = data->reset_num; 1815 rst->rstc.ops = &axg_audio_rstc_ops; 1816 rst->rstc.of_node = dev->of_node; 1817 rst->rstc.owner = THIS_MODULE; 1818 1819 return devm_reset_controller_register(dev, &rst->rstc); 1820 } 1821 1822 static const struct audioclk_data axg_audioclk_data = { 1823 .regmap_clks = axg_clk_regmaps, 1824 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps), 1825 .hw_clks = { 1826 .hws = axg_audio_hw_clks, 1827 .num = ARRAY_SIZE(axg_audio_hw_clks), 1828 }, 1829 }; 1830 1831 static const struct audioclk_data g12a_audioclk_data = { 1832 .regmap_clks = g12a_clk_regmaps, 1833 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), 1834 .hw_clks = { 1835 .hws = g12a_audio_hw_clks, 1836 .num = ARRAY_SIZE(g12a_audio_hw_clks), 1837 }, 1838 .reset_offset = AUDIO_SW_RESET, 1839 .reset_num = 26, 1840 }; 1841 1842 static const struct audioclk_data sm1_audioclk_data = { 1843 .regmap_clks = sm1_clk_regmaps, 1844 .regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps), 1845 .hw_clks = { 1846 .hws = sm1_audio_hw_clks, 1847 .num = ARRAY_SIZE(sm1_audio_hw_clks), 1848 }, 1849 .reset_offset = AUDIO_SM1_SW_RESET0, 1850 .reset_num = 39, 1851 }; 1852 1853 static const struct of_device_id clkc_match_table[] = { 1854 { 1855 .compatible = "amlogic,axg-audio-clkc", 1856 .data = &axg_audioclk_data 1857 }, { 1858 .compatible = "amlogic,g12a-audio-clkc", 1859 .data = &g12a_audioclk_data 1860 }, { 1861 .compatible = "amlogic,sm1-audio-clkc", 1862 .data = &sm1_audioclk_data 1863 }, {} 1864 }; 1865 MODULE_DEVICE_TABLE(of, clkc_match_table); 1866 1867 static struct platform_driver axg_audio_driver = { 1868 .probe = axg_audio_clkc_probe, 1869 .driver = { 1870 .name = "axg-audio-clkc", 1871 .of_match_table = clkc_match_table, 1872 }, 1873 }; 1874 module_platform_driver(axg_audio_driver); 1875 1876 MODULE_DESCRIPTION("Amlogic AXG/G12A/SM1 Audio Clock driver"); 1877 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 1878 MODULE_LICENSE("GPL v2"); 1879