clk.h (ff70fbd0e81018b45daad5f64ee03ce32d20c917) clk.h (404680794224334bcbea498d571c645e1838c879)
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __MACH_IMX_CLK_H
3#define __MACH_IMX_CLK_H
4
5#include <linux/spinlock.h>
6#include <linux/clk-provider.h>
7
8extern spinlock_t imx_ccm_lock;

--- 7 unchanged lines hidden (view full) ---

16 IMX_PLLV1_IMX1,
17 IMX_PLLV1_IMX21,
18 IMX_PLLV1_IMX25,
19 IMX_PLLV1_IMX27,
20 IMX_PLLV1_IMX31,
21 IMX_PLLV1_IMX35,
22};
23
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __MACH_IMX_CLK_H
3#define __MACH_IMX_CLK_H
4
5#include <linux/spinlock.h>
6#include <linux/clk-provider.h>
7
8extern spinlock_t imx_ccm_lock;

--- 7 unchanged lines hidden (view full) ---

16 IMX_PLLV1_IMX1,
17 IMX_PLLV1_IMX21,
18 IMX_PLLV1_IMX25,
19 IMX_PLLV1_IMX27,
20 IMX_PLLV1_IMX31,
21 IMX_PLLV1_IMX35,
22};
23
24enum imx_sccg_pll_type {
25 SCCG_PLL1,
26 SCCG_PLL2,
27};
28
29struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
30 const char *parent, void __iomem *base);
31
32struct clk *imx_clk_pllv2(const char *name, const char *parent,
33 void __iomem *base);
34
24struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
25 const char *parent, void __iomem *base);
26
27struct clk *imx_clk_pllv2(const char *name, const char *parent,
28 void __iomem *base);
29
35struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
36 void __iomem *base);
37
38struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name,
39 void __iomem *base,
40 enum imx_sccg_pll_type pll_type);
41
42enum imx_pllv3_type {
43 IMX_PLLV3_GENERIC,
44 IMX_PLLV3_SYS,
45 IMX_PLLV3_USB,
46 IMX_PLLV3_USB_VF610,
47 IMX_PLLV3_AV,
48 IMX_PLLV3_ENET,
49 IMX_PLLV3_ENET_IMX7,

--- 73 unchanged lines hidden (view full) ---

123static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
124 void __iomem *reg, u8 shift, u8 width)
125{
126 return clk_register_divider(NULL, name, parent,
127 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
128 reg, shift, width, 0, &imx_ccm_lock);
129}
130
30enum imx_pllv3_type {
31 IMX_PLLV3_GENERIC,
32 IMX_PLLV3_SYS,
33 IMX_PLLV3_USB,
34 IMX_PLLV3_USB_VF610,
35 IMX_PLLV3_AV,
36 IMX_PLLV3_ENET,
37 IMX_PLLV3_ENET_IMX7,

--- 73 unchanged lines hidden (view full) ---

111static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
112 void __iomem *reg, u8 shift, u8 width)
113{
114 return clk_register_divider(NULL, name, parent,
115 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
116 reg, shift, width, 0, &imx_ccm_lock);
117}
118
131static inline struct clk *imx_clk_divider2_flags(const char *name,
132 const char *parent, void __iomem *reg, u8 shift, u8 width,
133 unsigned long flags)
134{
135 return clk_register_divider(NULL, name, parent,
136 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
137 reg, shift, width, 0, &imx_ccm_lock);
138}
139
140static inline struct clk *imx_clk_gate(const char *name, const char *parent,
141 void __iomem *reg, u8 shift)
142{
143 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
144 shift, 0, &imx_ccm_lock);
145}
146
147static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,

--- 58 unchanged lines hidden (view full) ---

206static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
207 void __iomem *reg, u8 shift)
208{
209 return clk_register_gate(NULL, name, parent,
210 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
211 reg, shift, 0, &imx_ccm_lock);
212}
213
119static inline struct clk *imx_clk_gate(const char *name, const char *parent,
120 void __iomem *reg, u8 shift)
121{
122 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
123 shift, 0, &imx_ccm_lock);
124}
125
126static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,

--- 58 unchanged lines hidden (view full) ---

185static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
186 void __iomem *reg, u8 shift)
187{
188 return clk_register_gate(NULL, name, parent,
189 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
190 reg, shift, 0, &imx_ccm_lock);
191}
192
214static inline struct clk *imx_clk_gate3_flags(const char *name,
215 const char *parent, void __iomem *reg, u8 shift,
216 unsigned long flags)
217{
218 return clk_register_gate(NULL, name, parent,
219 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
220 reg, shift, 0, &imx_ccm_lock);
221}
222
223static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
224 void __iomem *reg, u8 shift)
225{
226 return clk_register_gate2(NULL, name, parent,
227 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
228 reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
229}
230
193static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
194 void __iomem *reg, u8 shift)
195{
196 return clk_register_gate2(NULL, name, parent,
197 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
198 reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
199}
200
231static inline struct clk *imx_clk_gate4_flags(const char *name,
232 const char *parent, void __iomem *reg, u8 shift,
233 unsigned long flags)
234{
235 return clk_register_gate2(NULL, name, parent,
236 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
237 reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
238}
239
240static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
241 u8 shift, u8 width, const char **parents, int num_parents)
242{
243 return clk_register_mux(NULL, name, parents, num_parents,
244 CLK_SET_RATE_NO_REPARENT, reg, shift,
245 width, 0, &imx_ccm_lock);
246}
247

--- 9 unchanged lines hidden (view full) ---

257 void __iomem *reg, u8 shift, u8 width, const char **parents,
258 int num_parents, unsigned long flags)
259{
260 return clk_register_mux(NULL, name, parents, num_parents,
261 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
262 &imx_ccm_lock);
263}
264
201static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
202 u8 shift, u8 width, const char **parents, int num_parents)
203{
204 return clk_register_mux(NULL, name, parents, num_parents,
205 CLK_SET_RATE_NO_REPARENT, reg, shift,
206 width, 0, &imx_ccm_lock);
207}
208

--- 9 unchanged lines hidden (view full) ---

218 void __iomem *reg, u8 shift, u8 width, const char **parents,
219 int num_parents, unsigned long flags)
220{
221 return clk_register_mux(NULL, name, parents, num_parents,
222 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
223 &imx_ccm_lock);
224}
225
265static inline struct clk *imx_clk_mux2_flags(const char *name,
266 void __iomem *reg, u8 shift, u8 width, const char **parents,
267 int num_parents, unsigned long flags)
268{
269 return clk_register_mux(NULL, name, parents, num_parents,
270 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
271 reg, shift, width, 0, &imx_ccm_lock);
272}
273
274struct clk *imx_clk_cpu(const char *name, const char *parent_name,
275 struct clk *div, struct clk *mux, struct clk *pll,
276 struct clk *step);
277
226struct clk *imx_clk_cpu(const char *name, const char *parent_name,
227 struct clk *div, struct clk *mux, struct clk *pll,
228 struct clk *step);
229
278struct clk *imx8m_clk_composite_flags(const char *name,
279 const char **parent_names,
280 int num_parents, void __iomem *reg,
281 unsigned long flags);
282
283#define __imx8m_clk_composite(name, parent_names, reg, flags) \
284 imx8m_clk_composite_flags(name, parent_names, \
285 ARRAY_SIZE(parent_names), reg, \
286 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
287
288#define imx8m_clk_composite(name, parent_names, reg) \
289 __imx8m_clk_composite(name, parent_names, reg, 0)
290
291#define imx8m_clk_composite_critical(name, parent_names, reg) \
292 __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
293
230struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name,
231 unsigned long flags, void __iomem *reg, u8 shift, u8 width,
232 u8 clk_divider_flags, const struct clk_div_table *table,
233 spinlock_t *lock);
294#endif
234#endif