1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __MACH_IMX_CLK_H 3 #define __MACH_IMX_CLK_H 4 5 #include <linux/spinlock.h> 6 #include <linux/clk-provider.h> 7 8 extern spinlock_t imx_ccm_lock; 9 10 void imx_check_clocks(struct clk *clks[], unsigned int count); 11 void imx_register_uart_clocks(struct clk ** const clks[]); 12 13 extern void imx_cscmr1_fixup(u32 *val); 14 15 enum imx_pllv1_type { 16 IMX_PLLV1_IMX1, 17 IMX_PLLV1_IMX21, 18 IMX_PLLV1_IMX25, 19 IMX_PLLV1_IMX27, 20 IMX_PLLV1_IMX31, 21 IMX_PLLV1_IMX35, 22 }; 23 24 enum imx_sccg_pll_type { 25 SCCG_PLL1, 26 SCCG_PLL2, 27 }; 28 29 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, 30 const char *parent, void __iomem *base); 31 32 struct clk *imx_clk_pllv2(const char *name, const char *parent, 33 void __iomem *base); 34 35 struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, 36 void __iomem *base); 37 38 struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name, 39 void __iomem *base, 40 enum imx_sccg_pll_type pll_type); 41 42 enum imx_pllv3_type { 43 IMX_PLLV3_GENERIC, 44 IMX_PLLV3_SYS, 45 IMX_PLLV3_USB, 46 IMX_PLLV3_USB_VF610, 47 IMX_PLLV3_AV, 48 IMX_PLLV3_ENET, 49 IMX_PLLV3_ENET_IMX7, 50 IMX_PLLV3_SYS_VF610, 51 IMX_PLLV3_DDR_IMX7, 52 }; 53 54 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 55 const char *parent_name, void __iomem *base, u32 div_mask); 56 57 struct clk *clk_register_gate2(struct device *dev, const char *name, 58 const char *parent_name, unsigned long flags, 59 void __iomem *reg, u8 bit_idx, u8 cgr_val, 60 u8 clk_gate_flags, spinlock_t *lock, 61 unsigned int *share_count); 62 63 struct clk * imx_obtain_fixed_clock( 64 const char *name, unsigned long rate); 65 66 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, 67 void __iomem *reg, u8 shift, u32 exclusive_mask); 68 69 struct clk *imx_clk_pfd(const char *name, const char *parent_name, 70 void __iomem *reg, u8 idx); 71 72 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, 73 void __iomem *reg, u8 shift, u8 width, 74 void __iomem *busy_reg, u8 busy_shift); 75 76 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, 77 u8 width, void __iomem *busy_reg, u8 busy_shift, 78 const char **parent_names, int num_parents); 79 80 struct clk *imx_clk_fixup_divider(const char *name, const char *parent, 81 void __iomem *reg, u8 shift, u8 width, 82 void (*fixup)(u32 *val)); 83 84 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, 85 u8 shift, u8 width, const char **parents, 86 int num_parents, void (*fixup)(u32 *val)); 87 88 static inline struct clk *imx_clk_fixed(const char *name, int rate) 89 { 90 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 91 } 92 93 static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, 94 u8 shift, u8 width, const char **parents, int num_parents) 95 { 96 return clk_register_mux(NULL, name, parents, num_parents, 97 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, 98 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); 99 } 100 101 static inline struct clk *imx_clk_fixed_factor(const char *name, 102 const char *parent, unsigned int mult, unsigned int div) 103 { 104 return clk_register_fixed_factor(NULL, name, parent, 105 CLK_SET_RATE_PARENT, mult, div); 106 } 107 108 static inline struct clk *imx_clk_divider(const char *name, const char *parent, 109 void __iomem *reg, u8 shift, u8 width) 110 { 111 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, 112 reg, shift, width, 0, &imx_ccm_lock); 113 } 114 115 static inline struct clk *imx_clk_divider_flags(const char *name, 116 const char *parent, void __iomem *reg, u8 shift, u8 width, 117 unsigned long flags) 118 { 119 return clk_register_divider(NULL, name, parent, flags, 120 reg, shift, width, 0, &imx_ccm_lock); 121 } 122 123 static inline struct clk *imx_clk_divider2(const char *name, const char *parent, 124 void __iomem *reg, u8 shift, u8 width) 125 { 126 return clk_register_divider(NULL, name, parent, 127 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 128 reg, shift, width, 0, &imx_ccm_lock); 129 } 130 131 static inline struct clk *imx_clk_divider2_flags(const char *name, 132 const char *parent, void __iomem *reg, u8 shift, u8 width, 133 unsigned long flags) 134 { 135 return clk_register_divider(NULL, name, parent, 136 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 137 reg, shift, width, 0, &imx_ccm_lock); 138 } 139 140 static inline struct clk *imx_clk_gate(const char *name, const char *parent, 141 void __iomem *reg, u8 shift) 142 { 143 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 144 shift, 0, &imx_ccm_lock); 145 } 146 147 static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent, 148 void __iomem *reg, u8 shift, unsigned long flags) 149 { 150 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 151 shift, 0, &imx_ccm_lock); 152 } 153 154 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, 155 void __iomem *reg, u8 shift) 156 { 157 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 158 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 159 } 160 161 static inline struct clk *imx_clk_gate_dis_flags(const char *name, const char *parent, 162 void __iomem *reg, u8 shift, unsigned long flags) 163 { 164 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 165 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 166 } 167 168 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, 169 void __iomem *reg, u8 shift) 170 { 171 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 172 shift, 0x3, 0, &imx_ccm_lock, NULL); 173 } 174 175 static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent, 176 void __iomem *reg, u8 shift, unsigned long flags) 177 { 178 return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 179 shift, 0x3, 0, &imx_ccm_lock, NULL); 180 } 181 182 static inline struct clk *imx_clk_gate2_shared(const char *name, 183 const char *parent, void __iomem *reg, u8 shift, 184 unsigned int *share_count) 185 { 186 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 187 shift, 0x3, 0, &imx_ccm_lock, share_count); 188 } 189 190 static inline struct clk *imx_clk_gate2_shared2(const char *name, 191 const char *parent, void __iomem *reg, u8 shift, 192 unsigned int *share_count) 193 { 194 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | 195 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, 196 &imx_ccm_lock, share_count); 197 } 198 199 static inline struct clk *imx_clk_gate2_cgr(const char *name, 200 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) 201 { 202 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 203 shift, cgr_val, 0, &imx_ccm_lock, NULL); 204 } 205 206 static inline struct clk *imx_clk_gate3(const char *name, const char *parent, 207 void __iomem *reg, u8 shift) 208 { 209 return clk_register_gate(NULL, name, parent, 210 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 211 reg, shift, 0, &imx_ccm_lock); 212 } 213 214 static inline struct clk *imx_clk_gate3_flags(const char *name, 215 const char *parent, void __iomem *reg, u8 shift, 216 unsigned long flags) 217 { 218 return clk_register_gate(NULL, name, parent, 219 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 220 reg, shift, 0, &imx_ccm_lock); 221 } 222 223 static inline struct clk *imx_clk_gate4(const char *name, const char *parent, 224 void __iomem *reg, u8 shift) 225 { 226 return clk_register_gate2(NULL, name, parent, 227 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 228 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); 229 } 230 231 static inline struct clk *imx_clk_gate4_flags(const char *name, 232 const char *parent, void __iomem *reg, u8 shift, 233 unsigned long flags) 234 { 235 return clk_register_gate2(NULL, name, parent, 236 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 237 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); 238 } 239 240 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, 241 u8 shift, u8 width, const char **parents, int num_parents) 242 { 243 return clk_register_mux(NULL, name, parents, num_parents, 244 CLK_SET_RATE_NO_REPARENT, reg, shift, 245 width, 0, &imx_ccm_lock); 246 } 247 248 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, 249 u8 shift, u8 width, const char **parents, int num_parents) 250 { 251 return clk_register_mux(NULL, name, parents, num_parents, 252 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 253 reg, shift, width, 0, &imx_ccm_lock); 254 } 255 256 static inline struct clk *imx_clk_mux_flags(const char *name, 257 void __iomem *reg, u8 shift, u8 width, const char **parents, 258 int num_parents, unsigned long flags) 259 { 260 return clk_register_mux(NULL, name, parents, num_parents, 261 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, 262 &imx_ccm_lock); 263 } 264 265 static inline struct clk *imx_clk_mux2_flags(const char *name, 266 void __iomem *reg, u8 shift, u8 width, const char **parents, 267 int num_parents, unsigned long flags) 268 { 269 return clk_register_mux(NULL, name, parents, num_parents, 270 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 271 reg, shift, width, 0, &imx_ccm_lock); 272 } 273 274 struct clk *imx_clk_cpu(const char *name, const char *parent_name, 275 struct clk *div, struct clk *mux, struct clk *pll, 276 struct clk *step); 277 278 struct clk *imx8m_clk_composite_flags(const char *name, 279 const char **parent_names, 280 int num_parents, void __iomem *reg, 281 unsigned long flags); 282 283 #define __imx8m_clk_composite(name, parent_names, reg, flags) \ 284 imx8m_clk_composite_flags(name, parent_names, \ 285 ARRAY_SIZE(parent_names), reg, \ 286 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 287 288 #define imx8m_clk_composite(name, parent_names, reg) \ 289 __imx8m_clk_composite(name, parent_names, reg, 0) 290 291 #define imx8m_clk_composite_critical(name, parent_names, reg) \ 292 __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) 293 294 #endif 295