ivpu_mmu.c (e013aa9ab01b400cccc6c3e8b969b8e7f10bc6cb) ivpu_mmu.c (0c287c27fbffa2737f155af73646a794e540e1d3)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6#include <linux/circ_buf.h>
7#include <linux/highmem.h>
8

--- 486 unchanged lines hidden (view full) ---

495}
496
497static int ivpu_mmu_cmdq_sync(struct ivpu_device *vdev)
498{
499 struct ivpu_mmu_queue *q = &vdev->mmu->cmdq;
500 u64 val;
501 int ret;
502
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2020-2023 Intel Corporation
4 */
5
6#include <linux/circ_buf.h>
7#include <linux/highmem.h>
8

--- 486 unchanged lines hidden (view full) ---

495}
496
497static int ivpu_mmu_cmdq_sync(struct ivpu_device *vdev)
498{
499 struct ivpu_mmu_queue *q = &vdev->mmu->cmdq;
500 u64 val;
501 int ret;
502
503 val = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_SYNC) |
504 FIELD_PREP(IVPU_MMU_CMD_SYNC_0_CS, 0x2) |
505 FIELD_PREP(IVPU_MMU_CMD_SYNC_0_MSH, 0x3) |
506 FIELD_PREP(IVPU_MMU_CMD_SYNC_0_MSI_ATTR, 0xf);
503 val = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_SYNC);
507
508 ret = ivpu_mmu_cmdq_cmd_write(vdev, "SYNC", val, 0);
509 if (ret)
510 return ret;
511
512 clflush_cache_range(q->base, IVPU_MMU_CMDQ_SIZE);
513 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod);
514

--- 439 unchanged lines hidden --- 		504
505 ret = ivpu_mmu_cmdq_cmd_write(vdev, "SYNC", val, 0);
506 if (ret)
507 return ret;
508
509 clflush_cache_range(q->base, IVPU_MMU_CMDQ_SIZE);
510 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod);
511

--- 439 unchanged lines hidden ---