1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2023 Intel Corporation 4 */ 5 6 #include <linux/circ_buf.h> 7 #include <linux/highmem.h> 8 9 #include "ivpu_drv.h" 10 #include "ivpu_hw_reg_io.h" 11 #include "ivpu_mmu.h" 12 #include "ivpu_mmu_context.h" 13 #include "ivpu_pm.h" 14 15 #define IVPU_MMU_REG_IDR0 0x00200000u 16 #define IVPU_MMU_REG_IDR1 0x00200004u 17 #define IVPU_MMU_REG_IDR3 0x0020000cu 18 #define IVPU_MMU_REG_IDR5 0x00200014u 19 #define IVPU_MMU_REG_CR0 0x00200020u 20 #define IVPU_MMU_REG_CR0ACK 0x00200024u 21 #define IVPU_MMU_REG_CR0ACK_VAL_MASK GENMASK(31, 0) 22 #define IVPU_MMU_REG_CR1 0x00200028u 23 #define IVPU_MMU_REG_CR2 0x0020002cu 24 #define IVPU_MMU_REG_IRQ_CTRL 0x00200050u 25 #define IVPU_MMU_REG_IRQ_CTRLACK 0x00200054u 26 #define IVPU_MMU_REG_IRQ_CTRLACK_VAL_MASK GENMASK(31, 0) 27 28 #define IVPU_MMU_REG_GERROR 0x00200060u 29 #define IVPU_MMU_REG_GERROR_CMDQ_MASK BIT_MASK(0) 30 #define IVPU_MMU_REG_GERROR_EVTQ_ABT_MASK BIT_MASK(2) 31 #define IVPU_MMU_REG_GERROR_PRIQ_ABT_MASK BIT_MASK(3) 32 #define IVPU_MMU_REG_GERROR_MSI_CMDQ_ABT_MASK BIT_MASK(4) 33 #define IVPU_MMU_REG_GERROR_MSI_EVTQ_ABT_MASK BIT_MASK(5) 34 #define IVPU_MMU_REG_GERROR_MSI_PRIQ_ABT_MASK BIT_MASK(6) 35 #define IVPU_MMU_REG_GERROR_MSI_ABT_MASK BIT_MASK(7) 36 37 #define IVPU_MMU_REG_GERRORN 0x00200064u 38 39 #define IVPU_MMU_REG_STRTAB_BASE 0x00200080u 40 #define IVPU_MMU_REG_STRTAB_BASE_CFG 0x00200088u 41 #define IVPU_MMU_REG_CMDQ_BASE 0x00200090u 42 #define IVPU_MMU_REG_CMDQ_PROD 0x00200098u 43 #define IVPU_MMU_REG_CMDQ_CONS 0x0020009cu 44 #define IVPU_MMU_REG_CMDQ_CONS_VAL_MASK GENMASK(23, 0) 45 #define IVPU_MMU_REG_CMDQ_CONS_ERR_MASK GENMASK(30, 24) 46 #define IVPU_MMU_REG_EVTQ_BASE 0x002000a0u 47 #define IVPU_MMU_REG_EVTQ_PROD 0x002000a8u 48 #define IVPU_MMU_REG_EVTQ_CONS 0x002000acu 49 #define IVPU_MMU_REG_EVTQ_PROD_SEC (0x002000a8u + SZ_64K) 50 #define IVPU_MMU_REG_EVTQ_CONS_SEC (0x002000acu + SZ_64K) 51 52 #define IVPU_MMU_IDR0_REF 0x080f3e0f 53 #define IVPU_MMU_IDR0_REF_SIMICS 0x080f3e1f 54 #define IVPU_MMU_IDR1_REF 0x0e739d18 55 #define IVPU_MMU_IDR3_REF 0x0000003c 56 #define IVPU_MMU_IDR5_REF 0x00040070 57 #define IVPU_MMU_IDR5_REF_SIMICS 0x00000075 58 #define IVPU_MMU_IDR5_REF_FPGA 0x00800075 59 60 #define IVPU_MMU_CDTAB_ENT_SIZE 64 61 #define IVPU_MMU_CDTAB_ENT_COUNT_LOG2 8 /* 256 entries */ 62 #define IVPU_MMU_CDTAB_ENT_COUNT ((u32)1 << IVPU_MMU_CDTAB_ENT_COUNT_LOG2) 63 64 #define IVPU_MMU_STREAM_ID0 0 65 #define IVPU_MMU_STREAM_ID3 3 66 67 #define IVPU_MMU_STRTAB_ENT_SIZE 64 68 #define IVPU_MMU_STRTAB_ENT_COUNT 4 69 #define IVPU_MMU_STRTAB_CFG_LOG2SIZE 2 70 #define IVPU_MMU_STRTAB_CFG IVPU_MMU_STRTAB_CFG_LOG2SIZE 71 72 #define IVPU_MMU_Q_COUNT_LOG2 4 /* 16 entries */ 73 #define IVPU_MMU_Q_COUNT ((u32)1 << IVPU_MMU_Q_COUNT_LOG2) 74 #define IVPU_MMU_Q_WRAP_BIT (IVPU_MMU_Q_COUNT << 1) 75 #define IVPU_MMU_Q_WRAP_MASK (IVPU_MMU_Q_WRAP_BIT - 1) 76 #define IVPU_MMU_Q_IDX_MASK (IVPU_MMU_Q_COUNT - 1) 77 #define IVPU_MMU_Q_IDX(val) ((val) & IVPU_MMU_Q_IDX_MASK) 78 79 #define IVPU_MMU_CMDQ_CMD_SIZE 16 80 #define IVPU_MMU_CMDQ_SIZE (IVPU_MMU_Q_COUNT * IVPU_MMU_CMDQ_CMD_SIZE) 81 82 #define IVPU_MMU_EVTQ_CMD_SIZE 32 83 #define IVPU_MMU_EVTQ_SIZE (IVPU_MMU_Q_COUNT * IVPU_MMU_EVTQ_CMD_SIZE) 84 85 #define IVPU_MMU_CMD_OPCODE GENMASK(7, 0) 86 87 #define IVPU_MMU_CMD_SYNC_0_CS GENMASK(13, 12) 88 #define IVPU_MMU_CMD_SYNC_0_MSH GENMASK(23, 22) 89 #define IVPU_MMU_CMD_SYNC_0_MSI_ATTR GENMASK(27, 24) 90 #define IVPU_MMU_CMD_SYNC_0_MSI_ATTR GENMASK(27, 24) 91 #define IVPU_MMU_CMD_SYNC_0_MSI_DATA GENMASK(63, 32) 92 93 #define IVPU_MMU_CMD_CFGI_0_SSEC BIT(10) 94 #define IVPU_MMU_CMD_CFGI_0_SSV BIT(11) 95 #define IVPU_MMU_CMD_CFGI_0_SSID GENMASK(31, 12) 96 #define IVPU_MMU_CMD_CFGI_0_SID GENMASK(63, 32) 97 #define IVPU_MMU_CMD_CFGI_1_RANGE GENMASK(4, 0) 98 99 #define IVPU_MMU_CMD_TLBI_0_ASID GENMASK(63, 48) 100 #define IVPU_MMU_CMD_TLBI_0_VMID GENMASK(47, 32) 101 102 #define CMD_PREFETCH_CFG 0x1 103 #define CMD_CFGI_STE 0x3 104 #define CMD_CFGI_ALL 0x4 105 #define CMD_CFGI_CD 0x5 106 #define CMD_CFGI_CD_ALL 0x6 107 #define CMD_TLBI_NH_ASID 0x11 108 #define CMD_TLBI_EL2_ALL 0x20 109 #define CMD_TLBI_NSNH_ALL 0x30 110 #define CMD_SYNC 0x46 111 112 #define IVPU_MMU_EVT_F_UUT 0x01 113 #define IVPU_MMU_EVT_C_BAD_STREAMID 0x02 114 #define IVPU_MMU_EVT_F_STE_FETCH 0x03 115 #define IVPU_MMU_EVT_C_BAD_STE 0x04 116 #define IVPU_MMU_EVT_F_BAD_ATS_TREQ 0x05 117 #define IVPU_MMU_EVT_F_STREAM_DISABLED 0x06 118 #define IVPU_MMU_EVT_F_TRANSL_FORBIDDEN 0x07 119 #define IVPU_MMU_EVT_C_BAD_SUBSTREAMID 0x08 120 #define IVPU_MMU_EVT_F_CD_FETCH 0x09 121 #define IVPU_MMU_EVT_C_BAD_CD 0x0a 122 #define IVPU_MMU_EVT_F_WALK_EABT 0x0b 123 #define IVPU_MMU_EVT_F_TRANSLATION 0x10 124 #define IVPU_MMU_EVT_F_ADDR_SIZE 0x11 125 #define IVPU_MMU_EVT_F_ACCESS 0x12 126 #define IVPU_MMU_EVT_F_PERMISSION 0x13 127 #define IVPU_MMU_EVT_F_TLB_CONFLICT 0x20 128 #define IVPU_MMU_EVT_F_CFG_CONFLICT 0x21 129 #define IVPU_MMU_EVT_E_PAGE_REQUEST 0x24 130 #define IVPU_MMU_EVT_F_VMS_FETCH 0x25 131 132 #define IVPU_MMU_EVT_OP_MASK GENMASK_ULL(7, 0) 133 #define IVPU_MMU_EVT_SSID_MASK GENMASK_ULL(31, 12) 134 135 #define IVPU_MMU_Q_BASE_RWA BIT(62) 136 #define IVPU_MMU_Q_BASE_ADDR_MASK GENMASK_ULL(51, 5) 137 #define IVPU_MMU_STRTAB_BASE_RA BIT(62) 138 #define IVPU_MMU_STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6) 139 140 #define IVPU_MMU_IRQ_EVTQ_EN BIT(2) 141 #define IVPU_MMU_IRQ_GERROR_EN BIT(0) 142 143 #define IVPU_MMU_CR0_ATSCHK BIT(4) 144 #define IVPU_MMU_CR0_CMDQEN BIT(3) 145 #define IVPU_MMU_CR0_EVTQEN BIT(2) 146 #define IVPU_MMU_CR0_PRIQEN BIT(1) 147 #define IVPU_MMU_CR0_SMMUEN BIT(0) 148 149 #define IVPU_MMU_CR1_TABLE_SH GENMASK(11, 10) 150 #define IVPU_MMU_CR1_TABLE_OC GENMASK(9, 8) 151 #define IVPU_MMU_CR1_TABLE_IC GENMASK(7, 6) 152 #define IVPU_MMU_CR1_QUEUE_SH GENMASK(5, 4) 153 #define IVPU_MMU_CR1_QUEUE_OC GENMASK(3, 2) 154 #define IVPU_MMU_CR1_QUEUE_IC GENMASK(1, 0) 155 #define IVPU_MMU_CACHE_NC 0 156 #define IVPU_MMU_CACHE_WB 1 157 #define IVPU_MMU_CACHE_WT 2 158 #define IVPU_MMU_SH_NSH 0 159 #define IVPU_MMU_SH_OSH 2 160 #define IVPU_MMU_SH_ISH 3 161 162 #define IVPU_MMU_CMDQ_OP GENMASK_ULL(7, 0) 163 164 #define IVPU_MMU_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) 165 #define IVPU_MMU_CD_0_TCR_TG0 GENMASK_ULL(7, 6) 166 #define IVPU_MMU_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) 167 #define IVPU_MMU_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10) 168 #define IVPU_MMU_CD_0_TCR_SH0 GENMASK_ULL(13, 12) 169 #define IVPU_MMU_CD_0_TCR_EPD0 BIT_ULL(14) 170 #define IVPU_MMU_CD_0_TCR_EPD1 BIT_ULL(30) 171 #define IVPU_MMU_CD_0_ENDI BIT(15) 172 #define IVPU_MMU_CD_0_V BIT(31) 173 #define IVPU_MMU_CD_0_TCR_IPS GENMASK_ULL(34, 32) 174 #define IVPU_MMU_CD_0_TCR_TBI0 BIT_ULL(38) 175 #define IVPU_MMU_CD_0_AA64 BIT(41) 176 #define IVPU_MMU_CD_0_S BIT(44) 177 #define IVPU_MMU_CD_0_R BIT(45) 178 #define IVPU_MMU_CD_0_A BIT(46) 179 #define IVPU_MMU_CD_0_ASET BIT(47) 180 #define IVPU_MMU_CD_0_ASID GENMASK_ULL(63, 48) 181 182 #define IVPU_MMU_T0SZ_48BIT 16 183 #define IVPU_MMU_T0SZ_38BIT 26 184 185 #define IVPU_MMU_IPS_48BIT 5 186 #define IVPU_MMU_IPS_44BIT 4 187 #define IVPU_MMU_IPS_42BIT 3 188 #define IVPU_MMU_IPS_40BIT 2 189 #define IVPU_MMU_IPS_36BIT 1 190 #define IVPU_MMU_IPS_32BIT 0 191 192 #define IVPU_MMU_CD_1_TTB0_MASK GENMASK_ULL(51, 4) 193 194 #define IVPU_MMU_STE_0_S1CDMAX GENMASK_ULL(63, 59) 195 #define IVPU_MMU_STE_0_S1FMT GENMASK_ULL(5, 4) 196 #define IVPU_MMU_STE_0_S1FMT_LINEAR 0 197 #define IVPU_MMU_STE_DWORDS 8 198 #define IVPU_MMU_STE_0_CFG_S1_TRANS 5 199 #define IVPU_MMU_STE_0_CFG GENMASK_ULL(3, 1) 200 #define IVPU_MMU_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6) 201 #define IVPU_MMU_STE_0_V BIT(0) 202 203 #define IVPU_MMU_STE_1_STRW_NSEL1 0ul 204 #define IVPU_MMU_STE_1_CONT GENMASK_ULL(16, 13) 205 #define IVPU_MMU_STE_1_STRW GENMASK_ULL(31, 30) 206 #define IVPU_MMU_STE_1_PRIVCFG GENMASK_ULL(49, 48) 207 #define IVPU_MMU_STE_1_PRIVCFG_UNPRIV 2ul 208 #define IVPU_MMU_STE_1_INSTCFG GENMASK_ULL(51, 50) 209 #define IVPU_MMU_STE_1_INSTCFG_DATA 2ul 210 #define IVPU_MMU_STE_1_MEV BIT(19) 211 #define IVPU_MMU_STE_1_S1STALLD BIT(27) 212 #define IVPU_MMU_STE_1_S1C_CACHE_NC 0ul 213 #define IVPU_MMU_STE_1_S1C_CACHE_WBRA 1ul 214 #define IVPU_MMU_STE_1_S1C_CACHE_WT 2ul 215 #define IVPU_MMU_STE_1_S1C_CACHE_WB 3ul 216 #define IVPU_MMU_STE_1_S1CIR GENMASK_ULL(3, 2) 217 #define IVPU_MMU_STE_1_S1COR GENMASK_ULL(5, 4) 218 #define IVPU_MMU_STE_1_S1CSH GENMASK_ULL(7, 6) 219 #define IVPU_MMU_STE_1_S1DSS GENMASK_ULL(1, 0) 220 #define IVPU_MMU_STE_1_S1DSS_TERMINATE 0x0 221 222 #define IVPU_MMU_REG_TIMEOUT_US (10 * USEC_PER_MSEC) 223 #define IVPU_MMU_QUEUE_TIMEOUT_US (100 * USEC_PER_MSEC) 224 225 #define IVPU_MMU_GERROR_ERR_MASK ((REG_FLD(IVPU_MMU_REG_GERROR, CMDQ)) | \ 226 (REG_FLD(IVPU_MMU_REG_GERROR, EVTQ_ABT)) | \ 227 (REG_FLD(IVPU_MMU_REG_GERROR, PRIQ_ABT)) | \ 228 (REG_FLD(IVPU_MMU_REG_GERROR, MSI_CMDQ_ABT)) | \ 229 (REG_FLD(IVPU_MMU_REG_GERROR, MSI_EVTQ_ABT)) | \ 230 (REG_FLD(IVPU_MMU_REG_GERROR, MSI_PRIQ_ABT)) | \ 231 (REG_FLD(IVPU_MMU_REG_GERROR, MSI_ABT))) 232 233 #define IVPU_MMU_CERROR_NONE 0x0 234 #define IVPU_MMU_CERROR_ILL 0x1 235 #define IVPU_MMU_CERROR_ABT 0x2 236 #define IVPU_MMU_CERROR_ATC_INV_SYNC 0x3 237 238 static const char *ivpu_mmu_event_to_str(u32 cmd) 239 { 240 switch (cmd) { 241 case IVPU_MMU_EVT_F_UUT: 242 return "Unsupported Upstream Transaction"; 243 case IVPU_MMU_EVT_C_BAD_STREAMID: 244 return "Transaction StreamID out of range"; 245 case IVPU_MMU_EVT_F_STE_FETCH: 246 return "Fetch of STE caused external abort"; 247 case IVPU_MMU_EVT_C_BAD_STE: 248 return "Used STE invalid"; 249 case IVPU_MMU_EVT_F_BAD_ATS_TREQ: 250 return "Address Request disallowed for a StreamID"; 251 case IVPU_MMU_EVT_F_STREAM_DISABLED: 252 return "Transaction marks non-substream disabled"; 253 case IVPU_MMU_EVT_F_TRANSL_FORBIDDEN: 254 return "MMU bypass is disallowed for this StreamID"; 255 case IVPU_MMU_EVT_C_BAD_SUBSTREAMID: 256 return "Invalid StreamID"; 257 case IVPU_MMU_EVT_F_CD_FETCH: 258 return "Fetch of CD caused external abort"; 259 case IVPU_MMU_EVT_C_BAD_CD: 260 return "Fetched CD invalid"; 261 case IVPU_MMU_EVT_F_WALK_EABT: 262 return " An external abort occurred fetching a TLB"; 263 case IVPU_MMU_EVT_F_TRANSLATION: 264 return "Translation fault"; 265 case IVPU_MMU_EVT_F_ADDR_SIZE: 266 return " Output address caused address size fault"; 267 case IVPU_MMU_EVT_F_ACCESS: 268 return "Access flag fault"; 269 case IVPU_MMU_EVT_F_PERMISSION: 270 return "Permission fault occurred on page access"; 271 case IVPU_MMU_EVT_F_TLB_CONFLICT: 272 return "A TLB conflict"; 273 case IVPU_MMU_EVT_F_CFG_CONFLICT: 274 return "A configuration cache conflict"; 275 case IVPU_MMU_EVT_E_PAGE_REQUEST: 276 return "Page request hint from a client device"; 277 case IVPU_MMU_EVT_F_VMS_FETCH: 278 return "Fetch of VMS caused external abort"; 279 default: 280 return "Unknown CMDQ command"; 281 } 282 } 283 284 static const char *ivpu_mmu_cmdq_err_to_str(u32 err) 285 { 286 switch (err) { 287 case IVPU_MMU_CERROR_NONE: 288 return "No CMDQ Error"; 289 case IVPU_MMU_CERROR_ILL: 290 return "Illegal command"; 291 case IVPU_MMU_CERROR_ABT: 292 return "External abort on CMDQ read"; 293 case IVPU_MMU_CERROR_ATC_INV_SYNC: 294 return "Sync failed to complete ATS invalidation"; 295 default: 296 return "Unknown CMDQ Error"; 297 } 298 } 299 300 static void ivpu_mmu_config_check(struct ivpu_device *vdev) 301 { 302 u32 val_ref; 303 u32 val; 304 305 if (ivpu_is_simics(vdev)) 306 val_ref = IVPU_MMU_IDR0_REF_SIMICS; 307 else 308 val_ref = IVPU_MMU_IDR0_REF; 309 310 val = REGV_RD32(IVPU_MMU_REG_IDR0); 311 if (val != val_ref) 312 ivpu_dbg(vdev, MMU, "IDR0 0x%x != IDR0_REF 0x%x\n", val, val_ref); 313 314 val = REGV_RD32(IVPU_MMU_REG_IDR1); 315 if (val != IVPU_MMU_IDR1_REF) 316 ivpu_dbg(vdev, MMU, "IDR1 0x%x != IDR1_REF 0x%x\n", val, IVPU_MMU_IDR1_REF); 317 318 val = REGV_RD32(IVPU_MMU_REG_IDR3); 319 if (val != IVPU_MMU_IDR3_REF) 320 ivpu_dbg(vdev, MMU, "IDR3 0x%x != IDR3_REF 0x%x\n", val, IVPU_MMU_IDR3_REF); 321 322 if (ivpu_is_simics(vdev)) 323 val_ref = IVPU_MMU_IDR5_REF_SIMICS; 324 else if (ivpu_is_fpga(vdev)) 325 val_ref = IVPU_MMU_IDR5_REF_FPGA; 326 else 327 val_ref = IVPU_MMU_IDR5_REF; 328 329 val = REGV_RD32(IVPU_MMU_REG_IDR5); 330 if (val != val_ref) 331 ivpu_dbg(vdev, MMU, "IDR5 0x%x != IDR5_REF 0x%x\n", val, val_ref); 332 } 333 334 static int ivpu_mmu_cdtab_alloc(struct ivpu_device *vdev) 335 { 336 struct ivpu_mmu_info *mmu = vdev->mmu; 337 struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab; 338 size_t size = IVPU_MMU_CDTAB_ENT_COUNT * IVPU_MMU_CDTAB_ENT_SIZE; 339 340 cdtab->base = dmam_alloc_coherent(vdev->drm.dev, size, &cdtab->dma, GFP_KERNEL); 341 if (!cdtab->base) 342 return -ENOMEM; 343 344 ivpu_dbg(vdev, MMU, "CDTAB alloc: dma=%pad size=%zu\n", &cdtab->dma, size); 345 346 return 0; 347 } 348 349 static int ivpu_mmu_strtab_alloc(struct ivpu_device *vdev) 350 { 351 struct ivpu_mmu_info *mmu = vdev->mmu; 352 struct ivpu_mmu_strtab *strtab = &mmu->strtab; 353 size_t size = IVPU_MMU_STRTAB_ENT_COUNT * IVPU_MMU_STRTAB_ENT_SIZE; 354 355 strtab->base = dmam_alloc_coherent(vdev->drm.dev, size, &strtab->dma, GFP_KERNEL); 356 if (!strtab->base) 357 return -ENOMEM; 358 359 strtab->base_cfg = IVPU_MMU_STRTAB_CFG; 360 strtab->dma_q = IVPU_MMU_STRTAB_BASE_RA; 361 strtab->dma_q |= strtab->dma & IVPU_MMU_STRTAB_BASE_ADDR_MASK; 362 363 ivpu_dbg(vdev, MMU, "STRTAB alloc: dma=%pad dma_q=%pad size=%zu\n", 364 &strtab->dma, &strtab->dma_q, size); 365 366 return 0; 367 } 368 369 static int ivpu_mmu_cmdq_alloc(struct ivpu_device *vdev) 370 { 371 struct ivpu_mmu_info *mmu = vdev->mmu; 372 struct ivpu_mmu_queue *q = &mmu->cmdq; 373 374 q->base = dmam_alloc_coherent(vdev->drm.dev, IVPU_MMU_CMDQ_SIZE, &q->dma, GFP_KERNEL); 375 if (!q->base) 376 return -ENOMEM; 377 378 q->dma_q = IVPU_MMU_Q_BASE_RWA; 379 q->dma_q |= q->dma & IVPU_MMU_Q_BASE_ADDR_MASK; 380 q->dma_q |= IVPU_MMU_Q_COUNT_LOG2; 381 382 ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n", 383 &q->dma, &q->dma_q, IVPU_MMU_CMDQ_SIZE); 384 385 return 0; 386 } 387 388 static int ivpu_mmu_evtq_alloc(struct ivpu_device *vdev) 389 { 390 struct ivpu_mmu_info *mmu = vdev->mmu; 391 struct ivpu_mmu_queue *q = &mmu->evtq; 392 393 q->base = dmam_alloc_coherent(vdev->drm.dev, IVPU_MMU_EVTQ_SIZE, &q->dma, GFP_KERNEL); 394 if (!q->base) 395 return -ENOMEM; 396 397 q->dma_q = IVPU_MMU_Q_BASE_RWA; 398 q->dma_q |= q->dma & IVPU_MMU_Q_BASE_ADDR_MASK; 399 q->dma_q |= IVPU_MMU_Q_COUNT_LOG2; 400 401 ivpu_dbg(vdev, MMU, "EVTQ alloc: dma=%pad dma_q=%pad size=%u\n", 402 &q->dma, &q->dma_q, IVPU_MMU_EVTQ_SIZE); 403 404 return 0; 405 } 406 407 static int ivpu_mmu_structs_alloc(struct ivpu_device *vdev) 408 { 409 int ret; 410 411 ret = ivpu_mmu_cdtab_alloc(vdev); 412 if (ret) { 413 ivpu_err(vdev, "Failed to allocate cdtab: %d\n", ret); 414 return ret; 415 } 416 417 ret = ivpu_mmu_strtab_alloc(vdev); 418 if (ret) { 419 ivpu_err(vdev, "Failed to allocate strtab: %d\n", ret); 420 return ret; 421 } 422 423 ret = ivpu_mmu_cmdq_alloc(vdev); 424 if (ret) { 425 ivpu_err(vdev, "Failed to allocate cmdq: %d\n", ret); 426 return ret; 427 } 428 429 ret = ivpu_mmu_evtq_alloc(vdev); 430 if (ret) 431 ivpu_err(vdev, "Failed to allocate evtq: %d\n", ret); 432 433 return ret; 434 } 435 436 static int ivpu_mmu_reg_write_cr0(struct ivpu_device *vdev, u32 val) 437 { 438 REGV_WR32(IVPU_MMU_REG_CR0, val); 439 440 return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US); 441 } 442 443 static int ivpu_mmu_reg_write_irq_ctrl(struct ivpu_device *vdev, u32 val) 444 { 445 REGV_WR32(IVPU_MMU_REG_IRQ_CTRL, val); 446 447 return REGV_POLL_FLD(IVPU_MMU_REG_IRQ_CTRLACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US); 448 } 449 450 static int ivpu_mmu_irqs_setup(struct ivpu_device *vdev) 451 { 452 u32 irq_ctrl = IVPU_MMU_IRQ_EVTQ_EN | IVPU_MMU_IRQ_GERROR_EN; 453 int ret; 454 455 ret = ivpu_mmu_reg_write_irq_ctrl(vdev, 0); 456 if (ret) 457 return ret; 458 459 return ivpu_mmu_reg_write_irq_ctrl(vdev, irq_ctrl); 460 } 461 462 static int ivpu_mmu_cmdq_wait_for_cons(struct ivpu_device *vdev) 463 { 464 struct ivpu_mmu_queue *cmdq = &vdev->mmu->cmdq; 465 int ret; 466 467 ret = REGV_POLL_FLD(IVPU_MMU_REG_CMDQ_CONS, VAL, cmdq->prod, 468 IVPU_MMU_QUEUE_TIMEOUT_US); 469 if (ret) 470 return ret; 471 472 cmdq->cons = cmdq->prod; 473 474 return 0; 475 } 476 477 static int ivpu_mmu_cmdq_cmd_write(struct ivpu_device *vdev, const char *name, u64 data0, u64 data1) 478 { 479 struct ivpu_mmu_queue *q = &vdev->mmu->cmdq; 480 u64 *queue_buffer = q->base; 481 int idx = IVPU_MMU_Q_IDX(q->prod) * (IVPU_MMU_CMDQ_CMD_SIZE / sizeof(*queue_buffer)); 482 483 if (!CIRC_SPACE(IVPU_MMU_Q_IDX(q->prod), IVPU_MMU_Q_IDX(q->cons), IVPU_MMU_Q_COUNT)) { 484 ivpu_err(vdev, "Failed to write MMU CMD %s\n", name); 485 return -EBUSY; 486 } 487 488 queue_buffer[idx] = data0; 489 queue_buffer[idx + 1] = data1; 490 q->prod = (q->prod + 1) & IVPU_MMU_Q_WRAP_MASK; 491 492 ivpu_dbg(vdev, MMU, "CMD write: %s data: 0x%llx 0x%llx\n", name, data0, data1); 493 494 return 0; 495 } 496 497 static int ivpu_mmu_cmdq_sync(struct ivpu_device *vdev) 498 { 499 struct ivpu_mmu_queue *q = &vdev->mmu->cmdq; 500 u64 val; 501 int ret; 502 503 val = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_SYNC) | 504 FIELD_PREP(IVPU_MMU_CMD_SYNC_0_CS, 0x2) | 505 FIELD_PREP(IVPU_MMU_CMD_SYNC_0_MSH, 0x3) | 506 FIELD_PREP(IVPU_MMU_CMD_SYNC_0_MSI_ATTR, 0xf); 507 508 ret = ivpu_mmu_cmdq_cmd_write(vdev, "SYNC", val, 0); 509 if (ret) 510 return ret; 511 512 clflush_cache_range(q->base, IVPU_MMU_CMDQ_SIZE); 513 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod); 514 515 ret = ivpu_mmu_cmdq_wait_for_cons(vdev); 516 if (ret) { 517 u32 err; 518 519 val = REGV_RD32(IVPU_MMU_REG_CMDQ_CONS); 520 err = REG_GET_FLD(IVPU_MMU_REG_CMDQ_CONS, ERR, val); 521 522 ivpu_err(vdev, "Timed out waiting for MMU consumer: %d, error: %s\n", ret, 523 ivpu_mmu_cmdq_err_to_str(err)); 524 } 525 526 return ret; 527 } 528 529 static int ivpu_mmu_cmdq_write_cfgi_all(struct ivpu_device *vdev) 530 { 531 u64 data0 = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_CFGI_ALL); 532 u64 data1 = FIELD_PREP(IVPU_MMU_CMD_CFGI_1_RANGE, 0x1f); 533 534 return ivpu_mmu_cmdq_cmd_write(vdev, "CFGI_ALL", data0, data1); 535 } 536 537 static int ivpu_mmu_cmdq_write_tlbi_nh_asid(struct ivpu_device *vdev, u16 ssid) 538 { 539 u64 val = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_TLBI_NH_ASID) | 540 FIELD_PREP(IVPU_MMU_CMD_TLBI_0_ASID, ssid); 541 542 return ivpu_mmu_cmdq_cmd_write(vdev, "TLBI_NH_ASID", val, 0); 543 } 544 545 static int ivpu_mmu_cmdq_write_tlbi_nsnh_all(struct ivpu_device *vdev) 546 { 547 u64 val = FIELD_PREP(IVPU_MMU_CMD_OPCODE, CMD_TLBI_NSNH_ALL); 548 549 return ivpu_mmu_cmdq_cmd_write(vdev, "TLBI_NSNH_ALL", val, 0); 550 } 551 552 static int ivpu_mmu_reset(struct ivpu_device *vdev) 553 { 554 struct ivpu_mmu_info *mmu = vdev->mmu; 555 u32 val; 556 int ret; 557 558 memset(mmu->cmdq.base, 0, IVPU_MMU_CMDQ_SIZE); 559 clflush_cache_range(mmu->cmdq.base, IVPU_MMU_CMDQ_SIZE); 560 mmu->cmdq.prod = 0; 561 mmu->cmdq.cons = 0; 562 563 memset(mmu->evtq.base, 0, IVPU_MMU_EVTQ_SIZE); 564 clflush_cache_range(mmu->evtq.base, IVPU_MMU_EVTQ_SIZE); 565 mmu->evtq.prod = 0; 566 mmu->evtq.cons = 0; 567 568 ret = ivpu_mmu_reg_write_cr0(vdev, 0); 569 if (ret) 570 return ret; 571 572 val = FIELD_PREP(IVPU_MMU_CR1_TABLE_SH, IVPU_MMU_SH_ISH) | 573 FIELD_PREP(IVPU_MMU_CR1_TABLE_OC, IVPU_MMU_CACHE_WB) | 574 FIELD_PREP(IVPU_MMU_CR1_TABLE_IC, IVPU_MMU_CACHE_WB) | 575 FIELD_PREP(IVPU_MMU_CR1_QUEUE_SH, IVPU_MMU_SH_ISH) | 576 FIELD_PREP(IVPU_MMU_CR1_QUEUE_OC, IVPU_MMU_CACHE_WB) | 577 FIELD_PREP(IVPU_MMU_CR1_QUEUE_IC, IVPU_MMU_CACHE_WB); 578 REGV_WR32(IVPU_MMU_REG_CR1, val); 579 580 REGV_WR64(IVPU_MMU_REG_STRTAB_BASE, mmu->strtab.dma_q); 581 REGV_WR32(IVPU_MMU_REG_STRTAB_BASE_CFG, mmu->strtab.base_cfg); 582 583 REGV_WR64(IVPU_MMU_REG_CMDQ_BASE, mmu->cmdq.dma_q); 584 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, 0); 585 REGV_WR32(IVPU_MMU_REG_CMDQ_CONS, 0); 586 587 val = IVPU_MMU_CR0_CMDQEN; 588 ret = ivpu_mmu_reg_write_cr0(vdev, val); 589 if (ret) 590 return ret; 591 592 ret = ivpu_mmu_cmdq_write_cfgi_all(vdev); 593 if (ret) 594 return ret; 595 596 ret = ivpu_mmu_cmdq_write_tlbi_nsnh_all(vdev); 597 if (ret) 598 return ret; 599 600 ret = ivpu_mmu_cmdq_sync(vdev); 601 if (ret) 602 return ret; 603 604 REGV_WR64(IVPU_MMU_REG_EVTQ_BASE, mmu->evtq.dma_q); 605 REGV_WR32(IVPU_MMU_REG_EVTQ_PROD_SEC, 0); 606 REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, 0); 607 608 val |= IVPU_MMU_CR0_EVTQEN; 609 ret = ivpu_mmu_reg_write_cr0(vdev, val); 610 if (ret) 611 return ret; 612 613 val |= IVPU_MMU_CR0_ATSCHK; 614 ret = ivpu_mmu_reg_write_cr0(vdev, val); 615 if (ret) 616 return ret; 617 618 ret = ivpu_mmu_irqs_setup(vdev); 619 if (ret) 620 return ret; 621 622 val |= IVPU_MMU_CR0_SMMUEN; 623 return ivpu_mmu_reg_write_cr0(vdev, val); 624 } 625 626 static void ivpu_mmu_strtab_link_cd(struct ivpu_device *vdev, u32 sid) 627 { 628 struct ivpu_mmu_info *mmu = vdev->mmu; 629 struct ivpu_mmu_strtab *strtab = &mmu->strtab; 630 struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab; 631 u64 *entry = strtab->base + (sid * IVPU_MMU_STRTAB_ENT_SIZE); 632 u64 str[2]; 633 634 str[0] = FIELD_PREP(IVPU_MMU_STE_0_CFG, IVPU_MMU_STE_0_CFG_S1_TRANS) | 635 FIELD_PREP(IVPU_MMU_STE_0_S1CDMAX, IVPU_MMU_CDTAB_ENT_COUNT_LOG2) | 636 FIELD_PREP(IVPU_MMU_STE_0_S1FMT, IVPU_MMU_STE_0_S1FMT_LINEAR) | 637 IVPU_MMU_STE_0_V | 638 (cdtab->dma & IVPU_MMU_STE_0_S1CTXPTR_MASK); 639 640 str[1] = FIELD_PREP(IVPU_MMU_STE_1_S1DSS, IVPU_MMU_STE_1_S1DSS_TERMINATE) | 641 FIELD_PREP(IVPU_MMU_STE_1_S1CIR, IVPU_MMU_STE_1_S1C_CACHE_NC) | 642 FIELD_PREP(IVPU_MMU_STE_1_S1COR, IVPU_MMU_STE_1_S1C_CACHE_NC) | 643 FIELD_PREP(IVPU_MMU_STE_1_S1CSH, IVPU_MMU_SH_NSH) | 644 FIELD_PREP(IVPU_MMU_STE_1_PRIVCFG, IVPU_MMU_STE_1_PRIVCFG_UNPRIV) | 645 FIELD_PREP(IVPU_MMU_STE_1_INSTCFG, IVPU_MMU_STE_1_INSTCFG_DATA) | 646 FIELD_PREP(IVPU_MMU_STE_1_STRW, IVPU_MMU_STE_1_STRW_NSEL1) | 647 FIELD_PREP(IVPU_MMU_STE_1_CONT, IVPU_MMU_STRTAB_CFG_LOG2SIZE) | 648 IVPU_MMU_STE_1_MEV | 649 IVPU_MMU_STE_1_S1STALLD; 650 651 WRITE_ONCE(entry[1], str[1]); 652 WRITE_ONCE(entry[0], str[0]); 653 654 clflush_cache_range(entry, IVPU_MMU_STRTAB_ENT_SIZE); 655 656 ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]); 657 } 658 659 static int ivpu_mmu_strtab_init(struct ivpu_device *vdev) 660 { 661 ivpu_mmu_strtab_link_cd(vdev, IVPU_MMU_STREAM_ID0); 662 ivpu_mmu_strtab_link_cd(vdev, IVPU_MMU_STREAM_ID3); 663 664 return 0; 665 } 666 667 int ivpu_mmu_invalidate_tlb(struct ivpu_device *vdev, u16 ssid) 668 { 669 struct ivpu_mmu_info *mmu = vdev->mmu; 670 int ret = 0; 671 672 mutex_lock(&mmu->lock); 673 if (!mmu->on) 674 goto unlock; 675 676 ret = ivpu_mmu_cmdq_write_tlbi_nh_asid(vdev, ssid); 677 if (ret) 678 goto unlock; 679 680 ret = ivpu_mmu_cmdq_sync(vdev); 681 unlock: 682 mutex_unlock(&mmu->lock); 683 return ret; 684 } 685 686 static int ivpu_mmu_cd_add(struct ivpu_device *vdev, u32 ssid, u64 cd_dma) 687 { 688 struct ivpu_mmu_info *mmu = vdev->mmu; 689 struct ivpu_mmu_cdtab *cdtab = &mmu->cdtab; 690 u64 *entry; 691 u64 cd[4]; 692 int ret = 0; 693 694 if (ssid > IVPU_MMU_CDTAB_ENT_COUNT) 695 return -EINVAL; 696 697 entry = cdtab->base + (ssid * IVPU_MMU_CDTAB_ENT_SIZE); 698 699 if (cd_dma != 0) { 700 cd[0] = FIELD_PREP(IVPU_MMU_CD_0_TCR_T0SZ, IVPU_MMU_T0SZ_48BIT) | 701 FIELD_PREP(IVPU_MMU_CD_0_TCR_TG0, 0) | 702 FIELD_PREP(IVPU_MMU_CD_0_TCR_IRGN0, 0) | 703 FIELD_PREP(IVPU_MMU_CD_0_TCR_ORGN0, 0) | 704 FIELD_PREP(IVPU_MMU_CD_0_TCR_SH0, 0) | 705 FIELD_PREP(IVPU_MMU_CD_0_TCR_IPS, IVPU_MMU_IPS_48BIT) | 706 FIELD_PREP(IVPU_MMU_CD_0_ASID, ssid) | 707 IVPU_MMU_CD_0_TCR_EPD1 | 708 IVPU_MMU_CD_0_AA64 | 709 IVPU_MMU_CD_0_R | 710 IVPU_MMU_CD_0_ASET | 711 IVPU_MMU_CD_0_V; 712 cd[1] = cd_dma & IVPU_MMU_CD_1_TTB0_MASK; 713 cd[2] = 0; 714 cd[3] = 0x0000000000007444; 715 716 /* For global context generate memory fault on VPU */ 717 if (ssid == IVPU_GLOBAL_CONTEXT_MMU_SSID) 718 cd[0] |= IVPU_MMU_CD_0_A; 719 } else { 720 memset(cd, 0, sizeof(cd)); 721 } 722 723 WRITE_ONCE(entry[1], cd[1]); 724 WRITE_ONCE(entry[2], cd[2]); 725 WRITE_ONCE(entry[3], cd[3]); 726 WRITE_ONCE(entry[0], cd[0]); 727 728 clflush_cache_range(entry, IVPU_MMU_CDTAB_ENT_SIZE); 729 730 ivpu_dbg(vdev, MMU, "CDTAB %s entry (SSID=%u, dma=%pad): 0x%llx, 0x%llx, 0x%llx, 0x%llx\n", 731 cd_dma ? "write" : "clear", ssid, &cd_dma, cd[0], cd[1], cd[2], cd[3]); 732 733 mutex_lock(&mmu->lock); 734 if (!mmu->on) 735 goto unlock; 736 737 ret = ivpu_mmu_cmdq_write_cfgi_all(vdev); 738 if (ret) 739 goto unlock; 740 741 ret = ivpu_mmu_cmdq_sync(vdev); 742 unlock: 743 mutex_unlock(&mmu->lock); 744 return ret; 745 } 746 747 static int ivpu_mmu_cd_add_gbl(struct ivpu_device *vdev) 748 { 749 int ret; 750 751 ret = ivpu_mmu_cd_add(vdev, 0, vdev->gctx.pgtable.pgd_dma); 752 if (ret) 753 ivpu_err(vdev, "Failed to add global CD entry: %d\n", ret); 754 755 return ret; 756 } 757 758 static int ivpu_mmu_cd_add_user(struct ivpu_device *vdev, u32 ssid, dma_addr_t cd_dma) 759 { 760 int ret; 761 762 if (ssid == 0) { 763 ivpu_err(vdev, "Invalid SSID: %u\n", ssid); 764 return -EINVAL; 765 } 766 767 ret = ivpu_mmu_cd_add(vdev, ssid, cd_dma); 768 if (ret) 769 ivpu_err(vdev, "Failed to add CD entry SSID=%u: %d\n", ssid, ret); 770 771 return ret; 772 } 773 774 int ivpu_mmu_init(struct ivpu_device *vdev) 775 { 776 struct ivpu_mmu_info *mmu = vdev->mmu; 777 int ret; 778 779 ivpu_dbg(vdev, MMU, "Init..\n"); 780 781 drmm_mutex_init(&vdev->drm, &mmu->lock); 782 ivpu_mmu_config_check(vdev); 783 784 ret = ivpu_mmu_structs_alloc(vdev); 785 if (ret) 786 return ret; 787 788 ret = ivpu_mmu_strtab_init(vdev); 789 if (ret) { 790 ivpu_err(vdev, "Failed to initialize strtab: %d\n", ret); 791 return ret; 792 } 793 794 ret = ivpu_mmu_cd_add_gbl(vdev); 795 if (ret) { 796 ivpu_err(vdev, "Failed to initialize strtab: %d\n", ret); 797 return ret; 798 } 799 800 ret = ivpu_mmu_enable(vdev); 801 if (ret) { 802 ivpu_err(vdev, "Failed to resume MMU: %d\n", ret); 803 return ret; 804 } 805 806 ivpu_dbg(vdev, MMU, "Init done\n"); 807 808 return 0; 809 } 810 811 int ivpu_mmu_enable(struct ivpu_device *vdev) 812 { 813 struct ivpu_mmu_info *mmu = vdev->mmu; 814 int ret; 815 816 mutex_lock(&mmu->lock); 817 818 mmu->on = true; 819 820 ret = ivpu_mmu_reset(vdev); 821 if (ret) { 822 ivpu_err(vdev, "Failed to reset MMU: %d\n", ret); 823 goto err; 824 } 825 826 ret = ivpu_mmu_cmdq_write_cfgi_all(vdev); 827 if (ret) 828 goto err; 829 830 ret = ivpu_mmu_cmdq_write_tlbi_nsnh_all(vdev); 831 if (ret) 832 goto err; 833 834 ret = ivpu_mmu_cmdq_sync(vdev); 835 if (ret) 836 goto err; 837 838 mutex_unlock(&mmu->lock); 839 840 return 0; 841 err: 842 mmu->on = false; 843 mutex_unlock(&mmu->lock); 844 return ret; 845 } 846 847 void ivpu_mmu_disable(struct ivpu_device *vdev) 848 { 849 struct ivpu_mmu_info *mmu = vdev->mmu; 850 851 mutex_lock(&mmu->lock); 852 mmu->on = false; 853 mutex_unlock(&mmu->lock); 854 } 855 856 static void ivpu_mmu_dump_event(struct ivpu_device *vdev, u32 *event) 857 { 858 u32 ssid = FIELD_GET(IVPU_MMU_EVT_SSID_MASK, event[0]); 859 u32 op = FIELD_GET(IVPU_MMU_EVT_OP_MASK, event[0]); 860 u64 fetch_addr = ((u64)event[7]) << 32 | event[6]; 861 u64 in_addr = ((u64)event[5]) << 32 | event[4]; 862 u32 sid = event[1]; 863 864 ivpu_err(vdev, "MMU EVTQ: 0x%x (%s) SSID: %d SID: %d, e[2] %08x, e[3] %08x, in addr: 0x%llx, fetch addr: 0x%llx\n", 865 op, ivpu_mmu_event_to_str(op), ssid, sid, event[2], event[3], in_addr, fetch_addr); 866 } 867 868 static u32 *ivpu_mmu_get_event(struct ivpu_device *vdev) 869 { 870 struct ivpu_mmu_queue *evtq = &vdev->mmu->evtq; 871 u32 idx = IVPU_MMU_Q_IDX(evtq->cons); 872 u32 *evt = evtq->base + (idx * IVPU_MMU_EVTQ_CMD_SIZE); 873 874 evtq->prod = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC); 875 if (!CIRC_CNT(IVPU_MMU_Q_IDX(evtq->prod), IVPU_MMU_Q_IDX(evtq->cons), IVPU_MMU_Q_COUNT)) 876 return NULL; 877 878 clflush_cache_range(evt, IVPU_MMU_EVTQ_CMD_SIZE); 879 880 evtq->cons = (evtq->cons + 1) & IVPU_MMU_Q_WRAP_MASK; 881 REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, evtq->cons); 882 883 return evt; 884 } 885 886 void ivpu_mmu_irq_evtq_handler(struct ivpu_device *vdev) 887 { 888 bool schedule_recovery = false; 889 u32 *event; 890 u32 ssid; 891 892 ivpu_dbg(vdev, IRQ, "MMU event queue\n"); 893 894 while ((event = ivpu_mmu_get_event(vdev)) != NULL) { 895 ivpu_mmu_dump_event(vdev, event); 896 897 ssid = FIELD_GET(IVPU_MMU_EVT_SSID_MASK, event[0]); 898 if (ssid == IVPU_GLOBAL_CONTEXT_MMU_SSID) 899 schedule_recovery = true; 900 else 901 ivpu_mmu_user_context_mark_invalid(vdev, ssid); 902 } 903 904 if (schedule_recovery) 905 ivpu_pm_schedule_recovery(vdev); 906 } 907 908 void ivpu_mmu_irq_gerr_handler(struct ivpu_device *vdev) 909 { 910 u32 gerror_val, gerrorn_val, active; 911 912 ivpu_dbg(vdev, IRQ, "MMU error\n"); 913 914 gerror_val = REGV_RD32(IVPU_MMU_REG_GERROR); 915 gerrorn_val = REGV_RD32(IVPU_MMU_REG_GERRORN); 916 917 active = gerror_val ^ gerrorn_val; 918 if (!(active & IVPU_MMU_GERROR_ERR_MASK)) 919 return; 920 921 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_ABT, active)) 922 ivpu_warn_ratelimited(vdev, "MMU MSI ABT write aborted\n"); 923 924 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_PRIQ_ABT, active)) 925 ivpu_warn_ratelimited(vdev, "MMU PRIQ MSI ABT write aborted\n"); 926 927 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_EVTQ_ABT, active)) 928 ivpu_warn_ratelimited(vdev, "MMU EVTQ MSI ABT write aborted\n"); 929 930 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_CMDQ_ABT, active)) 931 ivpu_warn_ratelimited(vdev, "MMU CMDQ MSI ABT write aborted\n"); 932 933 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, PRIQ_ABT, active)) 934 ivpu_err_ratelimited(vdev, "MMU PRIQ write aborted\n"); 935 936 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, EVTQ_ABT, active)) 937 ivpu_err_ratelimited(vdev, "MMU EVTQ write aborted\n"); 938 939 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, CMDQ, active)) 940 ivpu_err_ratelimited(vdev, "MMU CMDQ write aborted\n"); 941 942 REGV_WR32(IVPU_MMU_REG_GERRORN, gerror_val); 943 } 944 945 int ivpu_mmu_set_pgtable(struct ivpu_device *vdev, int ssid, struct ivpu_mmu_pgtable *pgtable) 946 { 947 return ivpu_mmu_cd_add_user(vdev, ssid, pgtable->pgd_dma); 948 } 949 950 void ivpu_mmu_clear_pgtable(struct ivpu_device *vdev, int ssid) 951 { 952 ivpu_mmu_cd_add_user(vdev, ssid, 0); /* 0 will clear CD entry */ 953 } 954